In the fields of modern electronic measurement, communication systems and biomedicine, data acquisition and storage of broadband analog signals are often involved so that computers can further process data. In order to collect high-speed analog signals without distortion, according to the Nyquist theorem, the sampling frequency must be more than twice the signal frequency, but the anti-noise performance of the orthogonal sequence digital demodulation method in the electrical impedance multi-frequency and parametric imaging technology The number of sampling points per cycle of the signal is determined. The more sampling points, the higher the anti-noise performance. When the sampling signal frequency is very high, in order to sample more in one cycle of the sampled signal, the frequency of the sampling clock needs to be increased, but because the clock rate of the ADC device of the system cannot reach the required high frequency rate or storage processing speed, etc. To meet the requirements, we can use low-speed ADC devices to perform data acquisition on broadband analog signals through equivalent time sampling to make the system easy to implement.

1. The principle of equivalent time sampling

Equivalent time sampling technology transforms periodic or quasi-periodic high-frequency and fast signals into low-frequency slow signals. In the circuit, only the circuit before sampling has high frequency requirements, which greatly reduces the speed requirements of signal processing and display circuit after sampling conversion, and simplifies the design difficulty of the whole system. Equivalent time sampling is divided into sequential equivalent sampling, random equivalent sampling, and compound equivalent sampling combining these two methods. The sequential sampling in the equivalent time sampling implemented by two hardwares is introduced separately.

Below I will introduce the mixed time sampling in the equivalent time sampling, and the equivalent time sampling for periodic signals is shown in Figure 1(a).

The analog signal is sampled at the rising edges of the clock at the 2nd and 6th positions of the horizontal axis (time) in the first cycle, and the arrows in the figure indicate the sampling instants. Two points can be acquired in one cycle, followed by sampling the analog signal on the rising edge of the clock at the 11th and 15th positions on the horizontal axis of the second cycle. For the convenience of observation, the waveforms of the first to fifth periods are longitudinally arranged. It can be seen that the second cycle is one clock cycle later than the sampling point of the first cycle from the start point of the respective cycle. The third cycle is one clock cycle later than the sampling point of the second cycle from the start point of the third cycle. When sampling in the fourth cycle, we can find that the second sampling point has entered the fifth cycle. If we try to continue sampling in the above manner in the fifth cycle, that is, the fifth cycle is one clock cycle later than the sampling point of the fourth cycle from the starting point, then we will find that the sampling point sampled at the sampling starting point of the fifth cycle The value repeats the value sampled in the first cycle. So at this point we can stop sampling, then we get 8 data points collected in one cycle of sine waveform as shown in the sixth waveform diagram in Figure 1.

The theoretical basis when multiple points can be collected in each cycle in equivalent time sampling is given, and the theoretical basis when a single point can be collected in each cycle in equivalent time sampling is given.

We have reached or come close to meeting the processing speed clock requirement by dividing the high frequency clock. The clock signal with the smallest amplitude in Figure 1(b) is the sampling clock. The frequency-divided clock waveform can be clearly seen from Figure 1(b). The frequency-divided clock waveform samples the signal on the rising edge of the clock, and then the signal shown in Figure 1(a) will be obtained. Effective time sampling.

Principle of Equivalent Time Sampling Technology and Design of System Realized by FPGA

Figure 1 Schematic diagram of equivalent time sampling

2. Implementation of Equivalent Time Sampling Based on FPGA

2.1 System hardware implementation block diagram

The overall block diagram of the system is shown in Figure 2. The equivalent sampling clock controlled by the FPGA is connected to the clock part of the ADC device. The ADC device samples the wideband analog signal under the control of the clock, and the collected data is transmitted to the FIFO in the FPGA, and the FPGA re-samples the analog signal. The data in the FIFO in the FPGA is transferred to the FIFO in the USB, and then the USB pushes the FIFO data in the USB to the computer, and the computer reconstructs the received data. For the acquisition of the signal period, in the electrical impedance multi-frequency and parametric imaging technology, the period of the acquired signal is determined by the period of the transmitted signal, while for other complex periodic signals, the period can be obtained by the adopted method.

Principle of Equivalent Time Sampling Technology and Design of System Realized by FPGA

Figure 2 System scheme block diagram

2.2 Program Implementation of Equivalent Time Sampling Clock

Figure 3 shows the input and output ports of the FPGA-generated equivalent-time sampling block. CLK represents the input of the high-frequency clock, RESET represents the reset input, FREN_CON represents the frequency division control input used to control the frequency division of the high-frequency clock, and SANM_CONT represents how many high-frequency clocks the cycle of the analog signal contains The waveform of the signal, CLK_ADC_OUT represents the output clock port, which is connected to the clock input port of the analog-to-digital conversion device (ADC).

Principle of Equivalent Time Sampling Technology and Design of System Realized by FPGA

Figure 3 Equivalent time sampling block diagram

Here is the code to implement the clocks needed for equivalent time sampling:

SIGNAL SAMP_CONTS: STD_LOGIC_VECTOR (11

DOWNTO 0): = (OTHERS = "'0');

SIGNAL ADC_CLK_BANK: STD_LOGIC_VECTOR (11

DOWNTO 0): = (OTHERS = "'0');

SIGNAL CLK_CNT: INTEGER RANGE 0 TO 5000 : = 0;

SIGNAL CLK_TANK:STD_LOGIC:='0';

SIGNAL EN : STD_LOGIC := '1';

BEGIN

PROCESS(CLK, RESET)

BEGIN

IF RESET='1' THEN EN '0');

SAMP_CONTS '0');

EN

3. Waveform Simulation

The waveform simulation in Figure 4 is based on the assumption that one cycle of the analog signal is equal to 8 CLK clock cycles, CLK_ADC_OUT divides CLK by 4 and the duty cycle of the divided clock is 50%. The rising edge of the clock pointed to by arrow 1 marks the end of the first cycle, and the second cycle is entered after the rising edge. Similarly, the rising edge of the clock pointed to by arrow 2 marks the end of the second cycle, and after the rising edge marks the entry into the third cycle.

Principle of Equivalent Time Sampling Technology and Design of System Realized by FPGA

Figure 4 Waveform Simulation

Start timing from the first rising edge of CLK in the first cycle and divide CLK to get the CLK_ADC_OUT clock signal, and in the first cycle the second rising edge of CLK_ADC_OUT CLK_ADC_OUT level transition (there is a delay) , the level of CLK_ADC_OUT is toggled on the third rising edge in the second cycle, and the level of CLK_ADC_OUT is toggled on the fourth rising edge of CLK in the third cycle. It can be seen that the waveform simulation diagram is the realization of the clock expressed in the two diagrams of Figure 1 (a) and (b). It should be noted here that although there are 8 rising edges of CLK in the first cycle, it does not indicate the time between the rising edge of the CLK clock and the first rising edge of the CLK clock in the second cycle as indicated by arrow 1. waveform.

4 Conclusion

This paper introduces the basic principle of equivalent time sampling and the specific scheme of system implementation. Equivalent time sampling technology realizes the acquisition of wideband analog signals by using low-speed ADC devices, which reduces the system requirements for ADC devices and the complexity of system implementation. The equivalent time sampling technology introduced in this paper uses FPGA sampling technology, which greatly improves the sequential equivalent time sampling in which only one point can be collected in one cycle of the sampled signal, and can control the sampled signal. The number of acquisition points in one cycle of the acquisition signal can be controlled by frequency conversion according to the processing speed of the subsequent device. The equivalent sampling time is realized by FPGA, which reduces the complexity of the system implementation, and at the same time, it is very convenient to modify the code to make the debugging of the system easier.