feature

AD5390 : 16-channel, 14-bit voltage output DAC; AD5391: 16-channel, 12-bit voltage output DAC; AD5392: 8-channel, 14-bit voltage output DAC; guaranteed monotonic inline: ±1 LSB maximum (AD5391); ±3 LSB maximum (AD5390-5/AD5392-5); ±4 LSB max (AD5390-3/AD5392-3); On-chip 1.25 V/2.5 V, 10 ppm/°C reference; Temperature range: -40°C to +85°C; Rail-to-Rail Output Amplifier; Power-Down Mode Package Types: 64-lead LFCSP (9 mm x 9 mm); 52-lead LQFP (10 mm x 10 mm); User Interface; Serial SPI-, QSPI-, MICROWIRE- and DSP Compatible (with data readback); I2C compatible interface; synthesis function; channel monitor; synchronous output update via LDAC; ability to clear user-programmable code; amplifier boost mode to optimize slew rate; user-programmable offset and gain Adjustment; toggle mode enables square wave generation; thermal monitor; rugged 6.5 kV HBM and 2 kV FICDM ESD ratings.

application

Instrumentation and Industrial Control; Power Amplifier Control; Level Setting (ATE); Control Systems; Micro Electro Mechanical Systems (MEMs); Variable Optical Attenuators; Optical Transceivers (MSA 300 , XFP).

General Instructions

The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. These devices are available for 64-line LFCSP or 52-line LQFP. All channels have an on-chip output amplifier with rail-to-rail operation. All devices include an internal 1.25/2.5V, 10ppm/°C reference, an on-chip channel monitoring function that multiplexes the analog output to the common MON U OUT pin for external monitoring, and an output amplifier boost for optimized output amplifier slew rate pressure mode.

The AD5390/AD5391/AD5392 include a 3-wire serial interface with interface speeds in excess of 30 MHz, compatible with SPI® and QSPI 8482 ; MicroWire™, as well as a DSP interface standard and IC compatible interface supporting 400khz data transfer rates.

The input register followed by the DAC register provides double buffering, allowing the DAC output to update the input independently or simultaneously using the LDAC. Each channel has a programmable gain and offset adjustment register, allowing the user to fully calibrate any DAC channel.

Power consumption per channel is typically 0.25 mA.

the term

Relative Accuracy or Endpoint Linearity (INL) A measure of the maximum deviation of a straight line through the endpoints of a DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in least significant bits (lsb).

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal 1lsb change between any two adjacent codes. A differential nonlinearity of 1 LSB maximum is specified to ensure monotonicity.

Zero scale error

Error in DAC output voltage when all 0s are loaded into the DAC register. Ideally, load all 0s to the DAC, m=all 1s, c=2, VOUT (=0 V). n −1 zero scale) The zero scale error is the difference between the measured VOUT (actual) and VOUT (ideal) in mV. This is mainly caused by the offset of the output amplifier.

offset error

A measure of the difference between VOUT (actual) and VOUT (ideal) in mV in the linear region of the transfer function. Offset error is measured on the AD5390-5/AD5391-5/AD5392-5 with code 32 loaded in the DAC register and code 64 loaded in the DAC register on the AD5390-3/AD5391-3/AD5392-3.

gain error

The slope deviation of the DAC transfer characteristic from the ideal value, expressed in %FSR at no load on the DAC output. Gain error is specified in the linear region of the output range, between VOUT=10 mV and VOUT=AV−50 mV.

DC crosstalk

A dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s and vice versa) and output changes of all other DACs. It is expressed in LSB.

DC output impedance

Effective output source resistance. It is mainly based on packaged lead resistors.

Output voltage settling time

The time required for the output of a digital-to-analog converter to settle to a specified level for one quarter to one quarter full-scale input change. It is measured from a busy rising edge.

Digital-to-analog fault energy

The amount of energy injected into the analog output during major code transitions. It is designated as a fault region in nV-s. Measured by toggling the DAC register data between 0x1FF and 0x2000.

DAC-to-DAC crosstalk

A fault pulse that occurs at the output of one digital-to-analog converter due to a digital change from another digital-to-analog converter and a subsequent change in the analog output. Victim channels are loaded with mesoscale and DAC-to-DAC crosstalk is specified in nV-s.

digital crosstalk

A glitch pulse transmitted to the output of one converter due to a change in the DAC register code of the other converter is defined as digital crosstalk and is specified in nV-s.

digital feedthrough

When the device is not selected, high frequency logic activity on the device's digital inputs can capacitively couple across and through the device to appear as noise on the VOUT pin. It can also be connected along the power and ground wires. This noise is digital feedthrough.

Output Noise Spectral Density

This is random noise generated inside the measurement. Random noise is characterized by spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and measuring the noise at the output. It is measured in nV/(Hz) over a 1Hz bandwidth of 10kHz.

Typical performance characteristics

Function description

DAC Architecture

The AD5390/AD5391 are complete single-supply, 16-channel, voltage output DACs offering 14-bit and 12-bit resolution, respectively. The AD5392 is a complete single-supply, 8-channel, voltage output DAC that provides 14-bit resolution. All devices use 64-line LFCSP and 52-line LQFP and have serial interfaces. The family includes an internally selectable 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive buffered reference inputs (alternatively, these inputs can be driven with an external reference). All channels have an on-chip output amplifier with rail-to-rail output capable of driving a 5 kΩ load with 200 pF capacitance. The structure of a single DAC channel consists of 12- and 14-bit resistor string DACs and an output buffer amplifier operating in a gain of 2. This resistor string structure ensures the monotonicity of the DAC. The 12- and 14-bit binary digital codes loaded into the DAC registers determine at which node on the string the voltage is tapped before being input to the output amplifier. Each channel on these devices contains independent offset and gain control registers, allowing the user to digitally fine-tune the offset and gain.

These registers allow the user to calibrate errors throughout the signal chain (including the DAC) using the internal m and c registers, which hold the correction factors. All channels are double-buffered, allowing simultaneous updates of all channels using the LDAC pin. Figure 31 shows a block diagram of a single channel on the AD5390/AD5391/AD5392.

The digital input transfer function of each DAC can be expressed as:

Where: x2 is the data word loaded into the resistor string DAC; x1 is the 12-bit and 14-bit data word register written to the DAC input; m is the 12-bit and 14-bit gain factor (default is all 0x3FFE on AD5390/AD5392 and AD5391 LSB gain coefficient is zero; n = DAC resolution (AD5390/AD5392 and for AD5391, n = 12); c is 12-bit and 14-bit offset coefficient (default is 0x2000 on AD5390/AD5392 on AD5391 and 0x800).

The complete transfer function of these devices can be expressed as:

where: x2 is the data word loaded into the resistor string DAC.

VREF is the reference voltage applied to the REFIN/REFOUT pins on the DAC when an external reference is used (for specified performance on AD5390-5/AD5391-5/AD5392-5 and 1.25 V on AD5390-3/AD5391-3/ AD5392-3).

data decoding

AD5390/AD5392

The AD5390/AD5392 contain an internal 14-bit data bus. The input data is decoded from the data loaded into the REG1 and REG0 bits of the input serial register. As shown in Table 9.

Data from the serial input register is loaded into the addressing DAC input register, offset (c) register or gain (m) register. The format data, offset (c) and gain (m) register contents are shown in Table 10 to Table 12.

AD5391

The AD5391 contains an internal 12-bit data bus. The input data is decoded according to the value of the REG1 and REG0 bits loaded into the input serial register. The input data of the serial input register is loaded into the addressing DAC input register, offset (c) register or gain (m) register. The format data, offset (c) and gain (m) register contents are shown in Table 13 to Table 15.

interface

The AD5390/AD5391/AD5392 contain a serial interface that can be programmed to be DSP, SPI, and Microwire compatible, or IC compatible. The SPI/IC pins are used to select the interface mode.

To minimize device power consumption and on-chip digital noise, the interface is only fully powered up when the device is being written to, ie, on the falling edge of sync.

Serial interface compatible with DSP, SPI and MICROWIRE

The serial interface can operate with at least three wires in standalone mode or four wires in daisy-chain mode. Daisy chaining allows many devices to be cascaded together to increase the system channel count. The SPI/IC pins are tied to logic 1 pins to configure this mode of operation. The serial interface control pins are shown in Table 16.

Figures 2 through 4 show timing diagrams for serial writes to the AD5390/AD5391/AD5392 in standalone and daisy-chain modes. The 24-bit data word format for the serial interface is shown in Table 17 through Table 19. See Table 20 for a description of the bits.

solo mode

Independent mode is enabled by connecting the daisy-chain enable (DCEN) pin low. The serial interface can work with both continuous and non-continuous serial clocks. The first fall of the sync edge initiates the write cycle and resets the counter, which counts the number of serial clocks to ensure the correct number of bits is shifted into the serial shift register. Any other edges (except the falling edge) while synchronizing will be ignored until 24 bits are clocked. Once shifted in 24 bits, SCLK will be ignored. For another serial transfer, the counter must be reset with a synchronous falling edge.

Daisy Chain Mode

For systems with multiple devices, the SDO pins can be used to chain these devices together. This daisy-chain mode can be used for system diagnostics and to reduce the number of serial interface lines.

Daisy-chain mode is enabled by connecting the DCEN pin high. The first falling edge of synchronization begins the write cycle. SCLK is continuously applied to the input shift register when synchronization is low. If more than 24 clock pulses are applied, the data will fluctuate out of the shift register and appear on the SDO line. This data is clocked on the rising edge of SCLK and is valid on the falling edge. A multi-device interface is constructed by connecting the SDO of the first device to the DIN input of the next device in the chain. For each device in the system, 24 clock pulses are required. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5390/AD5391/AD5392 devices in the chain.

Sync will be high when the serial transfer to all devices is complete. This locks the input data in each device in the daisy chain and prevents any further data from entering the input shift register.

If a high sync occurs before 24 clocks into the section, it is considered a bad frame and the data is discarded. The serial clock can be a continuous clock or a gated clock. A continuous SCLK source can only be used if synchronization can be maintained at the correct number of clock cycles low. In gated clock mode, a burst clock containing an exact number of clock cycles must be used and synchronized high after the last clock to lock the data.

readback mode

Readback mode is invoked by setting the R/W bit = 1 in the serial input register write sequence. When R/W = 1, bits A3 to A0 are associated with bits REG1 and REG0 to select the register to be read. The remaining data bits in the write sequence are don't care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For single register reads, the NOP command can be used to clock out the data of the selected register on the SDO.

The readback graph in Figure 32 shows the readback sequence. For example, to read back the m register of channel 0 on the AD5390/AD5391/AD5392, the following sequence should be performed: First, write 0x404XXX to the AD5390/AD5391/AD5392 input registers. This configures the AD5390/AD5391/AD5392 in read mode and selects the m register for channel 0. Note that all data bits, from DB13 to DB0, are insignificant bits.

Next is the second write, the NOP condition, and 0x000000. During this write process, the data from the m register is clocked on the DOUT line, that is, the clocked data contains the data from the m register (from bit DB13 to bit DB0), and the first 10 bits contain the previously written address information. In readback mode, the sync signal must frame the data. Data is clocked on the rising edge of SCLK and valid on the falling edge of the SCLK signal. If SCLK idles high between the write and read operations of the readback, the first bit of data will be clocked on the falling edge of sync.

I2C serial interface

The AD5390/AD5391/AD5392 have an IC-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between dac and host at rates up to 400khz. Figure 6 shows the 2-wire interface timing diagram.

When the IC operating mode is selected by configuring the SPI/IC pins to logic 0, the device is connected to the IC bus as a slave device, i.e. the device does not generate a clock. The AD5390/AD5391/AD5392 have a 7-bit slave address of 10101 (AD1) (AD0). The five msbs are hardcoded and the two lsbs are determined by the state of the AD1 and AD0 pins. The hardware configuration tool for the AD1 and AD0 pins allows four of these devices to be configured on the bus.

I2C data transfer

One data bit is transferred every SCL clock cycle. During the high period of the SCL clock pulse, the data on SDA must remain stable. A change in SDA while SCL is high is the control signal that configures the start and stop conditions. Both SDA and SCL are pulled high by external pull-up resistors when the IC bus is not busy.

start and stop conditions

The master device initiates communication by issuing a start condition. The start condition is a high-to-low transition on SDA with SCL high. A stop condition is a low-to-high transition on SDA while SCL is high. A start condition from the master device signals the AD5390/AD5391/AD5392 to begin a transfer. Parking conditions left the bus empty. If a Repeated Start condition (Sr) is generated instead of a Stop condition, the bus will remain active.

Repeated Start Condition

A Repeated Start (Sr) condition indicates a change in data direction on the bus. Sr can be used when the bus master is writing to multiple IC devices and does not want to relinquish control of the bus.

Acknowledgement Bit (ACK)

The Acknowledgement Bit (ACK) is the 9th bit appended to any 8-bit data word. The receiving device always generates an ACK. The AD5390/AD5391/AD5392 devices generate an ACK by pulling SDA low during the ninth clock cycle when receiving an address or data.

Monitoring ACK allows detection of unsuccessful data transfers. Unsuccessful data transfers can occur if the receiving device is busy or has a system failure. If the data transfer is unsuccessful, the bus master should retry the communication.

AD5390/AD5391/AD5392 second lave address

The bus master initiates communication with the slave by issuing a START condition preceded by a 7-bit slave address. When idle, the AD5390/AD5391/AD5392 devices wait for a start condition and then wait for the slave address. The LSB of the address word is the read/write (R/W) bit. AD5390/AD5391/AD5392 devices are receivers only, and R/W=0 when communicating with them. After receiving the correct address 10101 (AD1) (AD0), the AD5390/AD5391/AD5392 issues an ACK by pulling SDA low for one clock cycle. The AD5390/AD5391/AD5392 have four user-programmable addresses determined by the AD1 and AD0 bits.

I2C write operation

There are three specific modes for writing data to the AD5390/AD5391/AD5392 DACs.

4-byte mode

When writing to the AD5390/AD5391/AD5392 DAC, an address byte begins (R/W = 0), after which the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by the pointer byte. This addresses the specific channel to be addressed in the DAC and the DAC also acknowledges it. Address bits A3 through A0 represent all channels on the AD5390/AD5391. Address bits A2 through A0 address all channels on the AD5392. Address bit A3 is a zero on the AD5392. Two bytes of data are then written to the DAC, as shown in Figure 33. A stop condition then occurs. This allows the user to update a single channel in the AD5390/AD5391/AD5392 at any time and requires four bytes of data to be transferred from the host.

3-byte mode

3-byte mode allows the user to update multiple channels in a write sequence without writing the device address byte each time. The device address byte is only needed once, and subsequent channel updates require pointer bytes and data bytes. In 3-byte mode, after the user starts with the address byte (R/W=0), the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by the pointer byte; this indicates the specific channel in the DAC to be addressed, which the DAC also acknowledges. Address bits A3 through A0 represent all channels on the AD5390/AD5391. Address bits A2 through A0 represent the AD5392. Address bit A3 is a zero on the AD5392. Next are two data bytes. REG1 and REG0 determine which registers to update.

If a stop condition is not sent after the data byte, the other channel can be updated by sending a new pointer byte followed by the data byte. This mode requires only three bytes to be sent to update any channel after the device is initially addressed and reduces software overhead when updating AD5390/AD5391/AD5392 channels. A stop condition exits this mode at any time. Figure 35 shows a typical configuration.

2-byte mode

2-byte mode allows users to update channels sequentially after initializing this mode. The device address byte is only needed once, and the address pointer is configured for auto-increment or burst mode.

The user must start with an address byte (R/W=0) after which the DAC confirms that it is ready to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) which initiates burst mode of operation. The address pointer is initialized to channel 0, and the data behind the pointer is loaded into channel 0. The address pointer is automatically incremented to the next address.

The REG0 and REG1 bits in the data byte determine which register to update. In this mode, after initialization, only two data bytes are required to update the channel. The channel address is automatically incremented from address 0 to the final address and then returns to normal 3-byte operation mode. This mode allows data transfer to all channels in a block and reduces software overhead when configuring all channels. A stop condition exits this mode at any time. Switching operating modes is not supported in 2-byte mode. Figure 36 shows a typical configuration.

AD5390/AD5391/AD5392 dedicated on-chip

function register

The AD5390/AD5391/AD5392 contain a number of Special Function Registers (SFRs) as shown in Table 21. sfr is addressed with REG1=0 and REG0=0 and decoded using address bits A3 to A0.

SFR command

NOP (no operation)

REG1=REG0=0, A3 to A0=0000

Does nothing, but in readback mode can be used to punch a card on the SDO for diagnostics. During NOP operation, the BUSY output is low.

Write CLR code

REG1=REG0=0, A3 to A0=0001

DB13 to DB0 = contains CLR data

Turning the CLR line low or performing a soft clear function loads the contents of the DAC register with the data contained in the user-configurable CLR register and sets VOUT 0 to VOUT 15 accordingly. This is not only useful for setting a specific output voltage under clear conditions, but also for calibration. For calibration, the user can load full-scale or zero-scale into the clear code register, then issue a hardware or software clear command to load this code to all DACs, eliminating the need for separate writes to all DACs. Defaults to all zeros at boot.

Soft coherent lidar

REG1=REG0=0, A3 to A0=0010

DB13 to DB0 = don't care

Executing this instruction executes the CLR, which has the same function as that provided by the external CLR pin. The DAC output is loaded with the data in the CLR code register. The time required to fully execute the soft CLR is 20 microseconds on the AD5390/AD5391 and 15 microseconds on the AD5392. It is represented by a busy low time.

soft power off

REG1=REG0=0, A3 to A0=1000

DB13 to DB0 = don't care

Executing this instruction will perform a global power down, which will put all channels into a low power mode, reducing analog current to a maximum of 1 µA and digital power consumption to a maximum of 20 µA. In power-down mode, the output amplifier can be configured as a high-impedance output or with a 100 kΩ load to ground. The contents of all internal registers are preserved in power-down mode.

soft start

REG1=REG0=0, A3 to A0=1001

DB13 to DB0 = don't care

This command is used to power up the output amplifier and internal reference signal. The time to exit power-down mode is 8 microseconds. Hardware power-down and software functions are combined internally in digital or functions.

soft reset

REG1=REG0=0, A5 to A0=001111

DB13 to DB0 = don't care

This command is used to implement a software reset. All internal registers are reset to their default values of m for full scale and c for zero scale. Clears the contents of the DAC registers and sets all analog outputs to 0 V. The soft reset activation time is up to 135 microseconds. A soft reset is only performed when the AD5390/AD5391/AD5392 are not in power-down mode.

monitor channel

REG1=REG0=0, A3 to A0=01010

DB13 to DB8=contains the data of the channel to be addressed

monitor

Monitoring is available on all devices. This feature includes a multiplexer addressable through the interface, allowing any channel output to be routed to the MON_OUT pin for monitoring with an external ADC. In addition to monitoring all output channels, two external inputs are provided that allow the user to monitor signals external to the AD5390/AD5391/AD5392. Before routing any channel to the MON_OUT pin, the channel monitor function must be enabled in the control register. On the AD5390 and AD5392 14-bit parts, DB13 through DB8 contain the channel address of the channel being monitored. In the 12-bit portion of the AD5391, DB11 through DB6 contain the channel addresses of the channels to be monitored. Select address 63 to represent the MON U OUT pin.

The channel monitor decoding of the AD5390/AD5392 is shown in Table 22, and the monitor decoding of the AD5391 is shown in Table 23.

control register write

Table 24 shows the control register contents for the AD5390 and AD5392. Table 25 provides bit descriptions. Note that REG1=REG0=0, A3 to A0=1100, and DB13 to DB0 contain control register data.

Table 26 shows the control register contents of the AD5391. Table 27 provides bit descriptions. Note that REG1=REG0=0, A3 to A0=1100, and DB13 to DB0 contain control register data.

hardware function

Reset function

Turning the reset line down resets all internal registers to their power-on-reset state. Reset is a negative edge sensitive input. The default value corresponds to m at full scale, and c at zero scale. The contents of all DAC registers are passed by setting the output to 0 V. This sequence takes up to 270µs. The falling edge of reset initiates the reset process. Busy goes low for the duration and returns high after reset is complete. When busy is low, all interfaces are disabled and all LDACs ignore pulses. When BUSY returns high, the part continues normal operation and the state of the reset pin is ignored until the next falling edge is detected. Only perform reset mode when the hardware AD5390/AD5391/AD5392 is not powered down.

Asynchronous clear function

CLR is negative edge triggered and busy will go low for the duration of CLR execution. Lowering the CLR line clears the contents of the DAC register to be contained in the user-configurable CLR register and sets the analog output accordingly. This function can be used for system calibration to load zero scale and full scale together to all channels. This execution time for the CLR is 20µs on the AD5390/AD5391 and 15µs on the AD5392.

Busy and LDAC functions

BUSY is a digital CMOS output that indicates the AD5390/AD5391/AD5392 devices. Busy with internal computation of x2 data. If busy is low, this event is stored. The user can keep the LDAC input permanently low, in which case the DAC output is updated as soon as it is busy. Busy also goes low during power-on reset and when a falling edge is detected on the reset pin. During this time, all interfaces are disabled and any events on the LDAC are ignored.

The AD5390/AD5391/AD5392 contain an extra feature which, unless its x2 register has been written to since the last time LDAC was low. Normally, when LDAC is low, the DAC register is filled with the contents of the x2 register. However, these devices will only update the DAC registers when the x2 data has changed, thus eliminating unwanted digital crosstalk.

power-on reset

The AD5390/AD5391/AD5392 contain a power-on-reset generator and state machine. A power-on reset resets all registers to a predefined state and the analog outputs are configured as high-impedance outputs. During power-on reset, the busy pin goes low, preventing data from being written to the device.

power outage

The AD5390/AD5391/AD5392 include a global power-down feature that puts all channels into a low-power mode, reducing analog power consumption to a maximum of 1 μA and digital power consumption to a maximum of 20 μA. In power-down mode, the output amplifier can be configured as a high-impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are preserved in power-down mode. When exiting power-down, the settling time of the amplifier elapses before the output settles to its correct value.

Microprocessor interface

AD5390/AD5391/AD5392T o MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0, clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the MC68HC11 drives the SCLK of the AD5390/AD5391/AD5392, the MOSI output drives the serial data line (DIN) of the AD5390/AD5391/AD5392, and the MISO input is driven by D. The sync signal is derived from the port line (PC7). When data is sent to the AD5390/AD5391/AD5392, the sync line is taken low (PC7). Data displayed on the MOSI output is valid on the falling edge of SCK. Serial data from the MC8HC11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle.

AD5390/AD5391/AD5392T o Picture 16C6X/7x

The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON) - see the PIC16/17 Microcontroller User's Manual.

In Figure 38, I/O port RA1 is used for pulse synchronization and enables the serial port of the AD5390/AD5391/AD5392. The microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, three consecutive read/write operations are required, depending on the mode. Figure 38 shows the connection diagram.

AD5390/AD5391/AD5392 to 8051

The AD5390/AD5391/AD5392 require a clock that is synchronized with the serial data. Therefore, the 8051 serial interface must operate in mode 0. In this mode, serial data is entered and exited through RxD and a shift clock is output on TxD. Figure 39 shows how the 8051 connects to the AD5390/AD5391/AD5392. Because the AD5390/AD5391/AD5392 shift data out on the rising edge of the shift clock and latch the data on the falling edge, the shift clock must be inverted. The AD5390/AD5391/AD5392 require their data to have the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.

AD5390/AD5391/AD5392 to ADSP-BF527

Figure 40 shows the serial interface between the AD5390/AD5391/AD5392 and the ADSP-BF527. The ADSP-BF527 should be set to operate in motion transmission alternate frame mode. The ADSP-BF527 SPORT is programmed through motion control registers and should be configured as follows: internal clock operation, active low frame, and 16-bit word length. After enabling motion, a transfer is initiated by writing a word to the Tx register.

application information

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5390/AD5391/AD5392 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5390/AD5391/AD5392 are in a system where multiple devices require an AGND to DGND connection, this connection should only be made at one point. The star ground point should be as close as possible to the device.

For power supplies with multiple pins (AV, AVCC), it is recommended to connect these pins together. The AD5390/AD5391/AD5392 should have adequate supply bypassing of 10µF in parallel, and 0.1µF on each supply should be as close to the package as possible, ideally right across the device. The 10µF capacitors are of the tantalum bead type. The 0.1µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as a common ceramic type that provides a high frequency, low impedance path to ground to handle transient currents caused by internal logic switching.

The power supply lines to the AD5390/AD5391/AD5392 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power supply lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the DIN and SCLK lines helps reduce crosstalk between them (not needed on multi-layer boards because there is a separate ground plane, but separating the lines helps reduce crosstalk).

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Micro-stripe technology is by far the best, but dual panels are not always possible. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

Power sequence

For proper operation, please use DVD disc first, then use AVDD at the same time or use within 10ms of DVD disc. This ensures that the power-on reset circuit sets the registers to their default values and holds the analog output at 0 V until a valid write occurs. A hardware reset is issued when AVDD cannot be applied within 10 ms of DVDD. This will trigger the power-on reset circuit and load the default register values. In the case where the initial power supply has the same or lower voltage as the second power supply, a Schottky diode can be used to temporarily supply power until the second power supply is turned on. Table 28 lists the power supply sequence and recommended diode connections. Alternatively, a load switch such as the ADP196 can be used to delay the first power supply until the second power supply is turned on. Figure 43 shows a typical configuration using the ADP196. In this case, AV is applied first. This voltage does not appear on the AVDD pin of the AD5390/AD5391/AD5392 until DVD is applied and the EN pin is raised. The results show that both AVDD and DVDD are suitable for the AD5390/AD5391/AD5392.

Typical Configuration Circuit

Figure 45 shows a typical configuration of the AD5390/AD5391/AD5392 when used with external references. In the circuit shown, all a GND, SIGNAL-GND, and DAC-GND pins are connected to a common AGND. AGND and DGND are connected together on the AD5390/AD5391/AD5392 devices. At power-up, the AD5390/AD5391/AD5392 default to external reference operation. All AV lines are connected together and driven by the same 5V supply. 0.1µF ceramic and 10µF tantalum capacitors are recommended for decoupling close to the device. In this application, the reference for the AD5390-5/AD5391-5/AD5392-5 is provided externally from the ADR421 or ADR431 2.5 V reference.

External references for the AD5390-3/AD5391-3/AD5392-3 include the ADR280 1.2 V reference. The reference should be disconnected at the re-output/re-input pins of the device using a 0.1µF capacitor.

Figure 46 shows a typical configuration when using internal references. At power-up, the AD5390/AD5391/AD5392 default to external references; therefore, internal references need to be configured and turned on by writing to the AD5390/AD5391/AD5392 control registers. On the AD5390/AD5392, control register Bit CR12 allows the user to select the reference voltage; Bit CR10 selects the internal reference voltage. It is recommended to use 2.5V reference voltage when AV=5V, and 1.25V reference voltage when AVDD=3V. On the AD5391, control register bit CR10 allows the user to select the reference voltage; bit CR8 is used to select the internal reference voltage.

The AD5390/AD5391/AD5392 contain an internal power-on reset circuit with a 10-millisecond power-down time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD5390/AD5391/AD5392 during initialization to ensure that the calibration data is properly loaded into the device.

AD5390/AD5391/AD5392 Monitoring Function

The AD5390 includes a channel monitor function consisting of a multiplexer addressed through the interface, allowing any channel output to be routed to this pin for monitoring with an external ADC. Before routing any channel to the MON_OUT pin, the channel monitor function must be enabled in the control register.

Table 22 and Table 23 contain the decoding information required to route any channel on the AD5390, AD5391, and AD5392 to the MON_OUT pin. Select the MON_OUT pin of the three states of channel address 63. The AD5390/AD5391/AD5392 also contain two monitor input pins named MON_IN 1 and MON_IN 2. Users can connect external signals to

These pins, under software control, can be multiplexed to monitors for monitoring purposes. Figure 47 shows a typical supervisory circuit implemented using a 12-bit SAR ADC in a 6-lead SOT package. The external reference input is connected to MON_IN 1 for easy monitoring. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.

Switch mode function

The toggle mode feature allows the output signal to be generated using the LDAC control signal that toggles between the two DAC data registers. This function is configured using the SFR control register as follows: Write to the specified control register using a write of REG1=REG0=0, A3 to A0=1100. The toggle mode function is enabled in groups of eight channels using Bits CR3 and CR2 in the AD5390/AD5392 control register, and using Bits CR1 and CR0 in the AD5391 control register. (See the Control Register Write section.) Figure 48 shows a block diagram of the toggle mode implementation. Each DAC channel on the AD5390/AD5391/AD5392 contains A and B data registers. Note that the B register can only be loaded when toggle mode is enabled.

To configure the AD5390/AD5391/AD5392 to switch operating modes, the sequence of events is as follows:

1. Enable toggle mode for the desired channel via the control register.

2. Load data into all A registers.

3. Load data into all B registers.

4. Apply LDAC.

LDAC is used in determining the analog output. The first LDAC configures the output to reflect the data in the A register. This mode offers significant advantages if the user wishes to generate square waves at the outputs of all channels, which may be necessary to drive liquid crystal-based variable optical attenuators.

For example, when configuring the AD5390, the user writes to the control register and sets CR3=1 and CR2=1, thereby enabling switch mode operation in two of the eight groups. The user must load data into all 16 A and B registers. Toggling the LDAC sets the output value to reflect the data in the A and B registers, and the frequency of the LDAC determines the frequency of the square wave output. The first LDAC loads the contents of the A register into the DAC register. Switch mode is disabled through the control register; the first LDAC after switch mode is disabled updates the output with the data contained in the A register.

Thermal monitoring function

The AD5390/AD5391/AD5392 feature a temperature shutdown to protect the chip when multiple outputs are shorted. The short-circuit current of each output amplifier is typically 40 mA. Operating the AD5390/AD5391/AD5392 at 5 V will result in 200 mW/shorted amplifier power dissipation. This results in additional watts of power dissipation when five channels are shorted. For 52-lead LQFP, theta is typically 44°C/W.

The thermal monitor is enabled by the user using CR8 in the AD5390/AD5392 control register and CR6 in the AD5391 control register. The output amplifiers on the AD5390/AD5391/AD5392 will automatically power down if the die temperature exceeds approximately 130°C. After a thermal shutdown, if the temperature drops below 130°C, the user can re-enable the part by performing a soft-start or by turning off the thermal monitoring function through the control register.

Power Amplifier Control

The design of multi-stage power amplifiers requires a large number of settings in the operation and control of the output stage. The AD5390/AD5391/AD5392 are ideal for these applications due to their small size (LFCSP) and integration of 8 and 16 channels, offering 12 and 14 bit resolution. Figure 49 shows a typical transmitter architecture where the AD5390/AD5391/AD5392 DACs can be used for the following control circuits: I control, average power control (APC), peak power control (PPC), transmit gain control (TGC), and audio level Control (ALC). DACs are also required for variable voltage attenuators, phase shifter control, and DC setpoint control throughout the amplifier design.

Process Control Applications

The AD5390-5/AD5391-5/AD5392-5 are ideal for process control applications because it offers a combination of 8 and 16 channels and 12- and 14-bit resolution. These applications typically require output voltage ranges of 0 V to 5 V ± 5 V, 0 V to 10 V ± 10 V, as well as current sink and power supply functions. The AD5390-5/AD5391-5/AD5392-5 operate from a 5V supply, therefore, external signal conditioning is required to achieve the output ranges described here. Figure 50 shows a configuration to achieve these output ranges. The main advantages of using the AD5390-5/AD5391-5/AD5392-5 in these applications are: small package size, pin compatibility upgradeable from 12-bit to 14-bit, on-chip 2.5V reference voltage, and maximum temperature coefficient of 10ppm /°C, and excellent accuracy specifications. The AD5390-5/AD5391-5/AD5392-5 contain per-channel offset and gain registers so the user can perform system-level calibration on a per-channel basis.

Optical fiber communication transceiver module

The AD5390-3/AD5391-3/AD5392-3 are ideal for optical transceiver applications. For example, in a 300-pin MSA application, digital-to-analog converters are required to control laser power, APD bias, and modulator amplitude. The module's analog outputs require diagnostic information. The AD5390-3/AD5391-3/AD5392-3 offer a combination of 8/16 channels, 12/14 bits of resolution in a 64-lead LFCSP, and operate from a 2.7 V to 5.5 V supply voltage and internal reference. The AD5390-3/AD5391-3/AD5392-3 also feature IC compatibility and an SPI interface, making them ideal components in these applications. Figure 51 shows a typical configuration in an optical transceiver application.

Dimensions