Today's embedded products have become more complex and more advanced than they were just a few years ago. The design itself can include an FPGA and a single graphics processing unit (GPU), plus multiple connection ports for video termination, USB, wireless networking, and high-speed wired Ethernet, industrial Modbus, or fieldbus. Each processor and corresponding subsystem requires a unique frequency and type that is not associated with other clocks, and therefore, requires their own clock signal. Designing a clock system that can generate these distinct and required precision performances and distribute them to their respective loads is a new challenge among all the problems that product design engineers face.

A straightforward and obvious way to provide these clocks seems to be as simple as taking as many clock generator ICs as needed and placing them near various target loads on the PC board, or a single clock driven by a master clock The tree structure, as shown in Figure 1. This approach can, at least in theory, solve the problem of multiple clocks, because the needs of each load device can be met by tailor-made clock signals. Also, because each clock source is located close to its load, crosstalk between clocks and between clocks and signals is reduced, minimizing additional clock jitter and distortion issues.

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 1: Using a single master clock along with a clock tree with local clock generators is one way to provide as many local clocks as needed, but this has cost (BOM, price, footprint) and performance implications and must be carefully Research.

A solution with one clock IC per target load may seem attractive, but there are many disadvantages, such as:

1. The use of multiple separate clock generator ICs directly leads to higher BOM (Bill of Materials) costs, as well as the logistical issues of managing and procuring these different ICs.

2. Requires large PC board space, a problem that is limited in almost every design.

3. If a separate, single-output clock generator is used instead of a distributed clock tree, each clock requires its own crystal, which increases cost and board space.

4. Using a "clock tree" to generate the final multiple clocks increases cost, footprint, clock jitter, and error accumulation.

5. Using multiple ICs will increase the overall power consumption.

6. When using multiple clock generator ICs, each new design has a different board layout and clock components, making it difficult to reuse the system design across different products in the company's product line.

How important each factor is in a given situation depends on the specific design, its priorities, and various tradeoffs. In a multiprocessor system, the decision to use a clock generator plus a crystal for each unique clock required has many unintended consequences.

Advantages of the alternative

Fortunately, there is another approach that can largely overcome the disadvantages of using multiple separate clock generator ICs in multiprocessor designs. A multi-output, programmable clock generator can provide multiple independent outputs via a single crystal, thus replacing two, four, or more clocks. These ICs are available in a variety of output options, configurations, and frequency ranges, as well as for a variety of applications.

When selecting a multiple-output clock generator, it is critical to match its performance to the needs of various clock loads. In many designs, the various loads have not only different frequencies, but of course different voltages, formats, rise/fall time maximums, and jitter specifications. A high-end FPGA or SoC device will have more stringent clocking requirements than a lower-speed communication link used in the same design, but the designer will want to choose a single clock generator IC to meet all the different needs.

The latest generation of programmable clock generators can achieve these goals, especially some of the more difficult requirements. For example, Xilinx's Virtex-6 and Virtex-7 FPGAs feature transceivers with data rates of 480 Mbps to 6.6 Gbps, 2.488 Gbps to 11.18 Gbps, respectively, a PCI Express Base with raw data rates of up to 5.0 Gbps per lane, and a PCI Express Base that supports 10/ An Ethernet MAC module for a 100/1000 Mbps link, as shown in Figure 2.

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 2: FPGAs such as the Virtex 6 from Xilinx have high functional density and very high bandwidth data links, a 100GE MAC optical interface with framing, enhanced forward error correction (EFEC), and two Virtex -6 HX565T FPGA ASIC (or backplane) interface through Interlaken bus.

In order to meet the needs of designers to realize circuit design based on these FPGAs, IDT has introduced the VersaClock6 series programmable clock generator, as shown in Figure 3. The VersaClock6 clock generator provides 2 to 8 configurable outputs (selectable as LVDS or LVPECL) and 2, 3, or 4 one-time programmable (OTP) configurations, depending on the specific device selected. All clock generators include a fractional output divider architecture for maximum flexibility and can generate any frequency between 1 and 350MHz. The most notable feature of this family is the guaranteed root mean square (RMS) phase jitter specification well below 500 fs (0.5ps), as shown in Figure 4.

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 3: IDT's VersaClock 6-series clock generators feature 2 to 8 configurable LVDS or LVPECL outputs, each capable of user-programmable frequencies between 1 and 350 MHz.

Application research of multi-output programmable clock generator based on VersaClock6 series

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 4: Using 156.25 and 312.5MHz reference clocks, the measured phase jitter is slightly higher than 400fs (0.4ps) and 350fs (0.35ps) rms, respectively, as these bit noise curves show, exceeding the state-of-the-art FPGA's Require.

Demonstrate its advantages with application examples

Designs that must support the SMPTE 424 standard are good examples of the benefits of using a programmable multi-output device. The SMPTE 424 standard, also known as 3G-SDI, has very tight eye-diagram jitter specifications for high-performance 3 Gbps SerDes (serializer/deserializer) functions to meet desired bit error rate (BER) targets. [SMPTE is the Society of Motion Picture and Television Engineers, an internationally recognized standardization body that manages specifications including a high-speed serial physical interface for digital television transmission, commonly referred to as SDI or Serial Data Interface]. The main mandatory requirements include:

Timing jitter 2.0 UI max, peak-to-peak, frequency range from 10Hz to 100kHz

Alignment jitter specification (Alignment jitter) 0.3 UI maximum, peak-to-peak, frequency range from 100 kHz to 297 MHz, 0.2 UI recommended (one unit interval (UI) is the time interval between two adjacent signal transitions, which is the clock frequency reciprocal of ).

Adding to the technical challenges, many broadcast video designs need to support both the NTSC and PAL HDTV standards, which means they need to have both 148.5MHz and 148.5/(1.001)MHz reference clocks. Additionally, the trend for broadcast video products to support Video over IP (VoIP) means that these designs may also need to support 10GEPHY (10 Gigabit Ethernet Physical Layer), so an additional reference clock operating at 156.25 MHz is usually required.

Xilinx 7 series FPGAs are often selected for these SMPTE-compliant designs due to their integrated, high-performance GTX/GTH/GTP transceivers. In order to meet the SMPTE 424 eye jitter specification, Xilinx has specified very stringent dBc/Hz phase noise requirements for the reference clock used to drive these SerDes functions. If the same Xilinx 7 series GTX/GTH/GTP transceivers are also used to achieve 10 Gbps SerDes, the very tight dBc/Hz phase noise requirement is also critical. These non-integer-related clock frequencies (148.5 MHz, 148.351648 MHz, and 156.25 MHz), when combined with the very stringent phase noise requirements of each clock, mean that providing an integrated clock solution is a significant challenge Task.

Fortunately, there is already a single device that can combine all these high-performance clocks in a single device: IDT's Universal Frequency Translator (UFT) family of high-end phase-locked loops (PLLs). This family of products can be used as a high-performance synthesizer, requiring only a simple, fundamental-mode parallel-resonant crystal as its input reference. All products in the UFT family support one or two different pin-selectable configurations per PLL, and these can be preloaded into internal one-time programmable (OTP) nonvolatile memory for automatic run, or use an I2C serial interface to set the desired frequency translation configuration.

For SMPTE 424 designs, IDT's 8T49N241 can be used as a high-performance, quad-output synthesizer, as shown in Figure 5, where the board space savings and design complexity can be clearly seen. This family of clocking devices has the performance required by Xilinx 7 series reference clocks in such complex applications. Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 5: A single IDT general purpose frequency translation phase-locked loop (here 8T49N241) can be used as a high performance 4-output synthesizer capable of delivering the low jitter and high precision frequencies required by SMPTE, replacing 4 crystals and 4 generator IC.

Figure 6 shows a typical 156.25MHz output clock phase noise curve produced by an IDT UFT clock device. The phase noise curve is well below the phase noise level determined by Xilinx Action Note AR# 44549.

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 6: A typical phase noise curve for a 156.25 MHz output clock generated by IDT's UFT clock IC exceeds the noise requirements determined by the Xilinx AcTIon Note.

If the designer chooses to use a single clock generator IC with multiple outputs, many of the problems associated with using separate clock ICs disappear or become simpler. Additionally, by adding programmability to the clock IC, the same components and board layout can be reused for multiple products or upgraded products.

There is one thing that designers need to keep in mind when using a single clock IC. The physical location of the IC and the routing of the various outputs on the board to the corresponding loads must be modeled and simulated. These are necessary to maintain the integrity of the clock signal and keep the effects of crosstalk and noise, as well as jitter, low enough. Fortunately, simulation tools for high-speed signals and PCB layout are now available to accomplish these tasks and will also help ensure overall design performance for non-clocked signals.

Design Considerations for Tools, Ease of Use, etc.

Obviously, if a user-programmable, fully configurable clock generator IC cannot be easily programmed or configured, it will be a very frustrating thing for the user. IDT's TIming Commander software platform allows customers to configure and program devices through an intuitive and flexible graphical user interface (GUI).

Figure 7 shows a screenshot of the platform's GUI that configures the 8T49N241 as a high-performance quad-output synthesizer for SMPTE 424 applications. The combination of a fractional feedback PLL and a mix of integer and fractional output dividers allows the 8T49N241 to generate For all of these output frequencies, they have an additive synthesis error of 0 ppb (parts per billion), and the measured 10GE and SMPTE 424 clock phase noise performance meets the Xilinx 7 series requirements.

Application research of multi-output programmable clock generator based on VersaClock6 series

Figure 7: To configure the SMPTE design, the IDT TIming Commander GUI uses a combination of fractional feedback PLLs with a mix of integer and fractional output dividers to generate all desired output frequencies.

In addition, the in-system I2C programming mode can be used to program multiple output devices at power-up to override the one-time programmable memory configuration, thus reconfiguring the device if desired. Finally, the user can additionally program an independent spread spectrum function for each output pair to reduce system-level EMI/RFI levels and other related concerns, again depending on the device chosen.

User programmability is of great help to multiprocessor system designers in many ways, while also overcoming the drawbacks of using multiple separate, independent clock generators without compromising performance. User-programmable features enable a single device to support different types and load requirements, so questions like "Which clock is for which load type?" Of course, these devices can not only be customized in frequency, but also support some other key specifications, which can achieve the ideal balance of cost, performance and energy-efficient design, and the previous solutions often face the embarrassment of ignoring one and the other.