FPGA pin adjustment

With the continuous development of FPGA, its functions are more and more powerful, and it also brings great convenience to its wiring—the adjustment of pins.
For dense boards, you can no longer go around when routing, but adjust the signal according to the order of routing, and then correct the signal communication through software programming. There are a few considerations you must be familiar with before making adjustments to the FPGA pins.

FPGA Pinout Considerations

(1) As shown in Figure 12-1, when there is a VRN/VRP pin connected to a pull-up/pull-down resistor, it cannot be adjusted. The VRN/VRP pin provides a reference voltage for the internal circuit of the DCI, and the internal circuit of the DCI is based on this reference. The voltage-adjusted I/O output impedance is matched to the external reference resistor, R .

(2) Under normal circumstances, banks of the same voltage can be intermodulated, but some customers will require adjustment within the bank, so it is necessary to discuss with the customer before adjustment to avoid useless work.

(3) When making a difference, "P" and "N" correspond to positive and negative respectively, and cannot be adjusted with each other.

(4) The global clock should be placed on the P port of the global clock pin and cannot be adjusted casually.

Note the following before adjusting FPGA pins

Adjustment Tips for FPGA Pins

(1) In order to easily identify which Banks can be intermodulated, each Bank of the FPGA must be distinguished first. In the schematic editing interface, execute the icon command "Cross Probe", click a Bank of a certain FPGA, and directly jump to the corresponding Bank pin highlight in the PCB, then you can add it on a mechanical layer Mark and mark, as shown in Figure 12-2.

Note the following before adjusting FPGA pins

(2) According to the same operation method, the adjustment Bank can be marked on the PCB, as shown in Figure 12-3.

Note the following before adjusting FPGA pins

(3) After the above steps are completed, all the signal pins can be drawn out according to the normal BGA wiring method, and arranged in the order of wiring, but not connected, as shown in Figure 12-4, the flying leads are crossed , but not directly connected. Finally save all documents.

Note the following before adjusting FPGA pins

(4) In the PCB design interactive interface, execute the menu command "Project - Component Association" to match components, match all the left components to the right window, click the "Execute Update" button to execute the update, as shown in Figure 12-5 shown.

Note the following before adjusting FPGA pins

(5) Execute the menu command "Tools - Pin/Component Exchange - Configuration" to define and enable the switchable pin components. If a warning pops up, you must go back to step (4) to operate again, or execute Import PCB from Schematic operation, make the schematic diagram and PCB completely correspond, and then follow this step, otherwise the warning message shown in Figure 12-6 will pop up.

Note the following before adjusting FPGA pins

(6) Find the component number corresponding to the FPGA, check the enable state, double-click the component, create a Group operation for the swappable I/O attribute pins of the component, and click the "OK" button to complete the setting, as shown in the figure. 12-7.

Note the following before adjusting FPGA pins

(7) Execute the menu command "Tools - Pin/Component Swap - Interactive Pin/Network Swap", and click the previously docked signal trace to swap the wire sequence. Note: The "Project" project file must be saved before operation.

After the above steps are performed, the PCB pin swap is completed, and the specific effect is shown in Figure 12-8.

Note the following before adjusting FPGA pins

(8) After the PCB is exchanged and changed, it is necessary to de-import the network interaction into the schematic diagram, as shown in Figure 12-9, execute the menu command "Project - Project Options", and check the de-import option "Change Schematic Pins".

Note the following before adjusting FPGA pins

(9) In the PCB design interactive interface, execute the "Update Schematic in Project" command, and follow the same method as the previous schematic diagram to import the PCB to complete the PCB import schematic diagram.

Because some schematic drawing methods or formats are wrong, the back labeling may be incomplete or incomplete. It is recommended to use the positive import method to check it again after back labeling or directly manually draw the pin replacement table, and then compare and change them one by one.