Image acquisition and processing technology is widely used in many fields such as machine vision and image analysis. With the emergence of the high-speed PCI Express (PCIE) bus, the high-speed data acquisition card based on the PCIE interface will play an increasingly important role in the occasions where the data transmission and processing volume are large.

A CamLink camera refers to a camera with a Camera Link interface. Camera Link is a standard interface jointly developed by several industrial cameras and video card manufacturers to meet various video transmission requirements. This standard can not only meet the requirements of various high-speed video transmission, standardize the interface between digital cameras and frame grabbers, but also greatly reduce the time and cost of equipment development and maintenance for video equipment providers. Camera Link provides ultra-high image transfer speed and is quickly supported by most camera and frame grabber manufacturers due to its high performance, low cost and ease of connection.

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In some high-end fields, especially in the field of machine vision, the data transmission and processing capabilities of computers are seriously tested. The current development of image acquisition cards is gradually developing towards high-speed and stable transmission and high-speed processing. PCI Express adopts the current popular point-to-point serial connection method in the industry. Compared with the shared parallel architecture of PCI and earlier computer buses, each device has its own dedicated connection, does not need to request bandwidth from the entire bus, and can transfer data. The transfer rate is increased to a very high frequency, achieving a high bandwidth that PCI cannot provide. The PCI-Express specification is connected from 1 channel to 32 channels, and has very strong scalability to meet the different requirements of different system devices for data transmission bandwidth. For example, the PCIExpress X1 specification supports bidirectional data transmission, and each data transmission bandwidth is 250 MB/s, while the 33-bit 33 MHz PCI bus transmission bandwidth is only 133 MB/s. In the PCI Express X16 mode, the data transmission bandwidth can be as high as 4 GB/s per direction, and the bidirectional data transmission bandwidth is as much as 8 GB/s. Therefore, for cameras with high frame rate CamLink interface, traditional bus (such as PCI bus interface) can no longer meet the requirements of real-time image transmission.

This system uses PLX company's PEX8311 as the PCI Express X1 interface chip. The FPGA chip is used in the system to control the entire system. The FIFO IP core provided by the FPGA and two external independent SDRAMs are used to realize the cache processing of high-speed image data. .

1. System composition and principle

The hardware structure of CamLink image acquisition system based on PEX8311 is divided into 4 modules: CamLink interface module, FPGA control module, SDRAM storage module, PCI-Express interface module. Figure 1 is the principle block diagram of the system:

Design of high-speed image data system based on PEX8311 chip and FPGA device

The working principle of the system: After the system is powered on, the host computer software controls the FPGA to configure the internal parameters of the CamLink camera through the driver program. After the configuration is completed, the CamLink camera outputs frame rate signal, line rate signal, image cable clock signal and video signal. Since the output of the CamLink interface is a differential signal, the DS90CR288 A chip converts the differential into a single-ended signal and inputs it to the FPGA. Inside the FPGA, the data is buffered through the FIFO. Under the control of synchronization and clock signals, the data output by the FIFO is stored in the SDRAM. Since only SDRAM can be read or written at the same time, in order to prevent data loss, the FPGA is connected to two SDRAMs. In odd frames, one frame of image is written to SDRAM1, and the saved even frame image is read from SDRAM2. Complete the ping-pong operation of image transmission. The PEX8311 chip is used to complete the PCIE interface, and the PEX8311 is controlled by the logic program of the FPGA. The PCIE bus-based driver is written in the host computer, and the image is read from the SDRAM to the computer's memory by DMA, and the host computer software realizes the display and processing of the image.

2. PCI-Express interface module

There are many ways to realize the interface of PCI-Express. In this design, the PEX8311 chip of PLX Company is used to realize it by bridging. As a bridge chip, PEX8311 transmits information between the PCI Expr-ess bus and the Local bus. It can be used as the master device of the two buses to control the bus, and it can also be used as the target device of the two buses to respond to the bus. The chip jointly controls the data transmission of the chip through the internal control logic module, the internal bus state machine and the local bus state machine module. The control logic module of PEX8311 contains various register groups, which are used to control the transmission of data and record the transmission status.

The PEX8311 provides two serial E2PROM interfaces to read configuration information after the system is powered on. SPI serial E2PROM is the configuration E2PROM of PCI-Express. It is mainly used to control the performance of PCI-Express.

PEX8311 provides complete PCI-Express slave device support, and the signal lines of the PCI-Express interface part can be directly connected to PCI-Express connectors (commonly known as gold fingers). Among them, REFCLK± is a group of differential clocks, which is provided by the system board. Both reference clocks are required to remain within ±300ppm of the normal operating frequency of 100MHz. The PRSNT1/PRSNT2 signal lines are used to check if an add-in card is plugged into the connector. In this design, PRSNT1 and PRSNT2 are connected so that presence detection can be performed when the interface board is inserted into the PCI-Express connector. The schematic diagram of the PCI-Express interface is shown in Figure 2.

Design of high-speed image data system based on PEX8311 chip and FPGA device

3. System software design

3.1 FPGA logic program

Use Verilog to write FPGA logic control program, there are 5 bottom modules and 1 top module. Each module is responsible for a different function. The top-level module is the PCIE_CAMLINK module, which realizes the functions of the whole system by calling the functions of other modules; the CAMLINK module is used to control the reading and writing of the Camera Link interface; the DoubleSdcon module is used to control the enabling and reading and writing of the SDRAM chip to realize the ping-pong of the image. operation; the FIFO module is used to buffer data and match the working speed of each chip; the C_16450 module performs serial-to-parallel conversion to complete the control of the CamLink camera; the PEX8311-LOCAL module is used to control the read and write of the PCI-Express interface, and also It is to control the PEX8311 chip, and the control of the PEX8311 is the key to realize the PCI-Express bus.

In the design, the read and write of PEX8311 is controlled by writing a state machine (FSM, Finite State Machine). Fig. 3 is the Verilog HDL language sequence control state machine design of the single-cycle read and write of PEX8311. State 0 is an idle state, such as the local bus request signal LHOLD is set to 1, then go to state 1, otherwise stay in state 0. State 1 is the bus hold state, in which the local bus response signal LHOLDA should be set to 1. If the ADS signal is 0 and LW/R is 1, go to state 2; if the ADS signal is 0 and both LW/R and BLAST are 1, go to state 3, which is a single-cycle read state. State 2 is a single-cycle write state. In this state, the READY signal is set to 0 to indicate that the write data is valid. When BLAST is 0, it goes to state 3. State 3 is the read and write completion operation state. When LHOLD is set to 0, it indicates that PEX8311 no longer requests the local bus and goes to state 0. When BLAST is 0 and LHOLD is 1, it indicates that PEX8311 still needs to read and write data, then Go to state 1 to continue.

Design of high-speed image data system based on PEX8311 chip and FPGA device

3.2 Drivers

The PCI-E bus and the PCI bus are completely compatible in the software layer, so the development process of the PCI-E bus driver is the same as that of the PCI device driver. This design uses VC++6.0 and development kit Driver Studio (DS) to carry on the development of the driver. DS can be integrated into the Visual C++ environment to generate the corresponding driver framework for specific applications, and the object-oriented programming method is adopted in programming, which greatly improves the programming efficiency.

The main functions of the driver: 1) Initialize the device, find the hardware to be controlled, set the program entry point of the driver distribution routine in the driver object, and create all driver objects or other system resources; 2) Create device objects , use the AddDevice function to create a device object and connect it to the device stack with PD0 as the base; 3) Interrupt response and processing, complete the response to external hardware interrupts and pass the interrupt information to the application; 4) DMA operation, completes the DMA read and write operations and generates a DMA interrupt after the DMA transfer ends, and sends the transferred data to the external bus or application program through the responsive DMA interrupt.

4. Experimental results

The transmission performance of the system is tested by writing the host computer program. The basic principle of the test is that the host computer generates a batch of data, then writes it from the PCI-Express interface of the computer to the PEX8311, then writes it to the FIFO, and finally writes it to the SDBAM, and then the host computer again Read back the data just written from the SDRAM, compare whether the read and written data are consistent, you can judge whether the system read and write is correct, and test the data transmission rate. After a period of testing, the maximum transmission speed of the system reaches 180 MB/s, which meets the high-speed data transmission requirements of this system.

5 Conclusion

This paper designs a high-speed image acquisition system based on the CamLink interface of the PCI Express bus. After the hardware design of the system is completed, the logic control program of the FPGA is written, and the driver program and the host computer application program are developed. The system adopts PCI Express bus to realize high-speed data transmission between hardware circuit and computer. The interface chip adopts the first PCI Express bridge chip PEX8311 introduced by PLX Company. The experimental results show that the designed hardware system meets the requirements of high-speed image transmission and has stable performance.