Features and Benefits

▪ Low RDS (on) output

▪ Automatic current decay mode detection/selection

▪ Mixed and slow current decay modes

▪ Low power synchronous rectification

▪ Internal UVLO and thermal shutdown circuitry

▪ Cross current protection

illustrate

The A3983 is a complete microstepping motor driver with built-in translation for easy operation. It is designed to operate bipolar stepper motors in full-step, half-step, fourth-order, and eighth-order modes, with output drive capacities up to 35 V and ±2 A. The A3983 includes a fixed off-time current regulator capable of operating in slow decay mode or mixed decay mode.

Translation is the key to A3983's ease of implementation. Just a single pulse at the step input can drive the motor one microstep. There are no phase sequence tables, high frequency control lines or complex programming interfaces. The A3983 interface is ideal for applications where complex microprocessors are unavailable or overburdened.

The chopper control in the A3983 automatically selects the current decay mode (slow or mixed). When a signal is present at the step input pin, the A3983 determines whether the step is producing higher or lower current in each motor phase. If you change to a higher current, the decay mode is set to slow decay. If the change is to a lower current, the current decay is set to mixed (initially set to fast decay for a duration equal to 31.25% of the fixed off time, then set to slow decay for the remainder of the off time). The current decay control scheme reduces the audible noise of the motor, improves step accuracy, and reduces power consumption.

Internal synchronous rectification control circuitry is provided to improve power consumption during PWM operation. Internal circuit protections include: hysteretic thermal shutdown, undervoltage lockout (UVLO), and cross-current protection. No special power-up sequence is required.

The A3983 is offered in a low profile (1.2 mm maximum height), 24-pin TSSOP with exposed thermal pad (suffix LP). Lead free, 100 % matte tin leadframe.

selection guide

Absolute Maximum Ratings

Thermal characteristics

*In still air. Additional caloric information available on the Allegro website.

Function description

device operation. The A3983 is a complete microstepping motor driver with a built-in converter for simple operation and minimal control lines. It is designed to operate bipolar stepper motors in full-step, half-step, fourth-step and sixteen-step modes. The currents in the two output full bridges and all N-channel DMOS field effect transistors are regulated by a fixed off-time PMW (pulse width modulated) control circuit. In each step, the current of each full bridge is set by the values of its external current sense resistor (RS1 or RS2), the reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the converter).

At power-up or reset, the converter sets the DAC and phase current polarities to their initial initial state (as shown in Figures 2 to 5), and sets the current regulator to a mixed decay mode for both phases. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage and current polarity. (See Table 2 for the current level sequence.) The microstep resolution is set by the combined effect of the inputs MS1 and MS2, as shown in Table 1.

When stepping, if the new output level of the DAC is lower than its previous output level, the attenuation mode of the active full bridge is set to mixed. If the new output level of the DAC is higher or equal to its previous level, the decay mode of the active full bridge is set to slow. This automatic current decay selection improves microstepping performance by reducing current waveform distortion caused by motor back EMF.

Reset input (reset). The reset input sets the converter to a predefined initial state (shown in Figure 2 to Figure 5) and turns off all DMOS outputs. All step inputs will be ignored until the reset input is set high.

Step input (step). A low-to-high transition on the step input puts the translator in sequence and advances the motor one increment. The converter controls the input of the DAC and the current flow in each winding. The size of the increment is determined by the combined state of the inputs MS1 and MS2.

Microstep selection (MS1 and MS2). Select the microstep format as shown in Table 1. MS2 has a 100 kΩ pull-down resistor. Any changes made to these inputs will not take effect until the next rising edge.

Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction is clockwise, when high, the direction is counterclockwise. Changes to this input will not take effect until the next rising edge.

Internal PWM current control. Each full bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to the desired value ITRIP. Initially, a pair of diagonal source and sink DMO outputs are enabled and current flows through the motor windings and current sense resistor RS. When the voltage across R equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the source DMOS fet (in slow decay mode) or the sink and source DMOS fet (in mixed decay mode).

The maximum value of the current limit is set by selecting the voltage on the RS and VREF pins. The transconductance function is approximated by the current-limited maximum value itrimax(A), which is given by:

where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V).

The DAC output reduces the VREF output to the current sense comparator in precise steps such that:

(See Table 2 for the %itrimpax for each step.) It is critical not to exceed the maximum rating (0.5 V) of the SENSE1 and SENSE2 pins.

fixed rest periods. The internal PWM current control circuit uses a one-shot circuit to control the duration that the DMOS FET remains off. The one-shot off time tOFF is determined by the choice of an external resistor connected from the ROSC timing pin to ground. If the ROSC pin is connected to an external voltage greater than 3v, tOFF defaults to 30µs. For this purpose, the ROSC pin can be safely connected to the VDD pin. The value of tOFF (μs) is approximately:

blank. This function will blank the output of the current sense comparator when the internal current control circuit switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and switching transients associated with load capacitance. The blank time tBLANK (μs) is approximately:

Charge Pumps (CP1 and CP2). The charge pump is used to generate gate power greater than VBB to drive the gate of the source DMOS. A 0.1µF ceramic capacitor should be connected between CP1 and CP2. Additionally, a 0.1µF ceramic capacitor is required between VCP and VBB as a reservoir for the high-side DMOS gate.

VREG (VREG). This internally generated voltage is used to operate the receiver side DMOS output. The VREG pin must be grounded separately from a 0.22µF ceramic capacitor. VREG is monitored internally. In a fault condition, the DMOS output of the A3983 is disabled.

Enable input (enable). This input turns all DMOS outputs on or off. When set to logic high, the output is disabled. When set to logic low, internal control enables the output as needed. The converter inputs STEP, DIR, MS1 and MS2 and the internal sequencing logic remain active regardless of the enable input state.

closure. In the event of a fault, over temperature (over TJ) or under voltage (on VCP), the DMOS output of the A3983 is disabled until the fault condition is removed. On power-up, the UVLO (under-voltage lockout) circuit disables the DMOS output and resets the converter to its initial state.

Sleep mode (sleep). To minimize power consumption when the motor is not in use, this input disables many internal circuits, including the output DMOS FET, current regulator, and charge pump. A logic low on the sleep pin puts the A3983 into sleep mode. A logic high allows normal operation and startup (where the A3983 drives the motor to the initial microstep position). When emerging from sleep mode, a delay of 1 ms is provided before issuing a step command in order for the charge pump to stabilize.

Mixed decay operations. The bridge can be in mixed decay mode, depending on the sequence of steps, as shown in Figures 3 to 5. When the trigger point is reached, the A3983 initially goes into fast decay mode with a 31.25% off time. tove. After that, it switches to slow decay mode for the remaining flight time.

Synchronous rectification. When a PWM off cycle is triggered by an internal fixed-off time cycle, the load current cycles according to the decay mode selected by the control logic. This synchronous rectification function turns on the appropriate FET during current decay and effectively shorts the body diode with low DMOS RD(on). This greatly reduces power dissipation and can eliminate the need for external Schottky diodes in many applications. Turning off synchronous rectification prevents the load current from reversing when zero current levels are detected.

application layout

Layout. Printed circuit boards should use heavy duty ground planes. For best electrical and thermal performance, the A3983 must be soldered directly to the board. The bottom of the A3983 package is an exposed pad that provides a way to enhance heat dissipation. The thermal pad should be soldered directly to the exposed surface of the PCB. Thermal vias are used to transfer heat to other layers of the PCB.

To minimize the effects of ground bounce and offset issues, it is important to have a low impedance single point ground, called a star ground, located very close to the device. By connecting the pad to the ground plane directly below the A3983, this area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage at the input terminals remains stable. A star ground can be created using an exposed thermal pad under the device as a low impedance ground point and thermal path.

The two input capacitors should be placed in parallel and as close as possible to the device power pins. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for carrying the high frequency current to the element. The ground impedance of the sense resistors RSx should be very low as they must carry large currents while enabling very accurate voltage measurements through the current sense comparators. A long ground trace will cause an additional voltage drop, adversely affecting the comparator's ability to accurately measure the winding current. The distance between the SENSEx pin and the RSx resistor is very short, and the distance to the star ground below the device is very large and the impedance is very low. If possible, no other components should be present on the detection circuit.

Table 2. The step sequence is set at the starting microstep position at a step angle of 45°; DIR=H

*Ground pins must be connected together externally by connecting to the ground plane of the pad under the device.

Low Voltage Package, 24-Pin TSSOP with Exposed Thermal Pad