Features

● Low distortion: 5MHz at 5MHz

● gain +1 bandwidth: 400MHz

● Provide SOT23-5 packaging

● High -opening gain gain: 95db

● High -common model suppression: 90db

● Quick 12 -bit settings: 13ns (0.01%)

● Low noise: 2.7nv/√Hz

● High -output current: ± 60mA

● Very low difference gain/phase error: 0.007%/0.008 °

● ADC/ DAC buffer amplifier

● Low disturbance medium frequency placing large device

● High -resolution imaging

● Medical imaging

123] ● High CMR Differential amplifier

● Test instrument

● Professional audio

OPA642 provides what previously could not achieve in single -piece operations. Speed u200bu200band dynamic range AMP. Using OPA642 is a unit gain stable voltage feedback structure with two internal gain levels, which can achieve extremely low harmonic distortion within a wide frequency range. The ""classic"" differential input provides all common advantages of precision computing amplifiers, such as compared with broadband current feedback computing amplifiers, bias current elimination and extremely low reverse current noise. Quick stability time, excellent differential gain/phase performance, low voltage noise and high output current driver make OPA642 an ideal choice for most high dynamic range applications.

The stability of the unit gains enables OPA642 to be particularly suitable for low -gain differential amplifiers, cross -blocking large,+2 video cable drive gains, broadband integrals and low distortion ADC amplifiers. If you need higher gain or even lower harmonic distortion, consider OPA643, which is a higher gain bandwidth and lower noise version of OPA642.

High dynamic range 10MSPS digital meter

Typical performance curve

TA u003d+25 ° C, vs u003d ± 5V, RL u003d 100 , RF u003d 402 , g u003d+2, unless there is another explanation. RF u003d 25 , the gain is +1.

Application information Broadband voltage feedback operation [ 123] The combination of the speed and dynamic range of OPA642 can easily be realized in various application circuits, as long as it follows the simple principles of good design practice. For example, as shown in Figure 1, good power decoupling is essential to respond to the frequency of harmonic distortion as low as possible. The correct PC plate layout and careful component selection will maximize the performance of OPA642 in all applications, as described in the rest of the data table. FIG. 1 shows the +2 configuration gain as the basis of most typical performance curves. Most curves are characterized by the signal source of 50 driving impedance and 50 measuring equipment with load impedance. In FIG. 1, 50 parallel resistors at the VI terminal match the source resistance of the test generator, while the 50 series resistors on the VO terminal provide the matching resistor to the measuring device load. Generally speaking, the data table specification refers to the voltage swing at the output pin (VO in Figure 1). 100 loads generated by the combined with the connected resistance, plus the total feedback network load of 804 so that the OPA642 has a effective load of about 90

Cushion high -performance ADC

In order to achieve the entire performance of the high dynamic range A/D converter, it must be very careful when designing the input amplifier interface circuit. The example circuit on the homepage shows a typical AC coupling interface to a very high dynamic range converter. Symptoms work symmetrically within a range of about 0 volt. The 2VP-P swings then blocks the level of the DC by blocking the level of the capacitor. This is generated by a good decoupled resistor compressor in the internal reference voltage of the converter. In order to have a negligible effect on the rated dynamic range (SFDR) of the converter's rated dynamic dynamic range (SFDR), the SFDR of the amplifier should be greater than 10dB. In the homepage example, the insertion of OPA642 has an inestimable impact on the distortion of ADS804. The ADS804 implements the 80DB SFDR under the 5MHz Nyquist input signal.

In order to achieve as low as possible in the 8-pin SO-8 or DIP packaging, it is necessary to add 0.1 μF decoupled capacitors to the pin 5 and 8. As shown in Figure 1. Although the pin 5 and the pin 8 are connected to the pin 4 and the pin 7 of the pin 7 (the standard power supply pin of the 8 pins computing amplifier), the additional capacitor helps to separate the packaging of the packaging lead and the secondary time under 5MHz under 5MHz Harmony inhibitory increases by about 4dB. SOT23-5 shorter connection cables and power cords provide the best distortion performance, and only two power connections are required.

Successful application of OPA642 for ADC buffer requires carefully selecting series resistance at the amplifier output end, and an additional parallel container at the ADC input terminal. To some extent, the choice of this RC network will be determined by experienceThe type of type of type. Many high -performance CMOS ADCs, such as ADS804, have better performance when there is parallel container at the input end. The capacitor provides low -source impedance for the transient current generated during the sampling process. The improved SFDR is obtained by increasing the capacitor, and the value of the capacitor is usually recommended in the converter data table. The combination of external capacitors with the built -in capacitance of A/D input provides an important capacitance load for OPA642. If there is no series isolation resistance, the result may be the peak value or loss of stability that the amplifier does not want to achieve. Because the DC bias current of CMOS A/D input can be ignored, the resistance has no effect on the overall gain or offset accuracy. Refer to the curve diagram of ""RS and capacitance load"" in the typical performance curve to obtain a good startup value of series resistors. This will ensure a flat frequency response to the ADC input. Increasing the external capacitance value will reduce the series resistance, or keep the resistance unchanged, and will limit the signal and reduce the high -frequency noise input of the converter.

Video cable driver

Most video distribution system design has 75 series resistors to drive the matching 75 cable. In order to match the net gain of 1 to 75 match the load, the amplifier usually sets the voltage gain to +2 to compensate for the 6DB attenuation of the signs formed by the sterilizer formed by the resistor formed by the side of the resistor. If all the reference values u200bu200bof 50 the resistor are replaced by 75 then the circuit in Figure 1 is suitable for this requirement. Generally, the amplifier gain further increases to 2.2, which restores the additional DC loss of the typical long cable line. This change requires the gain resistance (RG) in Figure 1 from 402 to 335 . In any case, OPA642's gain flatness and differential gain/phase performance will provide excellent results in video distribution applications. Differential gain and phase measurement of color sub -carrier frequency (3.58MHz in the NTSC system) and large signal output levels (representing brightness information in the composite video signal) overall small signal gain and phase changes. OPA642 In the standard brightness range of the single -matching video cable 150 on the standard brightness range of the positive video (negative synchronization) signal, the differential gain/phase error of the display is less than 0.01%/0.01 °. Negative video signals will also appear similar. In fact, due to the linear high -frequency output impedance of OPA642, similar performance can be obtained even under two video loads.

Single transportation difference distribution large device

The voltage feedback architecture of OPA642, its high co -model ratio will provide excellent performance differential amplifier configuration. Figure 2 shows a typical configuration. The starting point of this design is to choose 200 to 2K RF value. The lower value reduces the required RG and increases the V2 sourceAnd the load output with OPA642. The higher value will increase the output noise and exacerbate the effects of parasitic boards and device capacitors. After selecting RF, you must set RG to obtain the reversal gain required for V2. Keep in mind that bandwidth will be set up by about the gain bandwidth (GBP) divide by noise gain (1+RF/RG). For accurate differential operations (that is, good CMR), the ratio R2/R1 must be set to RF/RG. Generally, it is best to set the absolute values u200bu200bof R2 and R1 to RF and RG, respectively; this can make the pressure division resistance equal and eliminate the effect of input bias current. However, in order to adjust the load on the drive source V1, adjusting the value of R2 and R1 is sometimes useful. In most cases, the achievement of low -frequency CMR will be limited by resistance accuracy. OPA642's 90DB CMR will not determine the CMR of the entire circuit unless the resistance is better than 0.003%. If it is necessary to fine -tune CMR, R2 is the recommended adjustment point.

The main disadvantage of the three -way calculation amplifier difference (instrument topology)

The main disadvantage of the single transportation difference distribution large device is that the input impedance is relatively low. When the differential input terminal requires high impedance, OPA642 can be used as a differential level to build a standard instrument amplifier (INA) topology. Figure 3 shows an example, two of which are encapsulated together as a dual voltage feedback amplifier OPA2650. Compared with the two additional OPA642 devices, this method saves circuit board space, cost and power consumption, and because the input amplifier's medium load can still get very good noise and distortion performance. In this circuit, because the four matching 1K resistors, the output covarranty is always 1, and the differential gain is set by (1+2RF1/RG), and the value in Figure 3 is equal to 2. The conversion of differential to single -ended is still performed by OPA642 output. High impedance input allows V1 and V2 source to match or impedance matching, and no differential amplifier is required to be loaded further. If V1 and V2 input are already real differential inputs, such as the output of the signal transformer, you can use a matching terminal resistor between them. However, please remember that for V1 and V2 input, there must always be a defined DC signal path; for the transformer situation, the second -level connection of the center drawing will provide the best DC operation point.

DAC cross-blocking large device

High-frequency DDC-DAC requires a low output amplifier to maintain its SFDR performance into a real load Essence The single -end output driver is implemented as shown in Figure 4. In this circuit, only one side of the complementary output drive signal is used. The figure shows the signal output current connected to the virtual grounding and knot connecting to OPA642. OPA642 is set to cross-resistant or ""I-V converter"". DAC's unused current output grounding. If DAC requires its output to be connected to non -connected landThe compliance voltage is performed, and the appropriate voltage level can be applied to the non -inverse input terminal of OPA642. The DC gain of this circuit is equal to radio frequency. Under high frequency, the DAC output capacitor will produce zero in the noise gain of OPA642, which may cause the peak of the closed -loop frequency response. Add CF to the RF to compensate for the peak of noise gain. In order to achieve a flat cross-resistance frequency response, the pole point in the feedback network should be set to:

The corner frequency u0026#402; 123]

Active filter

Most source filter topology will use OPA642 broadband and unit gain stability to provide excellent performance. The topology that uses capacitor feedback requires a stable voltage feedback amplifier with a stable unit gain. Salleenkey filter simply uses the operational amplifier as a non -inverted gain level in the RC network. The current or voltage feedback amplifier can be used for Sallen-Key.

FIG. 5 shows an example Sallen-Key low-pass filter, where OPA642 is set to provide a low-frequency gain of +2. Select the filter component value to obtain the maximum flat Bartworth response, the bandwidth is 5MHz -3DB. The resistance value has been slightly adjusted to compensate the influence of 150MHz bandwidth provided by OPA642 in the configuration. This filter can be combined with the ADC driver to provide medium (2 pole) Naquist filtering, restricting noise, and external weight into the input of ADC. This filter will provide high SFDR A/D converter (such as ADS804 (12 -bit, 10MSPS, 80DB SFDR).

Optimized resistance value

Since OPA642 is a voltage feedback amplifier with a stable voltage of unit gain, feedback and gain setting resistors can use a wide range of resistance. The main limit of these values u200bu200bis through dynamics through dynamic dynamics. Scope (noise and distortion) and parasitic capacitors. For non -counter -phase unit gain follower applications, the feedback connection should use 25 not directly short circuit. And improve frequency response flatness. Generally, the feedback resistance should be between 200 and 1K below 200 Wave disturbance performance. When it is higher than 1K , the typical parasitic capacitor (about 0.2pf) on the feedback resistance may cause the unreasonable band restrictions in the amplifier response.

A good experience is to bring RF RF The parallel combination with RG (Figure 1) is set toIt is less than about 200 . The combination impedance RF | | RG interacts with inverter input capacitors, adding a pole to the feedback network, so that the positive response is zero. Assuming the parasitic 2PF on the reverse node, keep RF | | RG u0026 LT; 200 it will keep the pole above 400MHz. As far as it is concerned, this constraint means that the feedback resistance RF can increase to several K under high gain. As long as the parasitic capacitance formed by RF's magnetic poles and parallel is not within the frequency range of interest, this is acceptable.

In the reverse configuration, you must pay attention to the additional design considerations. RG becomes the input resistance, so it becomes a load impedance of the driver source. If the impedance match is required, the RG can be set to the required terminal value. However, at low reverse gains, the feedback resistance value generated can provide an important load for the amplifier output. For example, if the inverter gain is 2 and the input matching resistance is 50 (u003d rg), a feedback resistor of 100 this will help the output load connect with the external load. In this case, it is best to increase the RF and RG values u200bu200bat the same time, and then use the third -to -ground resistance to achieve input matching impedance. The total input impedance becomes a parallel combination of RG and an additional parallel resistor.

Bandwidth and gain

When a closed -loop signal shows that the feedback of the gain increase, the feedback of gain decreases. Theoretically, this relationship is described as a width bandwidth (GBP) displayed in the specification. Ideally, GBP except for non -reincarnation signal gain (also known as noise gain, or NG) will predict a closed -loop bandwidth. In fact, it was established when the phase hameness is close to 90 °, just like in a high -gain configuration. Under low signal gain, most amplifiers will show more complicated response and lower phase habits. OPA642 is optimized and gives the largest flat second -order Bartworth response when the gain is 2. In this configuration, the OPA642 has a phase of about 60 °, and it will display a typical -3DB bandwidth of 150MHz. When the phase of the phase is 60 °, the closed loop band width is about the prediction value of the noise gain from the GBP. Increasing gain will make the phase margin close to 90 °, and the bandwidth is closer to the predicted value (GBP/NG). When the gain is +10, the 21MHz bandwidth displayed in the typical specifications is consistent with the typical GBP of 210MHz with a simple formula forecast.

Output driving capacity

OPA642 has been optimized, which can drive high requirements for dual -end transmission lines. When driving 50 line, use a series of 50 in the cable, and use a terminal load of 50 at the end of the cable. Under these conditions, the impedance of the cables appears as a resistance within a very wide frequency range. The total effective load on OPA642 is connected to 100 . The technical specifications show that there is a guarantee ± 2.5V swing in such a load, and then reduced to ± 1.25V at the terminal resistance. The guaranteed ± 35mA output driving temperature provides sufficient current driving grid for the load. When driving high impedance loads, higher voltage fluctuations (and lower distortion) can be achieved.

A single video load is usually displayed as 150 load (using standard 75 cable). OPA642 provides sufficient voltage and current drivers to support the NTSC signal up to 3 parallel video loads (total load 50 ). In the case of only one load, OPA642 achieved an exceptional low 0.007%/0.008 ° DG/DP error.

Drive capacitance load

For the operator, the most demanding and most common load conditions are the capacitance load. High -speed and high -open -rim gains like OPA642, when the capacitance load is directly applied to the output pin, its stability and closed -loop response peak value is very sensitive. Simply put, the capacitance load reacts with the opening resistance of the amplifier and introduces additional poles in the ring road, thereby reducing phase margin. This problem has become a hot topic of application comments and articles, and has proposed some external solutions to solve this problem. When the main consideration of frequency response flat, pulse response and/or distortion, the simplest and most effective solution is to insert a series of isolation resistance between the amplifier output and the capacitance load. Feedback circuit isolation. This does not eliminate the pole from the ring response, but shift it and add zero at a higher frequency. The effect of additional zero is to eliminate the phase lag of the container characteristics, thereby increasing the phase margin and improving the stability.

The typical performance curve shows the recommended RS and the frequency response generated by the recommended RS and the capacitance load and the frequency generated under the load. The standard for setting a recommended resistor is the maximum bandwidth and flat frequency response at the load. Because there is a passive low -pass filter between the output tube and the load capacitor, the response of the output tube's itself is usually a bit peak, and it becomes flat after the RC network rolled. In most applications, this is not a problem, but if the expectation signal under the load is very close to the amplitude limit of the amplifier. This limit is most likely to occur in the application of the pulse response, and the frequency peak manifested as an overwhelming in the step response.

Parasitic capacitance load greater than 2PF will begin to reduce the performance of OPA642. The long PC board trajectory, unsatisfactory cables, and connection with multiple devices can easily lead to exceeding this value. Always consider this impact carefully, and close the recommended series resistor (see the circuit board layout guide) as possible to the OPA642 output pins.

Disctional performance

OPA642 can transmit unusually distortion signals with high frequency and low -gain transmission. The distortion in the typical performance curve shows typical distortion in various cases. The dynamic range of most curves is 100dB. Before the signal level exceeds 0.5V and/or the base frequency exceeding 500kHz, the distortion of OPA642 will not rise to -100dbc. Audio distortion ≤ –120 decibels.

Generally speaking, before the base wave signal reaches a high frequency or power, the second harmonic will dominate the distortion, and the three harmonic components can be ignored. Then focus on the second harmonic to increase the load impedance directly to improve the distortion. Remember that in non -inverse configuration, the total load includes the feedback network. This is the sum of RF+RG, and in the reverse configuration, this is only RF (Figure 1). Increasing the output voltage swing directly increases the harmonic distortion. Increased output width of 6DB usually increases secondary harmonic 12DB and three harmonic 18DB. Increasing signal gain will also increase the second harmonic distortion. Similarly, an increase of 6 decibel gains will increase the second and third harmonic 6 decibels, even in the constant output power and frequency. Finally, due to the attenuation of the frequency of the loop, the distortion increased with the increase of the infrastructure. On the contrary, the distortion will improve to the low frequency until the main opening of the main opening of about 3KHz. From the 2VP-P-90DBC secondary harmonic to 500 , the distortion under G u003d+2 1MHz (according to the typical performance curve), the second harmonic distortion under 20kHz should be about -90db – 20log (1MHz// 20kHz) u003d - 124dbc.

OPA642 has extremely low third -order harmonic distortion. This also provides a very good double sound, three -tier intermodal interception, as shown in the typical performance curve. When the resistance is matched by 50 matching the resistor, the cutting curve is defined as 50 The network will be attenuated by the voltage of the output to the load of 6DB. If OPA642 is directly driven to the input terminal of high impedance device (such as ADC), this 6DB attenuation will not be used. Under these conditions, the cutting distance increases at least 6dBM. The cutting distance is used to predict the interoperability of two adjacent frequencies. If the two test frequencies F1 and F2 are specified in accordance with the average frequency and Δ frequency fo u003d (F1+F2)/2 and u0026#8710; F u003d | F2 – F2 |/2 Fo ± (3 u0026#8226; u0026#8710; f) appeared. The difference between the two equal testing sound levels and these interoperability mixed power levels is given by 2 u0026#8226; (IM3 – PO). Among them, the IM3 is the intercept of the typical performance curve. One of the tight intervals of the test frequency of 50 power level (DBM) under the load. For example, at 10MHz, OPA642 with a gain of +2 is matched 50 the intercept of the load is 46DBMEssence If the two frequencies of all-in-laws need to be 2VP-P, each tone is required to be 4DBM. Third-order interoperability mixed tone will be lower than the test sound level (-80dBm) 2 u0026#8226; (46–4) u003d 84DBC. If the same 2VP-P dual-tone package line is transmitted directly to the input terminal of the ADC, without matching loss or 50 the load of the network will increase to at least 52DBM. Under the same signal and gain conditions, but now driving directly under the light load, the boring tone will be at least lower than the 1VP-P test sound signal level 2 u0026#8226; (52–4) u003d 96dbc.

Noise performance

OPA642 supplements its ultra -low harmonic distortion with low input noise items. The input voltage noise is combined with the two input reference current noise items, which can generate lower output noise under various working conditions. Figure 6 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items represented by NV/√Hz or PA/√Hz.

The total output point noise voltage can be calculated as a square root contributed by the output noise voltage. This calculation method is to superimize all noise power at the output end, and then take a square root to get a point noise voltage. Formula 1 shows the general form of the output noise voltage, using the terms shown in FIG. 6.

This expression will be removed by the noise gain (GN u003d 1+RF/RG) at non -inverter input reference point noise voltage at the equivalent input input. As shown in equivalent 2.

Evaluate these two equations of the OPA642 circuit shown in Figure 1, which can draw the total output point noise voltage of 6.7nv/√Hz, equivalent input point noise noise The voltage is 3.35NV/√Hz.

The narrow -band communication system usually cares about the noise coefficient of the amplifier. The total input reference voltage noise expression (formula 2) can be used to calculate the noise coefficient. Formula 3 shows this noise coefficient expression. EN using formula 2 represents non -inverse configuration, where the input terminal connection resistor RT has been set to match the source impedance (as shown in Figure 1).

Calculated the Formula of Figure 1 Circuit 3 to obtain the noise coefficient u003d 17.6db. The input transformer coupling can be used to reduce the noise coefficient. Broadband pulse transformers can provide a noiseless voltage gain and a more optimized source impedance to minimize the noise coefficient. FIG. 7 shows an example based on the circuit construction in Figure 1, where the ratio ratio ratio is set to the closest integer of the minimum noise coefficient. The calculation formula for the best turn ratio ratio is as follows:

This optimization depends to a large extent on the selected amplifier and configurationEssence

DC offset control

OPA642 due to its high opening gain, high -co -model suppression, high power suppression, low input offset voltage and bias current bias The transfer error can provide excellent DC signal accuracy. Any packaging type (B) version of the encapsulation type provides input offset voltage of less than 1MV. In order to make full use of this low input bias voltage, you also need to pay close attention to the elimination of the input bias current. The high -speed input level of OPA642 has a relatively high input bias current (25 μA typical input pins), but the matching between the two input current is very close, usually a 100NA input bias current. By matching the source impedance of the two inputs, the total output offset voltage can be greatly reduced. For example, a method of adding bias current to the circuit in Figure 1 is to insert 175 series resistors into the non -inverse input terminal of 50 terminal connection resistors. When the input terminal impedance is 50 , the impedance of the input terminal will be increased to 50 Because this is now equivalent to the impedance outside the reverse input (RF | | RG), the circuit will offset the bias current gain of the output, leaving only the bias current multiplication to use the feedback resistor as the residual DC error item. With 402 feedback resistor, the output error is now less than 3 μA u0026#8226; 402 u003d 1.2mv.

Sometimes it is necessary to fine -tune the output offset or DC working point adjustment. There are many technologies to introduce DC offset control in the computing amplifier circuit. Most of these technologies will eventually be reduced to setting DC current through feedback resistors. One key consideration of choosing a technology is to ensure that it has the least impact on the frequency response of the expected signal path. If the signal path is intended to be non -reverse, the offset control is best as an anti -phase and signal application. If the signal path is reversed, you can consider the offset control of the input application of non -turbulent input. For DC coupling signals, in some configurations, DC offset signals can set DC current back to the source that must be considered. Adjusting the input of reverse computing amplifiers can also change the noise gain and frequency response flatness. FIG. 8 shows an example of the offset adjustment of the DC coupling pathway that has the minimum effect on the signal frequency response. In this case, the input is introduced to a inverter -increasing resistor, and the additional current that is adjusted by DC is added to the inverter node. The resistance network that sets this current is much larger than the signal pathway resistance. This will ensure that this adjustment has the least effect on the increase of the loop gain and frequency response.

Heat analysis

OPA642 does not require heat dissipation under most operating conditions. The maximum temperature required will set the maximum allowable internal power consumption as described below. In any case, the highest knot temperature must not exceed 175 ° C.

The working knot temperature (TJ) is from TA+PD u0026#8226; θJA gives. The total internal power consumption (PD) is a motivation for the additional power of the transmission load in static power (PDQ) and output (PDL). Static power is the specified air supply current multiplication by the total power supply voltage of the entire component. PDL will depend on the required output signals and loads, but for the ground resistance load, when the output is fixed at a voltage equivalent to the 1/2 power supply voltage (for equal dual power supply), the PDL will be maximized. Under this condition, PDL u003d vs2/(4 u0026#8226; RL), where RL includes feedback network load.

Note that the internal power consumption is the power of the output level rather than the load.

As the worst case, the maximum TJ is calculated using OPA642N (SOT23-5 packaging) in Figure 1 circuit, which runs at the highest-specified ambient temperature+85 ° C. Pd u003d 10V u0026#8226; 26MA+5^2/(4 u0026#8226; (100 | 804 ) u003d 330MW. The maximum TJ u003d+85 ° C+0.33W u0026#8226; 150 ° C/W u003d 135 ° C.

Circuit plate layout guide

To obtain the best performa