The Intersil ISL84684II device's low on-resistance bidirectional dual SPDT voltage analog switch is designed to operate from a single +1.8V to +4.5V supply. Target applications include battery power from low RON (0.21Ω) and fast switching speed (tON=43ns, tOFF=27ns). Digital logic when using a single +1.8V to 4.5V supply. For example, mobile phones often face ASIC functionality limitations. The number of analog inputs or GPIO pins can be limited and the digital geometry is not well suited for analog switch performance. This section can be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL84684II is packaged in a chip size of 2.00 mm x 1.50 mm, alleviating board space constraints. The 4x3 array solder ball pitch is 0.5mm. The ISL84684II is a committed dual single pole double throw (SPDT) switch consisting of two normally open (NO) and two normally closed (NC) switches. This configuration can be used as a dual 2-to-1 multiplexer. The ISL84684II is pin compatible with the MAX4684 and MAX4685

feature

Lead-free plus annealed (RoHS compliant) available

MAX4684 and max 4685

On-Resistance (RON) -V++=+2.7V. 0.21Ω-V+=+4.3V. 0.14 Euro

RON matching between channels, max. 0.05 Euro

RON flatness over signal range, max. 0.03 Euro

Single power supply operation. +1.8V to +4.5V

Low power PD. <0.32 microwatts

Fast switching action (V+=+2.7V) - t. 43 nanoseconds - time of flight. 27 ns

Guaranteed break-before-make

1.8V logic compatible

Low I+ current when VinH is not in the V+ rail

Available in 10-ball 4x3 array chip scale package (2mm x 1.5mm)

application

Battery Powered, Handheld and Portable Devices - Cellular/Mobile Phones - Pagers - Notebooks

Portable Test and Measurement

medical equipment

Audio and video switching

Note: Intersil lead-free + annealed products feature a special lead-free material set; molding compound/mold join material and 100 % matte tinplate finish, RoHS compliant and compatible with SnPb and lead-free soldering operations. Intersil's lead-free products are classified as MSLs that meet or exceed the lead-free requirements for temperature IPC/JEDEC J Standard-020 during lead-free peak reflow soldering.

Absolute Maximum Ratings Thermal Information

V+ is grounded. -0.3 to +5V

Input voltage

No, NC, inches (Note 2). -0.3 to ((V+)+0.3V)

The output voltage

COM (Note 2). -0.3 to ((V+)+0.3V)

Continuous current NO, NC or COM. ± 300mA

Peak current NO, NC or COM

(pulse 1 ms, 10% duty cycle, max). ± 500mA

ESD HBM ratings (per Mil-Std-883, Method 3015). ? kV

Thermal Resistance (Typical, Note 3) θJA (Celsius/Watt)

10 ball crumb weigher package. 91

Maximum storage temperature range. -65°C to 150°C

Soldering conditions (Note 4). According to J-STD-020

operating conditions

temperature range

ISL84684II. -40°C to 85°C

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

2. Signals on NC, NO, IN or COM that exceed V+ or GND are clamped by internal diodes. Limit forward diode current to maximum rated current.

3. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air.

4. Allowable soldier profiles are limited to those recommended in the industry standard specification JEDEC J-STD-020. Preheating is mandatory. Hand or wave soldering is not allowed.

Electrical Specifications - 3V Power Supply Test Conditions: V+=+2.7V to +3.3V, GND=0V, VINH=1.4V, VINL=0.5V (Notes 5, 7) unless otherwise specified

Electrical Specifications - 3V Power Supply Test Conditions: V+=+2.7V to +3.3V, GND=0V, VINH=1.4V, VINL=0.5V (Notes 5, 7) unless otherwise specified (continued)

notes:

5. VIN = input voltage to perform correct function.

6. The algebraic convention is used in this data sheet, where the most negative value is the minimum value and the most positive value is the maximum value.

7. Parts are 100% tested at +25°C. Limit values over the entire temperature range are guaranteed by design and correlation.

8. Flatness refers to the difference between the maximum value and the minimum value of the on-resistance within the specified analog signal range.

9. Guaranteed but not tested.

10. RON matching between channels is calculated by subtracting the channel with the highest maximum RON value from the channel with the lowest maximum RON value

Electrical Specifications - 4.3V Power Supply Test Conditions: V+=+3.9V to +4.5V, GND=0V, VINH=1.4V, VINL=0.5V (Notes 5, 7) unless otherwise specified (continued)

Detailed description

The ISL84684II is a bidirectional, dual unipolar/dual analog switch single-channel 1.8V to 4.5V power supply that provides precision switching, low on-resistance (0.21Ω) and high-speed operation (tON=43ns, tOFF=27ns). This device is particularly suitable for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (0.32 microwatts max), low leakage current (150nA max), and tiny chip package. Ultra-low resistance and Ron flatness provide very low insertion loss and distortion for applications requiring signal replication. Power Supply Sequencing and Overvoltage Protection As with any CMOS device, proper power supply sequencing protects the device from excessive input current that can permanently damage the integrated circuit. All I/O pins contain ESD protection diodes from the pin to V+ and ground (see Figure 8). To prevent these diodes from being forward biased, V+ must be applied before any input signal, and the input signal voltage must be kept between V+ and GND. If these conditions cannot be guaranteed, precautions must be implemented to prohibit logic pins and signal pins from exceeding the maximum switch ratings. The following two methods can be used to provide additional protection to limit signal pins or logic pins from voltages below ground or above the V+ rail. The logic input can be connected in series with the logic input (see Figure 8). Resistor limit input currents below the input current produce permanent damage and sub-microampere input currents produce insignificant voltage drops under normal conditions of operation.

This method does not work for signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting the Schottky As shown in Figure 8, a diode connected to the signal pin will shunt the fault current to supply or ground, thus protecting the switching. These Schottky diodes must be sized to handle the expected fault current.

Power Considerations

The ISL84684II structure is most single-supply typical CMOS analog switches with two supply pins; V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike the switch when the maximum supply voltage is 4V, the ISL84684II 5V maximum supply voltage is 10% tolerance of the 4.3V supply, plus overshoot and noise peaking.

The recommended minimum supply voltage is 1.8V, but the part will operate on supplies lower than 1.5V. It is important to note that at lower supply voltages, the input signal range, switching time, and on-resistance decrease. See the Electrical Specifications table and typical performance detail curves. V+ and GND also power the internal logic and level shifters. The level shifter converts the input logic level to the switch level to drive the V+ and GND signal terminals of the analog switch gate. This series of switches cannot be used with bipolar switches to operate the power supply because the input switch point becomes negative for this configuration. Logic Level Thresholds This switch family is compatible with 1.8V CMOS (0.5V and 1.4V) over a supply range of 1.8V to 4.5V (see Figure 16). The 4.5V VIH level is about 1.3V, still lower than the 1.8V CMOS guaranteed high output minimum level of 1.4V, but with a noise margin reduction. The digital input stage is where the digital input voltage is not on one of the supply rails. Power consumption is minimized by driving the fast transition time of digital input signals from GND to V+. The ISL84684II has been designed to operate at any time the input voltage is not driven to the supply rail (0V to V+). For an example of driving a device with 2.85V logic (0V to 2.85V) When operating from a 4.2V supply, the device draws only 1.6 microamps.

High frequency performance

In a 50Ω system, the signal response is fairly flat over 10MHz with an a-3dB bandwidth of 80MHz (see Figure 17). The frequency response is in the wide V+ range for a variety of analog signal levels. The turn-off switch acts like a capacitor, creating a feedthrough of the signal from the input to the output of the switch by passing higher frequencies with less attenuation. Off isolation is when crosstalk exhibits feedthrough from one switch to another. Figure 18 details the high isolation and crosstalk rejection provided by this section. At 100kHz, the disconnect isolation is about 56dB in a 50Ω system, decreasing by about 20dB with increasing frequency. High load impedance reduces isolation and crosstalk suppression due to switching divider operating impedance and load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog signal pin and V+ and GND. One of what if any analog signal exceeds V+ or ground. Almost all analog leakage current comes from the ESD diode to V+ or ground. Although the pins on a given signal are the same and thus fairly balanced, they have different reverse biases. Everyone is biased against V+ or GND and analog signals. This means that their leakage varies with the signal. The difference between the two diodes The leakage at the V+ and GND pins constitutes the analog signal path leakage current. All analog leakage currents are between each pin and one power terminal, not the other switch terminals. This is why a given switch can show the same or opposite leakage current polarity. There is no connection path between the analog signal and V+ or GND.

Typical performance curve TA=25°C unless otherwise specified

Typical performance curve TA=25°C unless otherwise specified (continued)