feature

Serial Peripheral Interface (SPI) compatible; supports SPI modes 0 (0,0) and 3 (1,1); datasheet describes mode 0 operation low voltage operation; 1.8 (VCC = 1.8V to 5.5V); 20MHz clock frequency (4.5V to 5.5V); supports 128 -byte page mode and byte write operations; block write protection; protects 1/4, 1/2, or the entire array; provides two hardware write protect (WP) pins and Write disable command and software data protection; auto-timed write cycles (5ms max); high reliability; endurance: 1,000,000 write cycles; data retention: 40 years; lead/halogen-free devices; 8-lead JEDEC SOIC, 8-lead TSSOP and 8-pad UDFN packages; die sales options: wafer shape, waffle wrap and punch.

illustrate

The Atmel® AT25512 provides 524,288 bits of serial electrically erasable programmable read-only memory (EEPROM), 65,536 words per 8 bits. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation is essential. These devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP and 8-pad UDFN packages. Additionally, the device operates from 1.8 volts to 5.5 volts.

The AT25512 is enabled via the chip select pin (CS) and via a three-wire interface including serial data input (SI), serial data output (SO) and serial clock (SCK). All programming cycles are fully automatically timed and no separate erase cycle is required before writing.

Block write protection is enabled by programming the status register, which can be the top 1/4, the top 1/2, or the entire write protection array. Separate program enable and program disable instructions provide additional data protection. Hardware data protection is provided via the WP pin to prevent accidental writes to the status register. The hold pin can be used to suspend any serial communication without resetting the serial sequence.

1. Pin configuration and pins

2. Absolute Maximum Ratings*

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and does not imply that the functional operation of the device under these or any other conditions is beyond that specified in the operating section of this specification. Long-term exposure to absolute maximum rating conditions may affect device reliability.

3. Block diagram

5. Serial interface description

Master: The device that generates the serial clock.

Slave: Since the serial clock pin (SCK) is always an input, the AT25512 always operates as a slave.

Transmitter/Receiver: The AT25512 has separate pins for data transmission (SO) and reception (SI).

Most Significant Bit: The Most Significant Bit (MSB) is the first bit sent and received.

Serial opcodes: After the device is selected, CS will go low and the first byte will be received. This byte contains the opcode that defines the operation to be performed.

Invalid opcode: If an invalid opcode is received, no data will be moved to the AT25512 and the serial output pin will (hence) remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize serial communication.

Chip Select: When the CS pin is low, the AT25512 is selected. When no device is selected, data will not be accepted through the SI pin and the SO pin will remain in a high impedance state.

Hold: The hold pin is used in conjunction with the CS pin to select the AT25512. When the device is selected and the serial sequence is in progress, Hold can be used to suspend serial communication with the master device without resetting the serial sequence. To suspend, the hold pin must be pulled low while the SCK pin is low. To resume serial communication, hold the pin high while the SCK pin is low (SCK can still toggle during the hold). When the SO pin is in a high impedance state, the input to the SI pin will be ignored.

Write Protect: When held high, the Write Protect pin (WP) will allow normal read/write operations. When the WP pin goes low, the WPEN bit is 1, and all writes to the status register are disabled. While CS is still low, WP going low will interrupt a write to the status register. If an internal write cycle has been initiated, WP going low has no effect on any writes to the status register. When the WPEN bit in the status register is zero, the WP pin function is blocked. This will allow the user in a system where the WP pin is grounded and still be able to write to the status register. When the WPEN bit is set to 1, all WP pin functions are enabled.

Figure 5-1. SPI serial interface

6. Function description

The AT25512 is designed to interface directly with the Synchronous Serial Peripheral Interface (SPI) of the Type 6800 series microcontrollers.

The AT25512 uses an 8-bit instruction register. The description list and its operation codes are shown in Table 7-3. All instructions, addresses and data are transferred MSB first, starting with a CS transition from high to low.

Write Enable (WREN): When VCC is applied, the device will power up in a write disabled state. Therefore, all programming instructions must be preceded by a write-enable instruction.

Write Disable (WRDI): To prevent accidental writes to the device, the Write Disable instruction disables all programming modes. The WRDI instruction has nothing to do with the state of the WP pin.

Read Status Register (RDSR): The Read Status Register instruction provides access to the Status Register.

The ready/busy and write-enabled status of the device can be determined by the RDSR instruction. Similarly, the block write protection bits indicate the extent of the protection employed. These bits are set using the WRSR instruction.

Write Status Register (WRSR): The WRSR instruction allows the user to select one of four protection levels. The AT25512 is divided into four array segments:

1. None or

2. Top quarter (quarter) or

3. The upper part (1/2) or

4. All memory segments can be protected

Therefore, any data within any selected segment will be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4.

The three bits BP0, BP1 and WPEN are non-volatile cells that have the same properties and functions as conventional memory cells (eg WREN, tWC, RDSR).

The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin by using the Write Protect enable (WPEN) bit. When the WP pin is low and the WPEN bit is one. Hardware write protection is disabled when the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the status register (including the block protection bit and the WPEN bit) and the block protection portion of the memory array are disabled. Only memory segments that are not block protected are allowed to be written.

Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP pin is held low.

Read Sequence (Read): The following sequence is required to read the AT25512 through the SO pin. After the CS line is pulled low to select a device, the read opcode is transmitted over the SI line, followed by the byte address to be read (see Table 6-6). When done, any data on the SI line is ignored. The data (D7–D0) is then moved to the SO row at the specified address. If only one byte is read, then the CS line should be driven high after the data is output. Since the byte address is auto-incremented, data will continue to be shifted out, so the read sequence can continue. When the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read cycle.

Write Sequence (Write): In order to program the AT25512, two separate instructions must be executed. First, the device must enable writing via the write Enable (WREN) instruction. The write command can then be executed. Additionally, the address of the memory location to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands except the RDSR instruction are ignored.

Write commands require the following sequence. After the CS line is pulled low to select the device, the write opcode is transmitted over the SI line, followed by the byte address and the data to be programmed (D7–D0 (see Table 6-6). The program will follow after the CS pin is brought high Startup. (After the D0 (LSB) data bit is clocked in, a low-to-high transition of the CS pin must occur immediately within the SCK low time.

The ready/busy status of the device can be determined by initiating the Read Status Register (RDSR) instruction. If bit 0=1, the write cycle is still in progress. If bit 0=0, the write cycle has ended. During a write programming cycle, only the Read Status Register instruction is enabled.

The AT25512 is capable of performing page write operations of 128 bytes. After each byte of data is received, the seven low-order address bits are internally incremented by one; the high-order bits of the address remain unchanged. If more than 128 bytes of data are transferred, the address counter will roll over and the previously written data will be overwritten. The AT25512 automatically returns to the write disable state at the end of the write cycle.

NOTE: If the device is not write enabled (WREN), the device will ignore the write command and return to the standby state when CS is raised. A new CS falling edge is required to restart serial communication.

7. Timing diagram (SPI mode 0 (0, 0))

8. Packaging information

8.1, 8S1-8 lead JEDEC SOIC

8.2 8X-8 lead TSSOP

Note: 1. This picture is for reference only. Refer to JEDEC Drawing MO-153, Change AA, for correct dimensions, tolerances, datums, etc.

2. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs must not exceed 0.15mm (0.006in) per side.

3. Dimension E1 does not include flash or protrusion between leads. Flashes and protrusions shall not exceed 0.25 mm (0.010 in) between wires on each side.

4. Dimension b does not include Dambar protrusions. Under the maximum material condition, the allowable protrusion of the dam bar should exceed 0.08mm of the b dimension. Dambar cannot be located in the lower radius of the foot. The minimum spacing between protrusions and adjacent wires is 0.07mm.

5. Dimensions D and E1 are determined at the reference plane H.

9.3 8Y7 — 8-pad UDFN