6506 -ic/" title="ISL6506 Product Specifications, Documentation and Sourcing Information" target="_blank">ISL6506 complements other power modules (voltage regulators) in ACPI compliant designs for microprocessor and computer applications. Integrated Circuits Integrates control of 5V dual rail and 3.3V dual rail into an 8-pin EPAD SOIC package. The ISL6506 operating mode (active output or sleep output) is selectable with two digital control pins, S3# and S5#. A fully integrated linear regulator Generates 3.3V from ATX power supply 5VSB output of dual voltage planes in sleep state (S3, S4/S5). In active state (during S0 and S1/S2), the ISL6506 uses an external N-channel channel to connect the output directly to 3.3V The input MOSFET is powered by the ATX power supply with minimal loss. The ISL6506 turns on the ATX 5V output state of the 5V dual power supply active NMOS transistor, or switches the ATX5VSB (or (PNP) transistor in the S3 sleep state through the PMOS. In the S4/S5 sleep state Under ISL6506 and ISL6506B 5V dual output is off. In ISL6506A, 5V dual output remains on during S4/S5 sleep state. Functionally, ISL6506 and ISL6506B are the same. This however, ISL6506B has an internal 3.3V LDO while ISL6506 has 1A Current Limit. The current limit of 3.3V inside the ISL6506A is 1A LDC.

feature

Provides 2 ACPI control voltages - 5V dual USB/keyboard/mouse -3.3VDUAL/3.3VSB PCI/auxiliary/LAN

Excellent 3.3V dual regulation in S3/S4/S5 - over temperature ±2.0% - 1A capability on ISL6506 and ISL6506A - 2A capability on ISL6506B

Small size; very low external component count

Over temperature shutdown

Lead-free available (RoHS compliant)

application

ACPI Compliant Motherboard Power Specifications - ISL6506, ISL6506B: 5V Dual-Machine Shutdown on S4/S5

Sleep State - ISL6506A: 5V duplex stays on in S4/S5 sleep state

Absolute Maximum Ratings Thermal Information

Supply voltage, V5VSB. +7.0V

DLA. Ground -0.3V to +14.5V

all other pins. +7.0V

ESD classification (Human Body Model). pending

Recommended Operating Conditions

Supply voltage, V5VSB. +5V±5%

Minimum 5VSB supply voltage guaranteed parameters. +4.5V

Digital inputs, VSx. 0 to +5.5V

Ambient temperature range. 0°C to 70°C

junction temperature range. 0°C to 125 °C

Thermal Resistance (Typical) θJA (Celsius/Watt) θJC (Celsius/Watt)

EPSOIC package (Note 1, 2). 40 3.5

Maximum Junction Temperature (Plastic Packaging). 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

(SOIC - lead only)

See Technical Brief TB389 for recommended soldering conditions.

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Function pin description

VCC (pin 1) provides a very well decoupled 5V bias supply for the IC. This pin is connected to the ATX5VSB output. This pin provides all biasing for the IC as well as the internal spare 3V3AUX LDO. The voltage on this pin is monitored for power-on-reset (POR) purposes. Ground (Pin 5, Pad) The IC's signal ground. These pins are also ground return to the internal 3V3AUX active in the LDOS3/S4/S5 sleep state. All voltage levels are used on these pins. S3# and S5# (pins 3 and 4) These pins change the operating state of the IC from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are digital inputs with an internal 10µA pull-down current source per pin. Additional circuitry prevents illegal state transitions such as S4/S5 to S3. Connect S3 and S5 to the SLP-S3 and SLP-S5 signals of the computer system. 3V3AUX (pin 2) Connect this pin to the 3V3 dual output. The voltage on this pin in sleep state is passed through the internal transmission device powered from 5VSBY through the VCC pin. In the active state, the ATX 3.3V output is delivered to this node through a fully on NMOS transistor. During states S3 and S4/S5, this pin is monitored for undervoltage events. DLA (Pin 6) This pin is an open-drain output. A 1kΩ resistor must be connected from this pin to the ATX 12V output. This resistor is used to pull the gate of the appropriate N-mosfet to 12V, in the active state, the switch ATX 3.3V and 5V outputs are input to the 3.3VAUX and 5V dual outputs respectively. This pin can also be used to monitor 12V rails during vehicle operation. If a resistor other than 1kΩ is used, the POR level will be affected. 5VDLSB (Pin 7) Connect this pin to the gate of the appropriate P-MOSFET. ISL6506 and ISL6506B: In S3 sleep state, this transistor is on, connecting the ATX 5VSB output to the 5V binaural regulator output. ISL6506A: In S3 and S4/S5 sleep states, this transistor is on, connecting the ATX 5VSB output to the 5V binaural regulator output

illustrate

operate

The ISL6506 controls 2 output voltages, 3.3V dual output and 5 video. It is designed for microcomputer applications that require 3.3V, 5V, 5VSB and 12V bias input from ATX power supply. The integrated circuit consists of a linear circuit that provides the computer system's controller/regulator with 3.3V dual power supply, 5V dual voltage supply, and all control and monitoring functions necessary to complete ACPI implementation. Initialization The ISL6506 automatically initializes power when it receives input. A power-on reset (POR) function continuously monitors the 5VSB input supply voltage. The island 6506 also monitors the 12V rail, making sure the ATX rail is up before entering the S0 state, even if SLP_S3 and SLP_S5 are both high. The truth table for dual output operation is described in Table 1 with 3.3V dual output and 5V dual output. The internal circuit may not allow the transition from the S4/S5 state to the S3 state.

Functional Timing Diagram

Figure 1 (ISL6506/B) and Figure 2 (ISL6506A) are simplified timing diagrams detailing all outputs (S3#) that respond to the state of the sleep state pins, and the state of the incoming ATX power supply. Not shown in these diagrams is for Protection against false sleep state tripping. In addition, the ISL6506 has a 60 microsecond delay for transition from S0 to S3 state. This immediately transitions from S0 state to S4/S5 state.

soft start

Figures 3 and 4 show a typical application launching into a sleep state. At time T0, 5VSB (bias) is applied to the circuit. At time T1, 5VSB exceeds the POR level. Time T2, a soft-start interval T1, indicates the start of soft-start. 3.3V dual rail via internal backup LDO via internal digital soft-start function. Figure 4 shows the track where the 5V video starts soft-starting at time T2. The 6506A island will pull 7.5µA into 5VDLSB for one soft-start cycle. This current will boost the P-MOSFET (Q2, see in a controlled manner. At time T3, the 3.3VDUAL is in regulation and the 5VDLSB pin is pulled to ground. If the 5V dual rail does not reach the level of the 5VSB rail at T3, then the rail will When the P-MOSFET gate is fully open, experience a sudden step boost. A soft-start profile for 5VDUAL might be to put a capacitor on the P-MOSFET. Adding this capacitor increases the gate capacitance and slows down the start-up 5V dual rail. At time T4, The system has transitioned to the S0 state and the supply of ATX has started to increase. Using the ISL6506/B (Figure 3), the 5V dual rail will pass from the 5VATX rail across the body diode of the N-MOSFET (Q3). The ISL6506A has installed the 5V dual rail regulation (Figure 3). 4). At time T5, the 12VATX rail has a POR level above 12V. Time T6 is the period after three soft starts exceed the 12V POR level. At time T6, three events occur simultaneously. The DLA pin is forced to a high impedance state, allowing the 12V rail Enhanced connection ATX rails are connected to 3.3V dual rail and 5V dual rail. The 5VDLSB pin is forced into a high impedance state, which will turn the P-MOSFET (Q2) off. Finally, the internal LLD 3.3VAUX rail is dormant and in standby state.

Sleep to Wake State Transition Figures 3 and 4, starting at time T4, depict the transition from the sleep state to the S0 wake state. Figure 3 shows the transition of the ISL6506/B from the S4/S5 state to the S0 state. Figure 4 shows how the ISL6506/B will enter the S0 state from the S3 sleep state. Figure 3 also shows the ISL6506A in the S0 transition state from S3 or S4/S5. For all transitions, T4 describes the system transitioning to the S0 state. Here, the ATX feed is enabled and begins to accelerate. At time T5, the 12VATX orbit has exceeded the POR threshold of ISL6506/B and ISL6506A. The start period after the three soft time T5, time T6, occurs simultaneously with three events. The DLA pin is forced to high impedance allowing the 12V rail to enhance the state of the two N mosfets (Q1 and Q3) that connect the ATX rail to the 3.3V dual rail and the 5V dual rail. The 5VDLSB pin is forced to a high impedance state (Q2) which will turn the P-MOSFET off. Finally, the track that regulates the 3.3 video's internal LDO in sleep is in standby.

Internal Linear Regulator Undervoltage Protection

The undervoltage protection of the internal linear regulator activates the ramp of the 3.3V linear regulator only during sleep state and after initial soft-start. The undervoltage trip point is set to 25% below nominal or 2.475V. When undervoltage is detected, the 3.3V linear regulator is disabled. After a soft-start interval, the 3.3V linear regulator retries through the soft-start ramp. If the linear regulator retries 3 times and the fourth undervoltage is detected, the 3.3V linear regulator is disabled and can only be reset by POR reset. Internal Linear Regulator Overcurrent Protection When an overcurrent condition is detected, the gate voltage to the internal NMOS pass element is reduced, which results in lowering the output voltage of the linear regulator. When the output voltage drops to the undervoltage trip point, the undervoltage protection is activated and the output will be turned off.

Layout Considerations

A typical application using the ISL6506 is direct implementation. Like other linear regulators, attention must be paid to a few potentially sensitive small signal components, such as sensitive nodes or nodes that provide critical bypass currents. Power components (through transistors) and controller ICs should come first. The controller should be placed centrally on the motherboard, not too far from the 3.3V dual island or I/O circuits. Make sure the 3V3AUX connection is properly sized to carry 1A with significant resistive losses at the load side. Similarly, the input bias supply (5VSB) has a similar level of current - for best results, make sure it is connected through properly sized traces and properly separated. Power-on transistors should be placed to dissipate thermal pads that match the power of the device. Where applicable, multiple pass connections to large internal planes can significantly reduce local device temperature rise.

The placement of decoupling capacitors and bulk capacitors should reflect their purpose. Therefore, the high frequency decoupling capacitors should be as close as possible to the load, they are separated; those separated by the controller close to the controller pins, the decoupled pins are near the load connector or the load itself (if embedded). Even though the placement of bulk capacitance (aluminum electrolytic or tantalum) is key to the placement of high frequency capacitors, it is best to have these capacitors close to the load they serve. Place all small signal parts close to the pins of the control IC, and if applicable, through vias close to the ground pads.

A multilayer printed circuit board is recommended. Figure 5 shows the connections to most components on the track. Note that each capacitor shown can represent many physical capacitors. A solid layer dedicated to ground is connected to component terminals as close as possible to component ground connections through vias. The EPAD should be fixed to the ground plane with three to five vias for thermal management. Using another entity layer as a powered plane divides this plane into a common voltage level. Ideally, a powered aircraft should support both input power and output power nodes. Use copper-filled polygons on the top and bottom circuit layers to create power islands (output capacitors) and loads that connect the filter components. Use the remaining printed content for circuit layers for small signal routing.

Parts Selection Guide

Selection of Output Capacitors The output capacitors should be chosen to allow the output to meet the voltage active state operation (S0/S1) required for dynamic regulation. Load transient components of various microprocessor systems may need to provide high slew rate (di/dt) quality capacitors present demand. Therefore, output selection capacitors are recommended for transient load regulation, paying attention to their parasitic components (ESR, ESL). Additionally, on the 5V dual output during transitions between active and sleep states, no energized elements are conducting. During this time, the output capacitor must supply the output current. The output voltage drop during this period of time can be easily approximated by the formula:

ΔVOUT = output voltage drop

ESRUT = output capacitor bank ESR

IOUT = output current during conversion

COUT = output capacitor bank capacitance

tt = active-to-sleep/sleep-to-active transition time (typically 10 µs) The output voltage drop is largely dependent on the ESR (equivalent series resistance) output capacitor bank, capacitors should be chosen to ensure that the output voltage is above the minimum Level adjustment is allowed. Selection of Input Capacitors The input capacitors for the ISL6506/A application must have a sufficiently low ESR that does not allow excessive drop capacitors when the input voltage energy is transferred to the output. If the ATX power supply does not meet specifications, some unbalanced output between the ATX and the ISL6506/A's regulation level can have from the input capacitor to the provided output. In active and sleep states, these phenomena may be excessive 5VSB voltage dips affecting output regulation. The solution to such a potential problem is larger input capacitance and lower overall ESR.

Transistor Selection / Considerations

The ISL6506/A typically requires one P-channel and two N-channel mosfets. All three MOSFETs are utilized as switching elements. An important criterion for choosing a transistor switching element is that the package selection for efficient disassembly is hot. The power dissipated by the switching element when it is turned on

Choose to keep the attached package and heatsink temperatures below the rated values, up to the maximum expected ambient temperature. Q1, Q3 These N-channel mosfets are used to switch the 3.3VATX supply to provide 5V input to 3.3VAUX and a dual output of 5V in the active (S0, S1) state. The primary criterion for selecting these transistors is output voltage budgeting. The highest allowable maximum rDS(on) junction temperature can be expressed as the equation:

VINmin=minimum input voltage

VOUTmin = minimum allowable output voltage

IOUTmax = maximum output current

Question 2

This is a P-channel MOSFET that switches the 5VSBATX power supply output to a 5V dual output sleep state. The selection criterion for this device, like an N-channel mosfet, is the appropriate voltage budget. This, however, is only available at a gate-to-source voltage of 4.5V, so a true logic level is required to select the MOSFET.