The ISL6341, ISL6341A, ISL6341B, ISL6341C enable full control and protection schemes driven by DC/DC buck converters to synchronize N-channel mosfets in buck topology. Since it can work with 5V or 12V power supply ICs are available for the system. It integrates control, gate driver, output adjustment, monitoring and protection functions into a 10ld thin DFN package. The ISL6341, ISL6341A, ISL6341B, ISL6341C (hereafter referred to as "ISL6341x" unless required) provide a feedback loop response for fast transient voltage mode control. The output voltage is precisely regulated down to 0.8V with a maximum tolerance of ±0.8% over temperature and line voltage variation. The fixed frequency oscillator and wide duty cycle range reduce design complexity while balancing typical application cost and efficiency. The frequency, duty cycle and OCP response are the only differences between the ISL6341x versions. See Table 1. Overcurrent protection consists of monitoring the rDS(ON) of the lower MOSFET to inhibit proper operation of the PWM (see "Overcurrent Protection (OCP)"). This approach simplifies by eliminating the need for a current sense resistor. The output voltage is also monitored for undervoltage and overvoltage protection, in addition to the monitoring of the PGOOD output.

feature

Operating voltage from +4.5V to 14.4V (for biasing) -1.5V to 12V VIN input range (limited; see page 12) -0.8V to ~VIN output range (duty cycle limit) - Integrated gate driver; LGATE uses VCC (5V to 12V); UGATE uses external boot diode to (5V to 12V) -0.8V internal reference; ? 0.8% Tolerance Simple Single-Loop Control Design - Traditional Dual Edge Modulator - Voltage-Mode PWM Control - Driving N-Channel MOSFETs Fast Transient Response - High Bandwidth Error Amplifier - ISL6341, ISL6341C Maximum Duty Cycle 0% to 85% - 0% to 75% maximum duty cycle for ISL6341A, ISL6341B Lossless, programmable overcurrent protection - rDS (on) using lower MOSFET - latch off mode (ISL6341, ISL6341B) - infinite retry (hiccup) mode (ISL6341A) - infinite retry (hiccup) mode; no UVP (ISL6341C)

Output voltage monitoring

- Under-voltage and over-voltage shutdown - PGOOD output

Small Converter in 10 Ld 3x3 Thin DFN - 300kHz Fixed Oscillator (ISL6341, ISL6341C) - 600kHz Fixed Oscillator (ISL6341A, ISL6341B) - Fixed Internal Soft Start, Ability to Enter Pre-Bias Loading - COMP/EN Pin Enable/Disable Function Lead Free (RoHS Compliant)

application

Power Supplies for Microprocessors or Peripherals - Personal Computers, Servers, Storage Devices - Digital Signal Processors and Core Communications Processor Power Supplies

Subsystem Power - PCI, AGP; Graphics Card; Digital TV - SSTL-2 and DDR/DDR2/ DDR3 SDRAM Bus Termination Supply

Cable Modems, Set-Top Boxes, and DSL Modems

Industrial Power; Universal Power

5V or 12V input DC/DC regulator

Low-voltage distributed power sources; point-of-load

Absolute Maximum Ratings Thermal Information

Supply voltage (VCC). Ground -0.3V to 15V

Boot Voltage (VBOOT-GND). Ground -0.3V to 36V

Start-up to phase voltage (VBOOT-VPHASE…). Ground -0.3V to 15V

-0.3V to 16V (<10ns, 10μJ)

Wear Voltage (VUGATE). Phase V -0.3V to VBOOT+0.3V

Phase V -3.5V (<100ns pulse width, 2μJ) to VBOOT+0.3V

LGATE/OCSET voltage (VLGATE). Ground -0.3V to VCC+0.3V

GND-5V (<100ns pulse width, 2μJ) to VCC+0.3V

Phase voltage (V phase). Ground -0.3V to VBOOT+0.3V

Ground -8V (<400ns, 20μJ) to 30V (<200ns, VBOOT-GND<36V)

FB, VOS, COMP/EN voltage. Ground -0.3V to 6V

PGOOD voltage. Ground -0.3V to 7V

Thermal Resistance (Typical) θJA (Celsius/Watt) θJC (Celsius/Watt)

10 Ld TDFN package (Note 1, 2). 44 Article 3.5

Maximum power consumption. 1.0W

Maximum Junction Temperature (Plastic Packaging). +150 degrees Celsius

Maximum storage temperature range. -65°C to +150°C

Lead-free reflow profile.

operating conditions

Supply voltage range, VCC. +4.5V to 14.4V

Ambient temperature range

ISL6341xCRZ (commercial). 0°C to +70°C

ISL6341xIRZ (Industrial). -40°C to +85°C

junction temperature range. -40°C to +125°C

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may affect product reliability and

cause malfunctions not covered by the warranty.

notes:

1. θJA is measured with components with "direct attach" characteristics mounted on a high efficiency thermal conductivity test board in free air.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications Test Conditions: VCC=12V, TJ=0°C to +85°C, unless otherwise noted. Min and/or max parameters Unless otherwise specified, limits are 100% tested at +25°C. Temperature limits determined by characterization are also not production testing.

Electrical Specifications Test Conditions: VCC=12V, TJ=0°C to +85°C, unless otherwise noted. Min and/or max parameters Unless otherwise specified, limits are 100% tested at +25°C. Temperature limits determined by characterization are also not production testing. (continued)

notes:

3. Limits should be considered typical limits and no production testing is performed.

4. Limits determined by characterization, without production testing.

5. UVP disabled on ISL6341C; trigger point not measured.

Function pin description

VCC (Pin 6) This pin also provides the bias supply for the ISL6341x as the gate of the lower MOSFET. The internal regulator will bias the supply when VCC rises above 5V, but LGATE/OCSET will still be sourced by VCC. Connect a well decoupled 5V to the 12V supply at this pin. FB (Pin 8) This pin is the inverting input of the internal error amplifier. Use FB, in conjunction with the COMP/EN pin, to compensate for the converter's voltage control feedback loop. A resistor divider from VOUT to FB to GND is used to set the regulation voltage. VOS (Pin 9) This input pin monitors the regulator output for OV and UV protection, and PGOOD (OV and UV). Connect the resistor divider from VOUT to VOS to GND, with the FB resistor divider. It is not recommended to share a distributor for FB and VOS; responses to faults may not be as fast or robust. There is a small pull-up bias current on the pin; if the VOS pin is not connected, the OV protection will trip to protect the load. Ground (Pin 5) This pin represents the IC's signal and power ground. This pin is a high current connection and should be connected with the lowest impedance ground island/plane available. The metal pads under the wrap should also be connected to the ground plane for thermal conductivity, but not conductive. Phase (pin 2) connects this pin to the power supply of the upper MOSFET, and the drain of the lower MOSFET. It is used as a wear driver and monitors low MOSFET overcurrent protection. This pin is also monitored by the adaptive shoot-through protection circuit to determine when the upper MOSFET is turned off. Wear (pin 3) connects this pin to the gate of the upper MOSFET; it provides gate drive controlled by PWM. It is also determined by the adaptive penetration protection circuit when the upper MOSFET is turned off. Sheath (Pin 1) This pin provides the ground referenced biasing MOSFET driver to the top. The bootstrap circuit is used to generate a voltage suitable for driving an N-channel MOSFET (equal to the VGD negative bootstrap diode voltage drop), with respect to phase. COMP/EN (Pin 7) This is a multiplexed pin. During soft-start and normal inverter operation, this pin represents the output of the error amplifier. Use COMP/EN in conjunction with the FB pin to compensate the converter's voltage control feedback loop.

Pulling compressor/EN low (nominal voltage = 0.7V) disables the controller, which causes the oscillator to stop LGATE and the UGATE output to stay low, soft-starting the re-armed circuit. The external pull-down device will initially need to overcome up to 5mA of COMP/EN output current. However, once the IC is disabled, the COMP output will also be disabled, so only the 20µA current source will continue to draw current. When the pull-down is released, the COMP/EN pin will begin to rise at a rate of 20µA to charge the capacitor on the COMP/EN pin. When the COMP/EN pin is above the VENABLE trip point, the ISL6341x will start a new initialization and soft-start cycle. LGATE/OCSET (pin 4) connects this pin to the gate of the lower MOSFET; it provides gate drive (from VCC) controlled by PWM. This pin is also monitored by the adaptive shoot-through protection circuit to determine when the lower MOSFET is turned off. This pin is also used to determine the converter's overcurrent threshold during a short period of time after power-on reset (POR) or shutdown release. Connect a resistor (ROCSET) from this pin to GND. See "Over Current Protection (OCP)" for equations on page 8. See Table 1 for a summary of current responses. Some text describing the LGATE function may make part of the OCSET name when it is discussed with. PGOOD (Pin 10) This output is an open-drain pull-down device that reflects the state of the PGOOD comparator. The external pull-up resistor should be connected to a power supply of 6V or less. The output will remain low through the soft-start ramp and allow the voltage to be high at the end of the soft-start if the VOS voltage is at the window. The PGOOD window protects the window more tightly than the OV or UV window, giving early warning of problems. PGOOD does have a direct response to OCP conditions, but can also go lower if you go low enough before the fight. Figure 1 shows a simplified timing diagram. This power-on-reset (POR) function continuously monitors the bias voltage of the VCC pin. Once the Boolean threshold rises above (VPOR = 4.3V nominal), overcurrent protection (OCP) sample-and-hold operation is initiated for the POR function (when COMP/EN is ~1V). When sampling is complete, you start the soft-start ramp.

If the COMP/EN pin is held low during power-up, initialization is delayed until it is released and the COMP/EN voltage is above the ventable trip point. Figure 2 shows a typical power-up sequence in more detail. Initialization starts at t0 when either VCC rises to VPOR, or the COMP/EN pin is released (after POR). This COMP/EN will be sourced high by an internal 20µA current, but the timing will be when COMP/EN exceeds the ventable trip point (t1). The capacitance of the external disable device, as well as the compensation capacitor, will determine that the 20µA current source will charge the COMP/EN pin. with typical values, with soft-start time. The compressor/engine will continue to climb to ~1V.

From t1, there is a nominal 4ms delay, which allows the VCC pin to rise. Meanwhile, the LGATE/OCSET pin is initialized by disabling the LGATE driver and the graphics IOCSET (10µA nominal) via ROCSET. This produces a voltage representing the OCSET trip point of the OCP sample to maintain operation. The sample and hold uses a digital counter and DAC (to save the voltage so that the stored value does not drop) as long as VCC is above VPOR. See "Over Current Protection (OCP)" on page 8 for more details on the equations and variables. When the sample is completed and held at t2, the soft-start operation is initiated (~0.8ms delay to t3), and then the output voltage rises for about 4ms (0% to 100% between t3 and t4. The PGOOD output is allowed if VOS (and therefore VOUT) is at within PGOOD, then the t4 high window. Soft-start and pre-biased output Functionally, the soft-start internally ramps the reference to the non-inverting terminal of the error amplifier, from 0 to 0.8V nominally for 4ms. So the output voltage will follow Ramp, from zero to final value, in the same 4ms. Creates the gradient digitization, so there will be small discrete steps. There is no easy way to externally change the ramp rate as it is driven by the 300kHz (or 600kHz) switching frequency (As well as the ramp and the delay time is the same for both frequencies.) After the initialization period (t2 to t3), the error amplifier (COMP/EN pin) is enabled and starts regulating the output voltage of the inverter at soft start. The oscillator's triangular wave The voltage is compared to the ramp error amplifier. This produces a phase pulse of increased width to charge the output capacitor. When the internally generated soft-start voltage exceeds the reference voltage (0.8V), the soft-start is complete and the output should be at the expected voltage. This method provides In order to control the output voltage rise; there is no large inrush current to charge the output capacitor. The entire start-up sequence typically takes 9ms from POR; 5ms samples for delay and OCP, and 4ms for the soft-start ramp.

Figure 3 shows the normal VOUT curve in blue; initialization starts at t0 and the output ramps between t1 and t2. The ISL6341x will detect this if the output pre-bias is lower than the expected voltage value (as shown by the magenta curve). The voltage exceeds the output during the soft-start ramp; VOUT ramps seamlessly from there. There is a limit to the pre-bias situation; if the pre-bias VOUT is greater than VGD, the start cap may be discharged and will not restart. For example, if VIN=12V, VOUT=8V, the pre-bias is 6V, and VGD is only 5V, the residual voltage (wear) on the trunk lid will not be able to turn on the upper FET. The easy fix is to use 12V for VGD. The guideline is to make VGD-diode-Vth upper FET>VOUT to prevent this. If the output pre-bias is higher than the expected voltage value (as shown by the red curve), at the end of the soft-start, it will pull the output voltage down rapidly to the final value. Any resistive load connected to the output will help reduce the voltage (the RC rate capacitance at the load R and the output C).

If the pre-bias is high enough to trigger the OV protection (>1V on VOS); then LGATE will pulse to try to pull you low. The IC will continue to lock in this mode until the VCC supply is toggled. If the VIN (or VGD voltage-steering diode) of the upper MOSFET drain comes from another supply VCC behind, the soft-start will begin its cycle, but there will be no output voltage ramp. Once the undervoltage protection is enabled (at the end of the soft-start ramp), the output will latch. Therefore, for normal operation, the VIN (and VGD) must be high enough before or with VCC. If this is not possible, then another approach is to add sequencing logic to the COMP/EN pin to delay soft start until VIN (and VGD) power is ready. If the IC is disabled (by pulling the COMP/EN pin low) after soft-start, and then enabled (by releasing the COMP/EN pin), then full initialization (including a new OCP instance) will occur. If the output is shorted to ground during soft-start, the OCP will handle it as described in the next section.

Over Current Protection (OCP) The over current function protects the converter from short circuits using the lower MOSFET on-resistance rDS(ON) output, monitoring the current. Resistor (ROCSET) to overcurrent trip level (see "Typical Applications" on page 3). This approach increases the efficiency of the converter and reduces the cost by eliminating the current sense resistor. After the release of POR and COMP/EN, the ISL6341x enables overcurrent protection sample and hold operation. The LGATE driver is disabled to allow the internal 10µA current source to generate a voltage on ROCSET. The ISL6341x samples this voltage (referenced to the ground pin) at the LGATE/OCSET pin and fixes it at the counter and DAC combination. The sampling voltage remains the same internally as the overcurrent setpoint as long as power is applied, or until the computer is turned off when a new sample is taken from it. The actual monitoring of the low MOSFET on-resistance starts with a 200ns (nominal) signal (creating a rising external LGATE signal) after the edge of the internal PWM logic. This is to enable gate transition noise and ringing to be settled before the phase pins are monitored. Monitoring ends when the internal PWM edge (and therefore LGATE) goes low. OCP can be detected anywhere within the above window. In order to have enough time to detect OCP, the regulator will be limited to 300kHz (~75%, and the maximum wear duty cycle is ~85% at 600kHz); there will always be at least 300ns. This minimum width will also be used to start the refresh function. If the boot capacitor loses any charge as it wears out, it will be refreshed every cycle while LGATE is high. The ISL6341x share most of the detection circuitry; the main difference between them is what happens when detected. ISL6341, ISL6341B When overcurrent is detected (when LGATE is high), the logic will disable UGATE and keep LGATE high until the current drops to 1/2 of its programmed OCP value. This can take a few clock cycles and it prevents the current from building up too high. Once the current is low enough, UGATE goes high on the next PWM cycle, when LGATE goes high. If the OCP trips a second time, it will wait again until the current drops. If it trips a third time, it will die output (LGATE and UGATE low). If no OCP trips a retry, then the trip counter resets to zero and three new consecutive cycles are required to lock.

Figure 4 shows the typical waveforms of the ISL6341, ISL6341B, the normal inductor current is about 10A, and the stroke of the OCP is 16A. This is just an example; the actual waveform shape depends on the component values, as well as the load and short-circuit characteristics. On the third trip, the gate driver stops switching and the current disappears and returns to zero. To recover from this locked-off state, the user must toggle VCC (power down and power up) for a new POR, or toggle the COMP/EN pin for restart (including initialization and soft-start). The output voltage is also affected as the output inductor current rises and falls. Note that in extreme cases three times in a row, the UV light may actually be at the OCP. In either case, the IC provides protection, but maybe not exactly at the program current. OCP trips can be reset by toggling POR or COMP/EN, but trips can only be reset by toggling POR. See Table 2 for an overview of protection. Starting into a shorted load is handled the same; however the waveform may look different because the output is not but its final value. During soft-start, OCP is always enabled (UV is not present); it takes three consecutive times to lock. ISL6341A, ISL6341C Figure 5 shows the same conditions for ISL6341A, ISL6341C. For this version, when overcurrent is detected first (when LGATE is high), the logic will turn off the output (both LGATE and UGATE go low) and zero the current. It will then go into "hiccup" mode with infinite retries. After two o'clock the virtual softstart times out and the real softstart will begin. If the short remains, it will trip during the soft start ramp and another retry cycle will begin. Once the short circuit is removed the next soft-start is successful and normal operation can continue.

Figure 6 shows the ISL6341A and ISL6341C output response during a retry with the output shorted to ground. The output has turned off condition at time t0 due to the sensed overcurrent. There are two internal soft-start delay periods (t1) to cool down the mosfet, keeping the average power consumption at an acceptable level while retrying. At time t2, the output begins a normal soft-start cycle and the output tries to ramp. Still applies if short circuit , and during the soft-start ramp the current reaches the OCSET trip point anytime How long. Figure 6 shows an output moving up halfway before turning off; therefore, the retry (or hiccup) time is about 12ms. The minimum should be nominally 9.6ms, and the maximum should be 14.4ms. If the condition is eventually shifted Except, the output should increase normally on the next t2 cycle. Startup into a short circuit load looks the same as retrying into the same short circuit load. In both cases, OCP is always enabled on soft start; once tripped, a retry will be entered State (hiccup) mode. The retry period will always have two dummy timeouts, plus whatever portion of the actual soft-start time passes before detection and shutdown; at this point the logic immediately starts a new two dummy period timeouts. Both OCP and UVP Shorts to ground can be protected against, but the response (and recovery) is different, as shown in Table 2. For output components and shorting methods, it can be difficult to predict that the protection will trip first (too low output voltage, or too high current). ISL6341C remove Got this by disabling UVP and relying on OCP Co. Note that for the other 3 versions, if OCP trips first, UVP is prevented from tripping at the same time, so only OCP response (and recovery) is active.

Overcurrent Equation For all ISL6341x versions, the overcurrent function trips the inductor current peak (IPEAK) by typical). The variation of the OC trigger point in the system is mainly due to the rDS(ON) variation of the MOSFET (over process, current and temperature). Avoid overcurrent tripping under normal operating load ranges, from

Equation 1:

1. Maximum junction maximum rDS(on) temperature.

2. Minimum IOCSET "Table" on page 5 in "Electrical Specifications".

3. Determine IPEAK

For the equation for the ripple current, see "Selecting the Output Inductor" on page 15. The allowable voltage range detected (IOCSET*ROCSET) is 0 to 550mV; but the actual range is smaller for typical mosfets. The voltage drop is set too low (<~20mV) and can cause almost continuous OCP tripping. It is also very sensitive to system noise and can spike in rapids, so should be avoided. This is a maximum setting of 550mV, but most recommend the ISL6341x The mosfet doesn't need to handle the power of the max trip point. OCP cannot be disabled, but setting it higher than the max (>600mV) will be close; should be high enough in most cases (compared to the normal expected range) to appear disabled .No resistor can clamp max (unless loading on LGATE prevents node from fully charging). But no low voltage clamps LGATE so that it can rise above 3V and turn on for 4ms during sampling; pre-biased output may be released. So, to avoid this, but still approach disabling OCP, a resistor (>60kΩ) is recommended. Note that conditions during power-up may differ from normal operation. For example, when powering up the system at 12V, the IC starts above 4V work; if the supply ramp is slow, the soft-start ramp may have ended long ago reaching 12 volts. So when power is applied when the gate drive voltage is low, the rDS(ON) of the mosfet will be higher, effectively reducing catenary tripping. Also, The ripple current may be different at lower input voltages. Another factor is the digital nature of the soft-start ramp. Turning on each discrete voltage step, there is actually a small load transient and current spikes charging the output capacitor The height of the current spike is not controlled; it is affected by the step size of the output, the value of the output capacitor, and the compensation of the IC's error amplifier. So it is possible to trip over current due to inrush current in addition to normal load and ripple considerations .During soft-start, OCP is always enabled, so protection starts to short-circuited loads.

Undervoltage protection

Protect the output from undervoltage conditions by monitoring the VOS pin. An external resistor divider (similar to the ratio on the FB pin) makes the voltage equal to the 0.8V internal reference during normal operation. If the output is too low (25% below 0.8V = 0.6V, VOS nominal), the output will lock and both wear and LGATE are forced low. This requires switching VCC (shutdown and power on) to restart (toggling COMP/EN doesn't restart it). UV protection is not enabled until the end of the soft-start ramp (Figure 2). Figure 7 shows a pull vot (and thus VOS) down to 75%; both gate drivers stop switching, and you're dragged down by the riot, and the load, at a rate determined by conditions and output components. The ISL6341C version does not have UVP; it relies on OCP for shorted loads. The PGOOD UV comparator is separate and still active.

Over voltage protection

Protect the output from overvoltage conditions by monitoring the VOS pin, similar to undervoltage. If the output is too high (25% higher than 0.8V=1.0V, VOS is normal), the output will lock. As shown in Figure 8, UGATE will be forced low, but LGATE will be forced high (trying to pull the output down) until the output drops to 1/2 normal voltage (50% of 0.8V is 0.4V nominal on VOS). Well, LGATE will be off, but when the output is too high again. Overvoltage lockout shutdown requires switching VCC (de-energized and (switching COMP/EN will not restart it). OV until rising VCC POR trip point is exceeded. Fixed 25% above final expected voltage. OVP is not closed by tripping OCP ( But if OCP is off, UVP is off first.) If the VOS pin is open, there will be a small bias current on the chip that will force an overvoltage condition.

The PGOOD function output monitors the output voltage using the same VOS pin and undervoltage and overvoltage protection, but has separate comparators for each. Rising OV trigger point (10% above 0.8V = 0.88V (VOS nominal) and falling UV trigger point (10% below 0.8V = 0.72V nominal, VOS) will trip faster than protect, In order to avoid possible problems. The response time of the comparator should be less than 1 microsecond; the VOS input alone will not be slowed down by the compensation on the FB pin. It is not recommended to connect the VOS pin to the FB pin so that the resistor is shared Voltage divider. If the VOS code is accidentally disconnected, a small bias current on the chip will force an overvoltage condition. Figure 9 shows how the PGOOD output trips in all directions in response to a ramp (without reaching any protection trip point of ± 25%); as long as you are (and therefore VOS) within the ±10% window.

The PGOOD output is an open-drain pull-down NMOS device that can output 4.0mA of sink current power at 0.3V. The pull-up resistor voltage of the external power supply sets the high-level voltage when the power is good. This supply should be less than or equal to 6.0V and is usually the logic that monitors the PGOOD output. If the PGOOD function is not used, the PGOOD pin can be left floating. Once VCC is above the rising point, the PGOOD pin will remain low during soft-start (but if PGOOD is supplied before or when VCC is used, it may be pulled high until the logic has enough voltage to turn on the output). Once the soft-start ramp has completed (VOUT, VOS, and FB should each be at 100% of their final values), the PGOOD pin will be allowed to go up if the output voltage is within the expected window. There is no additional delay after the soft start is complete. Note that the direct effect of overcurrent protection is felt when you drop 10% before the output voltage is monitored. The overvoltage and undervoltage protection circuits do not directly affect PGOOD, but due to the tight UV and OV windows of PGOOD so far, the PGOOD output should have been low enough to trip the protection device.