feature

Ultra-low noise preamplifier (preamplifier) voltage noise = 0.74nV/√Hz; current noise = 2.5pa/√Hz; 3dB bandwidth; AD8331 : 120MHz; AD8332, AD8334 : 100MHz; low power; AD8331: 125 mW/ch; AD8332, AD8334: 145 mW/ch; wide gain range -4.5dB to +43.5dB with programmable postamp, low gain mode; 7.5dB to 55.5dB in high gain mode; low output Reference noise: 48 nV/√Hz typical; active input impedance matching optimized for 10-bit/12-bit ADCs; selectable output clamp levels; single 5 V supply operation; AD8332 and AD8334 leadframe chip scale packages not available .

application

Ultrasonic and sonar time gain control; high performance automatic gain control (AGC) system; high speed I/Q signal processing, dual ADC drivers.

General Instructions

The AD8331/AD8332/AD8334 are single, dual, and quad, ultralow noise, linear decibel, variable gain amplifiers (VGAs). Optimized for ultrasonic systems, they can be used as low noise variable gain elements at frequencies up to 120 MHz.

Each channel includes an ultra-low noise preamplifier (LNA), an X-AMP with a gain range of 48 dB; VGA and a selectable gain postamp with adjustable output limit. With single-ended input and differential output, the LNA gain is 19db. Using a single resistor, the LNA input impedance can be adjusted to match the signal source without affecting noise performance.

The 48dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained over the entire range. The gain control interface provides an accurate linear in-dB scale of 50 dB/V for control voltages between 40 mV and 1 V. Factory trimming ensures good section-to-section and channel-to-channel gain matching.

The differential signal path produces excellent second- and third-order distortion performance and low crosstalk.

The low output-referred noise of the VGA is beneficial for driving high-speed differential ADCs. The gain of the postamp can be pinned to 3.5db or 15.5db to optimize the gain range and output noise for 12-bit or 10-bit converter applications. The output can be limited to a user-selected clamp level, preventing the input of subsequent ADCs from being overloaded. An external resistor adjusts the clamping level.

The operating temperature range is -40°C to +85°C. The AD8331 is available in a 20-lead QSOP package, the AD8332 is available in a 28-lead TSSOP and 32-lead LFCSP package, and the AD8334 is available in a 64-lead LFCSP package.

test circuit

Measurement Considerations

Figure 55 to Figure 68 show typical measurement configurations and correct interface values for measurements at 50Ω.

The short-circuit input noise measurement is shown in Figure 62. The input-referred noise level is determined by dividing the output noise by the numerical gain between points A and B, taking into account the noise floor of the spectrum analyzer. Gain should be measured at each frequency of interest and at low signal levels since the 50Ω load is driven directly. The generator was removed for noise measurements.

theory of operation

Overview

The AD8331/AD8332/AD8334 work in the same way.

Figures 69, 70 and 71 are schematic diagrams of functional blocks for three devices

Each channel includes an LNA that provides user-adjustable input impedance termination, differential X-AMP VGA, and programmable gain amplifier with adjustable output voltage limit. Figure 72 shows one with external components.

In linear decibels, the gain control interface trims slope and absolute accuracy. The gain range is +48dB, extending from -4.5dB to +43.5dB (low gain) and +7.5dB to +55.5dB (high gain mode). The slope of the gain control interface is 50db/V, the gain control range is 40mv to 1v, and the gain expressions are equation 1 and equation 2.

The ideal gain characteristics are shown in Figure 73.

When the mode is pulled high (if available), the gain slope is negative as follows:

The LNA converts the single-ended input to a differential output with a voltage gain of 19 dB. If only one output is used, the gain is 13dB. The inverter output is used for active input impedance termination. Each LNA output is capacitively coupled to the VGA input. The VGA consists of a 48dB range attenuator and a 21dB gain amplifier for a net gain range of -27dB to +21dB. X-AMP gain interpolation technology has the advantages of small gain error, uniform bandwidth, and small differential signal path distortion.

The final stage is a logic programmable amplifier with a gain of 3.5dB or 15.5dB. LO and HI gain modes are optimized for 12-bit and 10-bit ADC applications based on output-referred noise and absolute gain range. The output voltage limit is user programmable.

Low Noise Amplifier (LNA)

The AD8331/AD8332/AD8334 have good noise performance at the beginning of the signal chain relying on a proprietary ultra-low noise preamplifier that minimizes the noise contribution in the following VGAs. Active impedance control optimizes the application of noise performance for input matching.

Figure 74 shows a simplified schematic of the LNA. INH is capacitively coupled to the source. The bias generator establishes a DC input bias voltage of 3.25 V and centers the output common-mode level at 2.5 V. Capacitor C (which can be the same value as input coupling capacitor C) is connected from the LMD pin to ground to disconnect the LMD bus. The LMD pin cannot be used to configure the LNA as a differential input amplifier.

The LNA supports differential output voltages up to 5 V pp with a positive and negative offset of ±1.25 V and a common-mode voltage of approximately 2.5 V. With a differential gain amplitude of 9, the maximum input signal before saturation is ±275 mV or +550 mV pp. Overload protection ensures fast recovery time from large input voltages. Very large inputs can be handled without interacting with ESD protection because the inputs are capacitively coupled to the bias voltage close to the mid-supply.

Low value feedback resistors and the current drive capability of the output stage allow the LNA to achieve low input-referred voltage noise of 0.74nv/√Hz. This is achieved with a current consumption of only 11 mA per channel (55 mW). On-chip resistor matching results in an accurate single-ended gain of 4.5× (9× differential), which is critical for precise impedance control. The use of fully differential topology and negative feedback minimizes distortion. Low HD2 is especially important in second harmonic ultrasound imaging applications. Differential signaling achieves less swing at each output, further reducing third-order distortion.

Active Impedance Matching

The LNA supports active impedance matching from pin LON to pin INH through an external shunt feedback resistor. The input resistance, RIN, is given in Equation 5, where A is the single-ended gain of 4.5 and 6kΩ is the unterminated input impedance.

CIZ needs to be in series with RIZ because the DC levels of Pin LON and Pin INH are not equal. The expressions for selecting RIZ and selecting CIZ based on RIN can be found in the "Application Information" section. CSH and ferrite beads enhance stability at high frequencies, reduce loop gain at high frequencies, and prevent peaking. The frequency response plots of the LNA are shown in Figure 23 and Figure 24. For a matched input impedance of 50Ω to 200Ω, the bandwidth is about 130 MHz and drops off at higher source impedances. The unterminated bandwidth (when R=∞) is about 80mhz.

In addition to the VGA's 100Ω input impedance (200Ω differential), each output can drive external loads as low as 100Ω. Capacitive loads up to 10 pF are allowed. All loads should be AC coupled. Typically, the Pin-LOP output is used as a single-ended driver for auxiliary circuits such as those used for Doppler ultrasound imaging. Pin LON drives R. Alternatively, a differential external circuit can be driven from both outputs in addition to the active feedback termination. In both cases, the important stability considerations discussed in the application information section should be carefully observed.

The impedance of each LNA output is 5Ω. When driving a VGA, the open-circuit gain is reduced by 0.4dB, and when a 100Ω load is added to the output, the open-circuit gain is reduced by 0.8dB. The differential gain of the LNA is improved by 6db. If the load on both sides is less than 200Ω, it is recommended to use a compensating load on the opposite output.

low noise

Input-referenced voltage noise has a significant limit on system performance. The short-circuit input voltage noise of the LNA is 0.74nv/√Hz or 0.82nv/√Hz (at maximum gain), including VGA noise. Open circuit, the current noise is 2.5pa/√Hz. These measurements were taken without feedback resistors and provided the basis for calculating the input noise and noise figure performance for the configuration in Figure 75. Figure 76 and Figure 77 show simulated and 4.1db noise figure (NF) measurements extracted from these results, with the input actively matched to a 50Ω source. Unterminated (R=∞) operation has the lowest equivalent input noise and noise figure. Figure 76 shows the noise figure versus source resistance, rising at low R, where the LNA voltage noise is larger than the source noise, and rising again at high R due to current noise. All curves include VGA input reference voltage noise of 2.7nv/√Hz.

The main purpose of input impedance matching is to improve the transient response of the system. When the resistor is terminated, the input noise increases due to the thermal noise of the matching resistor and the contribution of the LNA input voltage noise generator. However, in the case of active impedance matching, the contributions of both are 1/(1+LNA gain) less than that of the resistive termination. Figure 76 shows their relative NF performance. In this figure, the input impedance is swept with R to keep each point matched. The noise figures for the 50Ω source impedance are 7.1db, 4.1db, and 2.5db for resistive, active, and unterminated configurations, respectively. The noise figures for 200Ω are 4.6dB, 2.0dB, and 1.0dB, respectively.

Figure 77 is a graph of NF versus R for various RIN values, which is helpful for design. An NF platform that actively matches the input mitigates source impedance variations. For comparison, a preamplifier with a gain of 19db and a noise spectral density of 1.0nv/√Hz combined with a VGA of 3.75nv/√Hz produces a noise figure reduction of about 1.5db (for most input impedances), a significant Lower performance than AD8331/AD8332/AD8334.

The equivalent input noise of the LNA is the same for single-ended and differential output applications. In the absence of VGA noise, the LNA noise figure improves to 3.5db at 50Ω, but this does not include noise contributions from other external circuits connected to the LOP. When driving external circuits on separate boards, series output resistors are generally recommended for stability (see the Applications Information section). In low noise applications, ferrite beads are more ideal.

Variable Gain Amplifier

Differential X-AMP VGAs provide precise input attenuation and interpolation. It features low input-referred noise of 2.7nv/√Hz and good gain linearity. A simplified block diagram is shown in Figure 78.

X-AMP VGA

The input to the VGA is a differential R-2R attenuator ladder network with 6 dB steps per stage with a net input impedance of 200Ω differential. The ladder diagram is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. The LNA output is AC coupled to reduce offset and isolate its common mode voltage. The VGA input is biased to VCM via the center-tapped connection of the ladder, which is typically set to 2.5 V and bypassed externally to provide a clean AC ground. The signal level of the continuous stage in the input attenuator is stepped down from 0db to -48db in +6db steps. The input stage of the X-AMP is distributed along a staircase, and a bias interpolator controlled by the gain interface determines the input tap point. At overlapping bias currents, the signals from successive taps are combined to provide a smooth attenuation range from 0 dB to -48 dB. The circuit technology has good linear in-dB gain law consistency and low distortion, deviates from the ideal value of ± 0.2db or less. The gain slope is monotonic with respect to the control voltage and stable over process, temperature, and power supply.

The X-AMP input is part of the 12-gain feedback amplifier that completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and ensure good frequency response uniformity over the gain setting (see Figure 12 and Figure 13).

Gain control

The position along the VGA attenuator is controlled by a single-ended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scale is adjusted to 50 dB/V (20 mV/dB). Gain values outside the control range saturate to the minimum or maximum gain value. Both channels of the AD8332 are controlled by a gain interface to maintain matching. The gain can be calculated using Equation 1 and Equation 2. Gain accuracy is excellent, as both the scaling factor and absolute gain are factory trimmed. The total accuracy relative to the theoretical gain expression is ±1db for variations in temperature, process, supply voltage, interpolator gain ripple, trimming error, and tester limits. For a given set of conditions, the gain error relative to the line of best fit is typically ±0.2db. The gain matching between channels is better than 0.1db (Figure 11 shows the gain error at the center of the control range). When V<0.1 or >0.95, the gain error is slightly larger.

The gain slope can be reversed as shown in Figure 73 (except for the AD8332 AR model). The gain decreases with a slope of -50db/V over the gain control range from maximum gain to minimum gain. This slope is useful in applications such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. Inverse gain mode is selected by setting the mode pin to high gain mode.

Gain control response time is less than 750 ns, determined to within 10% of the final value of the change from minimum gain to maximum gain.

VGA noise

In a typical application, a VGA compresses a wide dynamic range input signal into the ADC's input range. When the LNA's input-referred noise limits the smallest resolvable input signal, it is primarily determined by the maximum instantaneous dynamic range that the VGA's output-referred noise limits can handle at any given gain control voltage. This limit is set according to the quantization noise floor of the ADC.

Figure 25 and Figure 27 plot the output and input noise (called a function of V) for the shorted input condition. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range.

The output-referred noise is flat over most of the gain range because it is dominated by the VGA's fixed output-referred noise. 48 nV/√Hz in low gain mode and 178 nV/√Hz in high gain mode. At the high end of the gain control range, LNA noise and source noise dominate. Input error noise reaches its minimum value near the maximum gain control voltage, where the input reference contribution of the VGA becomes very small.

At lower gains, input-referred noise, and therefore noise figure, increases with decreasing gain. However, the instantaneous dynamic range of the system is not lost due to the increased input capacity. The contribution of the ADC noise floor also has the same dependency. The important relationship is the size of the VGA output noise floor relative to the ADC.

These devices are ideal for driving low voltage ADCs due to their low output referred noise levels. The converter's noise floor drops by 12 dB per two bits of resolution, and at lower input full-scale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications Information section. The previous noise performance discussion applies to differential VGA output signals. While the LNA noise performance is the same in single-ended and differential applications, the VGA performance is different. When used single-ended, the noise of the VGA is significantly higher because the contribution of its bias noise is designed to cancel out in the differential signal. Transformers can be used in single-ended applications when low noise is required.

Gain control noise is a problem in very low noise applications. Thermal noise in the gain control interface can adjust the channel gain. The resulting noise is proportional to the output signal level and is usually only noticeable when large signals are present. Its effect is only observable in low gain mode, where the noise floor is significantly lower. The gain interface includes an on-chip noise filter that significantly reduces this effect at frequencies above 5mhz. Care should be taken to minimize noise impact at the gain input. An external RC filter can be used to remove V source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.

Common Mode Bias

An internal bias network is connected to an intermediate supply voltage to establish a common-mode voltage in the VGA and postamp. An external bypass buffer maintains the voltage. The bypass capacitor forms an important AC ground connection because there are many important connections inside the VCM network, including the center tap of the VGA differential input attenuator, the feedback network of the VGA fixed gain amplifier, and the postamp feedback network at both gain settings. For best results, use a 1 nF capacitor in parallel with a 0.1 μF capacitor, the 1 nF capacitor closest to the VCM pin. Provide separate VCM pins for each channel. For DC coupling to a 3V ADC, adjust the output common-mode voltage to 1.5V by biasing the VCM pin.

post amp

The last stage has a selectable gain of 3.5db (×1.5) or 15.5db (×6), set by the HILO logic pin. Figure 79 is a simplified block diagram.

A separate feedback attenuator enables two gain settings. They are chosen with appropriately scaled input stages to maintain a constant 3db bandwidth between the two gain modes (~150mhz). The slew rate is 1200 V/µs in high gain mode and 300 V/µs in low gain mode. The feedback networks for the high-gain and low-gain modes are fine-tuned at the factory to adjust the absolute gain of each channel.

noise

The topology of the postamp provides constant input referred noise with two gain settings and variable output referred noise. Output-referred noise (with gain) increases by 4 in high gain mode. This setting is recommended when driving converters with higher noise floors. The additional gain appropriately increases the output signal level and noise floor. The LO gain mode optimizes the output dynamic range when driving circuits with lower input noise.

Although the ADC's quantization noise floor depends on many factors, the 48 nV/√Hz and 178 nV/√Hz levels are well suited for the average requirements of most 12-bit and 10-bit converters, respectively. Another technique described in the application information section can extend the noise floor lower for possible use with 14-bit ADCs.

output clamp

The output is internally limited to a 4.5 V pp differential level when operating from a 2.5 V common-mode voltage. The postamp implements an optional output clamp via a resistor from RCLMP to ground. Table 8 lists the recommended resistor values.

The output clamp can be used for ADC input overload protection if desired, or for post-amplifier overload protection when operating at lower common-mode levels such as 1.5 V. The user should be aware that distortion products increase as the output level approaches the clamp level and the user should adjust the clamp resistor accordingly. See the Application Information section for additional information.

In LO or HI mode, the accuracy of the clamping level is about ±5%. Figure 80 illustrates the output characteristics of some RCLMP values.

application information

LNA - External Components

The LMD pin (connected to the bias circuit) must be bypassed to ground and the signal passed to the INH pin, which is capacitively coupled with a 2.2 nF to 0.1 μF capacitor (see Figure 81).

The unterminated input impedance of the LNA is 6 kΩ. The user can synthesize 50Ω and 6kΩ. R is calculated according to Equation 6 or selected from Table 7.

When using active input termination, a decoupling capacitor (CIS) is required to isolate the input and output bias voltages of the LNA. The parallel input capacitor CSH reduces gain peaking at high frequencies where active termination matching is lost due to gain attenuation of the LNA. The value of CSH decreases as RIN increases to 500Ω, where no capacitor is required. The recommended CSH values of 50Ω≤RIN≤200Ω are shown in Table 7.

When a long trace at pin INH is unavoidable, or if two LNA outputs drive external circuits, a small ferrite bead (FB) in series with pin INH maintains circuit stability with negligible effect on noise. Magnetic beads shown are 75Ω at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful.

Figure 82 shows the interconnection details of the LNA output. Since the DC levels at the LNA output and VGA input are different, and the offset of the LNA needs to be canceled, capacitive coupling between the two is required. The recommended capacitor value is 0.1µF. The gain loss between the LNA output and the VGA input is 0.4 dB due to the 5Ω output resistance. The additional loading of the LOP and LON outputs affects the LNA gain.

Both LNA outputs can be used to drive external circuits.

In cases where a single-ended LNA output is required, a Pin LOP should be used. The user should be aware of the stray capacitive loading of the LNA output, especially the LON. The LNA can drive 100Ω in parallel with 10 pF. If the LNA output is routed to a remote PC board, it can withstand up to 100 pF of load capacitance by adding 49.9Ω series resistors or ferrite 75Ω/100 MHz beads.

Gain input

The gain pins are common to both channels of the AD8332. The input impedance is nominally 10 MΩ, and a bypass capacitor of 100 pF to 1 nF is recommended.

Parallel devices can be driven by a common voltage source or a DAC. Decoupling should account for any bandwidth factors of the drive waveform, using total distributed capacitance.

If gain control noise in low gain mode becomes a factor, maintaining ≤15 nV/√Hz noise at the gain pins ensures satisfactory noise performance. Internal noise at the gain pin is less than 15 nV/√Hz. Gain control noise is negligible in high gain mode.

VCM input

The common mode voltage of Pin VCM, Pin VOL and Pin VOH defaults to 2.5v dc. For output AC-coupled applications, the VCM pins are unterminated; however, the AC ground of the internal circuitry must still be bypassed in close proximity. The VGA output can be dc connected to a differential load such as an ADC. Common mode output voltage levels between 1.5v and 3.5v can be achieved at Pin VOH and Pin VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving the load on a separate PC board.

The voltage on the VCM pin is provided by an internal buffer with an output impedance of 30Ω and a default output current of ±2mA (see Figure 83). If the VCM pin is driven by an external power supply, its output impedance should be less than 30Ω, and its current drive capability should be greater than 2mA. If the VCM pins of several devices are connected in parallel, the external buffer should be able to overcome their collective output current. When using a common mode voltage other than 2.5V, a voltage limiting resistor R is required to prevent overload.

Logic inputs ENB, MODE and HILO

All enable pins have a nominal 25 kΩ input impedance and can be pulled up to 5 V (pull-up resistors are recommended) or driven by any 3 V or 5 V logic family. Enable pin ENB powers down the VGA; when pulled low, the VGA output voltage is close to ground. Multiple devices can be driven from a common source. See Table 3, Table 4, Table 5, and Table 6 for information on the circuit functions controlled by the enable pins.

Pin HILO is compatible with 3v or 5v CMOS logic families. It is either grounded or pulled up to 5V depending on the desired gain range and output noise.

Optional output voltage limit

The RCLMP pin provides the user with a way to limit the output voltage swing when used with loads that do not prevent the input from overdriving a specified load. The peak-to-peak limit voltage is adjusted by a resistor to ground (see Table 8 for a list of voltage levels and corresponding resistor values). When not connected, the default limit level is 4.5 V pp. Note that the third harmonic distortion increases as the waveform amplitude approaches clip. For minimal distortion, the clamp level should be set higher than the converter input range. For the 1v pp linear output range, the recommended clamp level is 1.5vp-p; for the 2vp-p range, the recommended clamp level is 2.7vp-p; for 0.5vp-p operation, the recommended clamp level is 1vp-p. Experiments have determined the best solution. Figure 84 shows the third harmonic distortion as a function of the extreme level of the 2v pp output signal. A wider limit level is required in high gain mode.

output decoupling

An output network of resistors and/or ferrite beads can be used to ensure stability when driving capacitive loads greater than about 10 pF, or making long circuit connections on other boards. These components can be incorporated into a Nyquist filter, as shown in Figure 81. In Figure 81, the resistance value is 84.5Ω. For example, all evaluation boards in this series use 100Ω in parallel with a 120 nH bead. Low value resistors allow for nearby loads or gains less than 40dB. The exact values of these ingredients can be chosen empirically.

Anti-aliasing noise filters are often used with ADCs. Filter requirements depend on the application.

When the ADC is on a separate board, most filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge backoff at the ADC input. Any series resistors that exceed output stability requirements should be placed on the ADC board. Figure 85 shows a second-order low-pass filter with a bandwidth of 20 MHz. The capacitors are chosen along with the ADC's 10pf input capacitance.

drive the ADC

The output drivers can accommodate various ADCs. The noise floor requirement for a VGA depends on many application factors, including bit resolution, sample rate, full-scale voltage, and the bandwidth of the noise/antialiasing filter. The output noise floor and gain range can be adjusted by selecting high or low gain mode.

The relative noise and distortion performance of the two gain modes can be compared in Figure 25 and Figures 31-41. The 48 nV/√Hz noise floor of the LO gain mode is suitable for converters with higher sampling rates or resolutions (eg, 12-bit). Both gain modes can accommodate ADC full-scale voltages up to 4v pp. Since the distortion performance remains favorable for output voltages up to 4vp-p (see Figure 36), the output-referred noise can be further reduced by using a resistive attenuator (or transformer) at the output. The circuit in Figure 86 has an output full-scale range of 2v pp, a gain range of -10.5db to +37.5db, and an output noise floor of 24nv/√Hz, making it suitable for some 14-bit ADC applications.

overload

When the gain is set unexpectedly high, these devices respond gracefully to large signals that overload their input stages and normal signals that overload the VGA. Each stage is designed for clean limited overload waveforms and fast recovery when gain settings or input amplitudes are reduced.

Signals greater than ±275mv at the LNA input are clipped to 5v pp differential before being fed into the VGA. Figure 48 shows the response to a 1v pp input burst. Symmetric overload waveforms are important in applications such as continuous wave Doppler ultrasound, where the spectrum of the LNA output during overload is critical. The input stage is also designed to accommodate signals up to ±2.5V without triggering the slow-set ESD input protection diodes.

Both stages of VGA are prone to overload. Post-amp limitations are more common, and the result is the cleanlimited output characteristic shown in Figure 49. Recovery is fast in all cases. The graph in Figure 87 summarizes the input signal and gain combinations that result in different types of overload.

The clamp interface mentioned in the output clamp section controls the maximum output swing of the postamp and its overload response. When the clamp feature is not used, the output level defaults to approximately 4.5 V pp differential, centered at 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of R should be chosen to ensure normal overload. For 1.5 V or 3.5 V common mode levels, the recommended value is 8.3 kΩ or less (for high gain mode, the recommended value is 7.2 kΩ). This limits the output swing to just over 2 V pp differential.

Optional input overload protection

Applications that apply high transients to the LNA input can benefit from the use of clamping diodes. A pair of back-to-back Schottky diodes can reduce these transients to manageable levels. Figure 88 illustrates how to connect such a diode protection scheme.

When choosing overload protection, the important parameters are the forward and reverse voltages and t (or ). The Infineon BAS40-04 series shown in Figure 88 has a  of 100 ps at 1 mA and a voltage of 310 mV. Many variants of these specifications can be found in the Supplier Directory.

Layout, Grounding and Bypassing

Due to their excellent high frequency characteristics, these devices are very sensitive to their PCB environment. Achieving the expected performance requires attention to details that are critical to a good high-speed board design.

A multilayer board with power and ground planes is recommended, with empty areas in the signal layers filled with ground planes. Make sure the power and ground pins provided for reliable power distribution to the device are connected. Disconnect power pins using surface mount capacitors as close to each pin as possible to minimize impedance paths to ground. Use a ferrite bead to disconnect the LNA power pins from the VGA power. Along with capacitors, ferrite beads eliminate unwanted high frequencies without reducing headroom. Use a larger value capacitor every 10 to 20 chips to separate residual low frequency noise. To minimize voltage drop, use a 5 V regulator for the VGA array.

Several important LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to pins VIN and VIP. The R must also be placed near the long pins. Resistors must be placed as close as possible to the VGA output pins, VOL and VOH, to mitigate the loading effects of the connected traces. Values are discussed in the Output Decoupling section.

Signal traces must be short and direct to avoid parasitic effects. When there are complementary signals, a symmetrical arrangement should be used to maintain waveform balance. When running differential signals over long distances, PCB traces should remain adjacent.

Multiple input matching

As shown in Figure 89, matching of multiple sources with different impedances can be accomplished. Relays and low supply voltage analog switches can be used to select between multiple supplies and their associated feedback resistors. An ADG736 dual SPDT switch is shown in this example; however, multiple switches can be used and the user can refer to the analog device selection guide for switches and multiplexers.

Disable LNA

Where accessible, connecting the LNA pin-to-ground de-energizes the LNA, resulting in a current reduction of about half. In this mode, the LNA input and output pins can be left unconnected; however, power must be connected to all power pins for the disable circuit to function properly. Figure 90 illustrates these connections using the AD8331 as an example.

Ultrasound TGC Application

The AD8332 is ideal for medical and industrial ultrasound applications. A key subsystem in such applications is the TGC amplifier, which provides the means for echolocation of ultrasound reflected energy.

Figure 91 through Figure 93 are schematic diagrams of a dual fully differential system using the AD8332 and AD9238 12-bit high-speed ADCs (conversion speeds up to 65 MSPS).

High Density Quad Layout

The AD8334 is an ideal solution for applications with limited board space. Figure 94 shows the four channels connected to this very compact quad VGA. Note that none of the signal paths cross, and all four channels are spaced to eliminate crosstalk.

In this example, all components shown are 0402 sized; however, the same layout is executable at the cost of more checkerboard area. The sketch also assumes that both sides of the printed circuit board are available for components, and that bypass and power supply decoupling circuits are on the routing side of the board.

AD8331 Evaluation Committee

General Instructions

The AD8331 evaluation board is a platform for testing and evaluating the AD8331 variable gain amplifier (VGA). The board is fully assembled and tested; the user only needs to connect an input signal, VGAIN source and a 5v power supply. The AD8331-EVALZ is lead-free and RoHS compliant. Figure 95 is a photo of the board.

User-supplied optional components

As shown in the schematic in Figure 96, the board provides optional components. Parts shown in black are for typical operation, parts shown in grey are installed by the user.

When shipped from the factory, the LNA input impedance of the AD8331-EVALZ is configured to be 50Ω to accommodate most signal generators and network analyzers. By varying the values of RFB and CSH, input impedances up to 6kΩ can be achieved. See the "How It Works" section for details on the functionality of this circuit. The typical values of input impedance and corresponding components are shown in Table 9.

The board is designed for use with 0603 size surface mount components.

Back-to-back diodes can be installed in position D3 if desired.

To evaluate the LNA as a standalone amplifier, install the optional SMA connectors LON and LOP and capacitors C1 and C2; 0.1µF or less typical. At R4 and R8, 0Ω resistors are installed unless capacitive loads greater than 10 pF are connected to the SMA connectors LON and LOP (like coax). In this case, small value resistors (68Ω to 100Ω) must be installed at R4 and R8 to maintain amplifier stability.

If output clamping is required, a resistor can be inserted at RCLMP.

The board is designed for use with 0603 size surface mount components. Back-to-back diodes can be installed in position D3 if desired.

To evaluate the LNA as a standalone amplifier, install the optional SMA connectors LON and LOP and capacitors C1 and C2; 0.1µF or less typical. At R4 and R8, 0Ω resistors are installed unless capacitive loads greater than 10 pF are connected to the SMA connectors LON and LOP (like coax). In this case, small value resistors (68Ω to 100Ω) must be installed at R4 and R8 to maintain amplifier stability.

If output clamping is required, a resistor can be inserted at RCLMP.

Measurement settings

The basic board connections for measuring bandwidth are shown in Figure 97. A 5V, 100mA minimum supply and a low noise, gain voltage reference supply are required. Table 10 lists the jumpers, and Figure 97 shows their function and location.

The preferred method of signal detection is a differential probe connected to VO, as shown in Figure 97. Single-ended loads can be connected using the board edge SMA connector VOH. Be sure to take into account the 25.8dB attenuation when using the board in this way. For the connection to the ADC, the 270Ω series resistors can be replaced with 0Ω or other appropriate values.

board layout

The EV kit circuit uses four conductor layers. The two inner layers are grounded, and all interconnecting circuits are on the outer layers. 99 to 102 illustrate copper patterns.

AD8331 Evaluation Board Schematic

AD8331 Evaluation Board PCB Layers

AD8332 Evaluation Committee

General Instructions

The AD8332-EVALZ is a platform for testing and evaluating the AD8332 variable gain amplifier (VGA). The board is assembled and tested at the factory, the user only needs to connect the signal and VGAIN source to a single 5v power supply. Figure 104 is a photograph of the circuit board assembly side, and Figure 105 is a schematic view. The AD8332-EVALZ is lead-free and RoHS compliant.

User-supplied optional components

The board was built and tested using the components shown in black in Figure 105. Provisions are made for optional components (shown in grey) that can be installed at the user's discretion for testing. The default LNA input impedance is 50Ω to match various signal generators and network analyzers. Input impedances up to 6kΩ can be achieved by varying the values of RFBx and CSHx. For reference, Table 11 lists the common input impedance values and corresponding adjustments. The board is designed for use with 0603 size surface mount components.

SMA connectors S2, S3, S6 and S7 are provided to access the LNA output or VGA input. If the LNA is used alone, 0.1µF coupling capacitors can be installed at C5, C9, C23, and C24. If the load capacitance seen by the LNA output is greater than about 10 pF, a 68Ω to 100Ω resistor may be required.

If output clamping is required, a resistor can be inserted at RCLMP. Adjust the peak-to-peak clamp level by installing one of the standard 1% resistor values listed in Table 8.

A high-frequency differential probe connected to the 2-pin header VOx is the preferred method for viewing VGA output waveforms. A typical setup is shown in Figure 106. Single-ended loads can be connected directly via board edge SMA connectors. Note that the AD8332 output amplifier is buffered by a 237Ω resistor; therefore, if a low impedance is connected to the output SMA, be sure to compensate for the attenuation.

Measurement settings

The basic board connections for measuring bandwidth are shown in Figure 106. A 5 V, 100 mA (min) supply is required, and a low noise voltage reference supply is required to obtain VGAIN.

board layout

The EV kit circuit uses four conductor layers. The two inner layers are the power and ground planes, and all interconnect circuits are on the outer layers. 108 to 111 show copper patterns.

Schematic diagram of the evaluation committee

AD8332 Evaluation Board PCB Layer

AD8334 Evaluation Committee

General Instructions

The AD8334-EVALZ is a platform for testing and evaluating the AD8334 variable gain amplifier (VGA). The board is assembled and tested at the factory, and the user only needs to connect the signal source, gain source, and a 5V power supply. Figure 113 is a photograph of the circuit board. The AD8334-EVALZ is lead-free and RoHS compliant.

Configure Input Impedance

The board was built and tested using the components shown in black in Figure 115. Provisions are made for optional components (shown in gray) that can be installed by the user. When shipped, the input impedance of the low noise amplifier (LNA) is configured to 50Ω to match the output impedance of most signal generators and network analyzers. Input impedances up to 6 kΩ can be achieved by varying the values of feedback resistors RFB1, RFB2, RFB3, RFB4 and parallel capacitors C6, C8, C10, and C12. For reference, Table 12 lists the 1% resistor standard values for some typical input impedance values. Of course, if the user has determined that the source impedance falls between these values, the feedback resistor value can be calculated accordingly. Note that the board is designed to accept standard surface mount, size 0603 components.

Drive a VGA from an external source or use an LNA to drive an external load

If the user wishes to drive the VGA or evaluate the LNA output directly from an external source, the appropriate components can be installed. If the LNA is used to drive off-board loads or cables, a small value series resistor (47Ω to 100Ω) is recommended for LNA decoupling. These can be installed in R10, R11, R14, R15, R18, R19, R22 and R23 spaces.

Surface mount SMA connectors are specified and can be used to drive from any direction. If the LNA is not used, it is recommended to carefully remove capacitors C16, C17, C21, C22, C26, C27, C31 and C32 to avoid driving the output of the LNA.

Use a clamp circuit

The board is shipped with no resistors installed in the space provided for clamp circuit operation. Note that each pair of channels shares a common clamp resistor. If output clamping is required, resistors are installed in R49 and R50. The peak-to-peak clamp level depends on the application.

Observe the signal

The preferred signal detector is a high impedance differential probe such as the Tektronix P6247, a 1 GHz differential probe connected to a 2-pin header (VO1, VO2, VO3, or VO4) as shown in Figure 116. The probe's low capacitance has the least impact on device performance of any inspection method. The probe can also be used to monitor the input signal at IN1, IN2, IN3 or IN4. It can be used to probe other circuit nodes; however, be aware that the 200 kΩ input impedance can affect some circuits.

Provides a differential-to-single-ended transformer for single-ended output connections. Note that if a 50Ω load is connected to the header, a series resistor is provided to prevent accidental output overloading. Of course, the role of these resistors is to limit the bandwidth. If the load connected to the SMA is greater than 500Ω, the 237Ω series resistors RX1, RX2, RX3, RX4, RX5, RX6, RX7, and RX8 can be replaced with 0Ω values.

Measurement settings

The basic board connections for measuring bandwidth are shown in Figure 116. A 5V, 200mA (minimum) supply, and a low noise voltage reference supply are required for gain.

board layout

The EV kit circuit uses four conductor layers. The two inner layers are grounded, and all interconnecting circuits are on the outer layers. Figures 117 to 120 illustrate copper patterns.

Schematic diagram of the evaluation committee

AD8334 Evaluation Board PCB Layers

Dimensions