I have a black gold AX309 board in my hand. The pin header spacing of the Jtag port is 2.0mm, while the download line spacing on my zturn board is 2.54mm, which is embarrassing. Then soldered an adapter board to solve it, but it was more troublesome. The most important thing is that the device cannot be found on the ISE. I don't know if I soldered it firmly or if I plugged and unplugged the JTAG port with power on (plugging and unplugging the JTAG port with power on will damage the JTAG port pins of the FPGA chip. ).

It stands to reason that now the board is advanced, there should be a protection circuit, but still be cautious.
The correct plug-in power-on sequence:

1. Turn off the power of the FPGA development board;

2. Connect the JTAG emulator to the FPGA development board through the JTAG cable;

3. Insert the USB cable into the USB port of the emulator (the other end needs to be plugged into the computer)

4. Turn on the power switch on the FPGA development board

The key is to power up last.

The correct power-off and wire-pulling sequence:

1. Turn off the power of the FPGA development board;

2. Unplug the USB cable on the downloader;

3. Unplug the JTAG connection on the FPGA development board.

The key is to turn off the power first.

How to check whether the FPGA pins of the JTAG port are broken down?

Because I usually have a cheap hand, I may "operate with electricity" without paying attention. One or two times may be all right, but if you often walk by the river, you will never get your shoes wet. This time, it may be dangerous. After eliminating the problem of the download cable itself, if the JTAG port of the FPGA cannot be accessed, it is likely that the pins of the JTAG port on the FPGA chip are damaged. The inspection is also very simple. Just use a multimeter to check the TCK, TMS, TDO in the JTAG port. Whether and TDI is shorted to GND, that is, it is grounded. If any signal is shorted to the ground signal, it indicates that the JTAG signal pin is damaged.

USB

Cause Analysis:

For some low-end chips, in order to save costs and simplify the design, the FPGAIO unit does not have a protection circuit. If it is plugged with power, there will be a certain probability of static electricity and surge on the JTAG port, which will eventually lead to the breakdown of the FPGA pins (the IO port of the FPGA). If you add a diode clamp protection circuit, it will not be a problem).

FPGA program programming method - AS, PS JTAG

There are three types of configuration download methods for FPGA devices:

1. Active configuration (AS)

2. Passive configuration (PS)

3. JTAG

AS mode (Active Serial configraTIon mode): The FPGA acts as a controller every time it is powered on, and the FPGA device guides the configuration operation process. It controls the external memory and initialization process, and actively sends a read data signal to the configuration device, thereby converting the EPCS* * The data is read into the FPGA to realize the programming of the FPGA.

PS mode (Passive Serial configaraTIon mode): The configuration process is controlled by an external computer or controller, and is completed by configuration devices such as enhanced configuration devices ( EPC16 , EPC8). As a control device, EPCS regards the FPGA as a memory, and writes data into the FPGA to realize the programming of the FPGA. This mode can realize the online programming of the FPGA.

JTAG mode: JTAG is directly programmed into the FPGA. Since it is programmed into the SRAM, it needs to be re-programmed after a power failure. AS is programmed into the FPGA's configuration chip (for example, the bit file can be programmed into the FPGA first. It is saved on the Flash on the board. After each power-on, the FPGA will automatically read and write the Flash to program the FPGA).