6306 -ic/" title="ISL6306 Product Parameters, Documentation and Sourcing Information" target="_blank">ISL6306 controls the microprocessor core voltage regulation through the parallel. Polyphase buck converter structure using interleaved timing to multiply the channel ripple Frequency reduces input and output ripple current. Low ripple results in fewer components, lower component cost, lower power dissipation, small loss, and small implementation area. Microprocessor loads can generate extremely fast edge rates for load transients. Features of ISL6306 is a bandwidth control loop and ripple frequencies up to >4MHz to provide the best response to transients. Today's microprocessors require tight control of the output voltage position versus load current (drop). The Island 6306 utilizes a patented technique to measure the current on the next turn-on Voltage on resistor RDS(on) Output inductor mosfet or DCRMOSFET conduction spacing when low voltage. Current sensing provides signals required for accuracy degradation, channel current balance and overcurrent protection. Programmable implementation of internal temperature compensation function to effectively compensate for current sensing Element. Provides a unity gain differential amplifier for remote voltage sensing. Any potential difference between remotes uses the remote amplifier. Elimination of ground differences improves regulation and protection accuracy. Threshold sensitive enable input can be used for precise coordination using any other voltage rail to start ISL6306. Dynamic Video 8482 ; technology allows seamless real-time video changes. Offset pin allows precise voltage offset settings independent of video settings

feature

Precision Polyphase Core Voltage Regulation - Differential Remote Sensing Voltage - Over Life, Load, Line and Temperature - Adjustable Accuracy Reference Voltage Offset

Accurate RDS (on) or DCR current sensing - Accurate load line programming - Accurate channel current balancing - Differential current sensing

Microprocessor Voltage Recognition Input - Dynamic Video™ Technology - 8-bit video input with selectable VR11 code and extended VR10 code at 6.25mV per bit - 0.5V to 1.6V operating range

Thermal monitoring

Integrated programmable temperature compensation

Power Threshold Sensitive Enable Function Sequencing and VTT Enable

overcurrent protection

Over voltage protection

2, 3 or 4 phase operation

Adjustable switching frequency per phase up to 1MHz

Package Options - QFN Compliant with JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Area; Improved PCB Efficiency, Thinner Profile

Lead-free plus annealed (RoHS compliant) available

200320130334.png" />

Absolute Maximum Ratings

Supply voltage, VCC. +6 volts

all pins. Ground -0.3V to VCC+0.3V

SD (human body model). >2kV

ESD (machine model). >200V

ESD (charging unit model). >1.5kV

operating conditions

Supply voltage, VCC. +5V±5%

Ambient temperature (ISL6306CRZ). 0°C to 70°C

Ambient temperature (ISL6306IRZ). -40°C to 85°C

Hot information

Thermal Resistance (Note 1, 2) θJA (Celsius/Watt) θJC (Celsius/Watt)

QFN package. 34 6.5

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct connect" characteristics.

2. For θJC, the "case temperature" location is the center of the exposed metal pad on the bottom of the package.

Electrical Specifications Operating Conditions: VCC=5V, unless otherwise specified

Electrical Specifications Operating Conditions: VCC=5V, unless otherwise specified (continued)

notes:

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Specifications are guaranteed by design.

5. During the soft-start process, VDAC first rises from 0 to 1.1V, and then rises to the VID voltage after receiving a valid VID.

6. The soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at a rate of 6.25 mV/cycle.

Function pin description

VCC - Provides the power needed to operate the chip. When the voltage on this pin exceeds the rising POR threshold, and the voltage on this pin falls below the falling POR threshold. Connect this pin directly to the +5V supply. GND—The bias and reference ground of the integrated circuit. The metal base of the bottom ISL6306 is GND. EN_PWR - This pin is a threshold sensitive enable input controller. Connect the 12V supply to EN_PWR to provide synchronous power-on of the controller and MOSFET driver IC through an appropriate resistor divider. The ISL6306 activates when the EN_PWR drive voltage is higher than 0.875V depending on the state of EN_VTT internal POR and pending fault state. Driving the PWR below 0.745V will clear all fault conditions and initiate a soft start when the ISL6306 is re-enabled. EN_VTT - This pin is an input to another threshold sensitive enable controller. It is usually connected to the VTT output of a voltage regulator on the computer motherboard. When EN_VTT is driven above 0.875V, the ISL6306 activation depends on the state of ENLL, internal POR and pending fault state. Driving the vehicle below 0.745V will clear all faults and re-enable the ISL6306 state and start to soft start. FS - Use this pin to set the desired switching frequency. A resistor from FS to ground will set the switching frequency. The relationship between the resistor values and the switching frequency will be approximated by the equation. SS - Use this pin to set the desired start-up oscillator frequency. A resistor soft-start ramp rate from SS to ground will be set. The relationship between the value of resistance and the soft-start ramp time is described by an approximate equation. Video 7, Video 6, Video 5, Video 4, Video 3, Video 2, Video 1 and Video 0 - these are the reference voltages for generating the output regulation. Connecting these pins turns on sinking outputs (with or without external pull-ups) with resistors or active pull-up outputs. All video pins have 40µA voltages above logic high. These inputs can be external voltages up to VCC+0.3V.

When shutting down the video code results in a shutdown, the controller needs to be reset before rebooting. VRSEL - Use this pin to select the internal video code. When it is grounded, select the extended VR10 code. When floating or pulled high, select VR11 code. This input can be pulled up to VCC plus 0.3V. VDIFF, VSEN, and RGND—VSEN and RGND form a precision differential sense amplifier. This amplifier converts the differential voltage at the remote output to a single-ended voltage referenced to the local ground. VDIFF is the output and input protection circuit of the amplifier. Connect VSEN and RGND to the pins of the sense remote load. The input and output inversions of the FB and COMP-errors are amplified, respectively. FB can be connected to VDIFF through a resistor. Correct selection of resistors When IDROOP, VDIFF and FB can set the load line (droop) pin tied to the FB pin. The droop scaling factor is set by the ratio of ISEN resistor and inductor DCR or lower MOSFET RDS(on). COMP compensates the regulator through an external RC network. The DAC and REF-DAC pins are the precision output internal DAC references. REF pin is the error amplifier. In a typical application, a 1kΩ, 1% resistor is used to generate a precision offset voltage between the DAC and REF. This voltage is proportional to the offset current by OFS to ground or VCC. Voltage Smoothing™ operation in Dynamic Video Surveillance using a capacitor between REF and ground. Pulse width modulated output. Connect these pins to the Intersil driver chip. The number of active channels is determined by the state of PWM3 and PWM4. Connect PWM3 to VCC to configure for 2-phase operation. Connect PWM4 to VCC to configure three-phase operation.

ISEN1+, ISEN1-; ISEN2+, ISEN2-; ISEN3+, ISEN3-; ISEN4+, ISEN4-- The ISEN+ and ISEN- pins are the current sense inputs to the respective differential amplifiers. The sensed current is used for channel current balancing, overcurrent protection, and droop regulation. Inactive channels should keep their respective current sense inputs open (for example, to open ISEN4+ and ISEN4- for three-phase operation). For DCR sensing, connect each ISEN-pin to a node between the RC sense elements. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, rising. Voltage and inductor current across a sense capacitor. Therefore, the induced current is proportional to the inductor current and rises according to the inductor. When configured for RDS(ON) current sensing, the ISEN1-, ISEN2-, ISEN3-, and ISEN4- pins are grounded MOSFET sources on the lower side. ISEN1+, ISEN2+, ISEN3+, and ISEN4+ pins are pinned to virtual ground. Therefore, a resistor, connected to these current sense pins and the drain terminal of the associated lower MOSFET makes the current proportional to the current flowing through that channel. The induced current is caused by the negative voltage on the low FET when it is energized, it is caused by the RDS(on) and the rising channel current. ISL6306 No. 12 FN9226.0 March 9, 2006 VR_dy-VR_dy indicates that the soft start has been completed and the output voltage is within the regulation range of the video setting. It is an open-drain logic output. VR_RDY will be pulled low when OCP or OVP occurs. It will also be to pull the threshold lower if the output voltage falls below the undervoltage.

The OFS-OFS pin provides a way to program the DC offset current input that produces a DC offset voltage at the reference voltage. Offset current and accurate internal voltage reference are generated through external resistors. Polarity Select the offset by connecting a resistor to GND or VCC. For no offset, the OFS pins should remain unterminated. TCOMP - Temperature Compensated Scaling Input. This effectively compensates the current sense element using the voltage sensed on the TM pin as the input for temperature adjustment of the ldroop and overcurrent protection limits. To implement comprehensive temperature compensation, the resistor divider circuit requires one resistor to be connected from TCOMP to VCC of the controller and another resistor being connected from TCOMP to GND. Changing the ratio value of the resistor will set the gain compensation of the integrated heat. When the function is not used when temperature compensation is integrated, please connect TCOMP to GND. IDROOP-IDROOP is the output pin that senses the average value of the channel current proportional to the load current. In applications that do not require a load line, leave this pin open. In applications that require a load line, connect this pin to FB so that the average current sensed will flow through the resistor between FB and VDIFF creating a voltage drop proportional to the load current. TM-TM is an input pin for virtual reality temperature measurement. Connect this pin to ground and the controller's Vcc resistor through an NTC thermistor. The voltage on this pin is inversely proportional to the VR temperature. The ISL6306 monitor is based on the TM pin voltage and outputs VR_HOT and VR_FAN signals. VR_HOT - VR_HOT is used as an indicated temperature for high VR. It is an open-drain logic output. It will turn on when the measured VR temperature reaches a certain level. VR_FAN-VR_FAN is an output pin output with open-drain logic. When the measured virtual reality temperature reaches a certain level.

Operating Multiphase Power Conversion The microprocessor load current profile has been changed to state that the advantages of multiphase power conversion are impossible to ignore. The technical challenges associated with producing single-phase converters are both cost-effective and thermally feasible, forcing a move to multi-phase cost-saving approaches. The ISL6306 controller helps to reduce the minimum output components by integrating important functions and requirements. Blocks 4, 5, 6, and 7 on the page provide a top-level view of the polyphase power conversion using the ISL6306 controller. The switching of each channel in an interleaved polyphase converter is a symmetrical out-of-phase channel with respect to each other. In a three-phase converter, each channel switches 1/3 of the loop after the previous channel, while tracking the channel. Therefore, the combined ripple frequency of the three-phase converter is higher than the ripple frequency of any one phase. Furthermore, the peak-to-peak amplitude reduction of the combined inductor current is proportional to the number of phases (Equations 1 and 2). Ripple frequency increases and ripple amplitude decreases. Designers can use less inductance per channel and lower total output capacitance specifications for any performance. Figure 1 illustrates the frequency of the multiplication effect of the output ripple. The three channel currents (IL1, IL2 and IL3) are combined to form the AC ripple current and the DC load current. The ripple of the ripple component is the frequency of the current in each channel. Each PWM pulse in the previous stage. The peak-to-peak current per phase is about 7A, and the DC component of the inductor current combines to deliver the goods.

To understand the ripple current amplitude in a polyphase circuit, examine the peak-to-peak inductor current representing a single channel.

The output capacitor conducts the inductor current. In the case of multiphase converters the capacitive current is per individual channel. Combine Equation 1 with the expression for the peak-to-peak current after summing N symmetrically phase-shifted inductor current Equation 2. The peak-to-peak ripple current is reduced by an amount proportional to the number of channels. The output voltage ripple is a function of capacitance, equivalent series resistance (ESR) and inductor ripple current. Reducing inductor ripple current allows designers to use fewer or less expensive output capacitors.

Another benefit of interleaving is reducing input ripple current. The input capacitor section is determined by the maximum input ripple current. Multiphase topologies can increase overall system cost and scale by reducing input ripple, enabling designers to reduce the cost of input capacitors. The example in Figure 2 demonstrates the current total input ripple current into a three-phase converter. The converter shown in Figure 2 delivers 36A from a 12V input to a 1.5V load. The rms input capacitor current is 5.9A. Compare this to a single-phase converter for the same buck, which is 12V to 1.5V at 36A. The single-phase converter has 11.9A rms input capacitor current. Single-phase converters must use an input capacitor bank with twice the rms current capacity equivalent to three-phase converters. Figures 21, 22 and 23 in the section titled "Input Capacitors" selection can be used to determine the input capacitor RMS based on load current, duty cycle and channel. in determining the optimal input capacitance solution. Figure 24 shows a phase input capacitor rms current comparison. The timing of PWM operation for each channel is set by the number of active channels. The default channel setting for the ISL6306 is 4. The switching period is defined as the time between two pulse width modulation pulse termination signals for each channel. An end-of-pulse signal is an internally generated clock signal that triggers the falling edge of a pulse width modulated signal. The cycle time pulse termination signal is the inverse of the switch frequency set by a resistor between the FS pin and ground. When commanded by the clock signal, the channel PWM signal goes low at the beginning of each cycle. The pulse width modulated signal commands the MOSFET driver to open/close the channel Mossfett. For 4-channel operation, the channel trigger sequence is 4-3-2-1: PWM3 pulses are terminated after PWM4, 1/4 of a cycle after PWM2 is output after 1/4 of a cycle after PWM3, and PWM1 is terminated after PWM2 another 1/4 of a cycle. For three-channel operation, the channel trigger sequence is 3-2-1. Connect PWM4 to VCC to select three-channel operation at pulse termination intervals of 1/3 cycle increments. If PWM3 is connected to VCC, it is dual channel select operation, 1/2 one cycle after PWM2 pulse termination.

Once the PWM signal transitions low, it will remain low for a minimum of 1/3 cycle. Forced off-time requirements ensure accurate current samples. Current sensing is described in the next section. When the forced off time expires, the PWM output will be enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the sawtooth ramp as shown in Figure 7. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output is highly transitioned. The MOSFET driver detects the state of the PWM signal and turns off the MOSFET above it synchronously. The PWM signal starts the next cycle by triggering a low PWM signal at the end of pulse signal mark. Current Sampling During the forced off time after the PWM transitions low, the associated channel current sense amplifier uses the ISEN input to reproduce the inductor current, IL. The current is sampled from 1/6 each time PWM goes low and continues to sample 1/3 of the cycle, or until PWM goes high, whichever comes first. Whatever the current method of sensing, sensing current, Ethan, is just inductive current. Consistent with the falling edge of the PWM signal, the sample-and-hold circuit samples the sensed current signal as shown in Figure 3. Therefore, the sampling current In and the output current are maintained for one switching cycle. The sample current is used for current balancing, load line regulation and overcurrent protection.

Current sensing

The ISL6306 supports inductive DCR sensing, MOSFET RDS (on) sensing, or resistive sensing techniques. This internal circuit, shown in Figures 4, 5, and 6, represents one channel of the N-channel converter. This circuit is repeated for each channel in the converter, but the pins cannot be activated based on the state of PWM3 and PWM4, as described in the "Pulse Width Modulation Operation" section. Inductive DCR Inductive inductor windings have resistance (direct current resistance) parameters measured by DCR. Think of the inductive DCR as a separate concentrated quantity, as shown in Figure 4. This channel current IL flowing through the inductor also passes through the DCR. Equation 3 shows the equivalent voltage across the s-domain inductance VL.

The DCR voltage is extracted through a simple RC network of inductors, as shown in Figure 4. The voltage across the capacitor, VC, can be shown to be proportional to the channel current IL, see Equation 4.

If the RC network component is selected, the RC time constant (=R*C) is matched to the inductor time constant (=L/DCR), and the voltage across the capacitor VC is equal to the voltage drop across the DCR, which is proportional to the channel current.