Summary

High-performance signal processor for communications, graphics, and imaging applications; super Harvard architecture; four independent buses for dual data acquisition, instruction fetch, and non-intrusive I/O; 32-bit IEEE floating-point computing unit - multiplier, arithmetic Arithmetic and Shifter; Dual Port On-Chip SRAM with Integrated I/O; Peripherals - A Complete System-on-Chip; Integrated Multiprocessing; Key Features: 40 MIPS, 25 ns instruction rate, single-cycle instruction execution; 120 MFLOPS peak , 80 MFLOPS sustained performance; dual data address generator with modulo reverse addressing; efficient program sequencing loop with zero overhead: single-cycle loop setup; IEEE JTAG Standard 1149.1 test access port and on-chip emulation; 240 -lead thermally enhanced MQFP package; 225-ball Plastic Ball Grid Array (PBGA); 32-bit single-precision and 40-bit extended precision; IEEE floating-point data format or 32-bit fixed-point data format for parallel computing; and parallel single-cycle multiplication and arithmetic operations; dual memory read/write and Instruction Fetch; Accelerated Multiplication, Addition and Subtraction for FFT; Butterfly Computing; 2mbit On-Chip SRAM; Dual Port, Independent Access by Core Processor and DMA; Off-Chip Memory Interface; Page mode DRAM support.

DMA controller; 10 DMA channels for transfers between ADSP-21062s ; internal and external memory; peripherals, host processor, serial port, or link port; background DMA transfers at 40 MHz, with full-speed processing Host processor interface for 16-bit and 32-bit microprocessors; host can directly read and write ADSP-21062 internal memory; multiprocessing; glueless connection architecture for scalable DSP multiprocessing; distributed on-chip bus arbitration for parallel buses ; Connect up to six ADSP-21062s Plus mainframes; Six link port multiprocessing for point-to-point connections and arrays; 240 mbytes/s parallel bus transfer rate; 240 MB/s transfer rate through link ports; serial Line ports; two 40mbit/s synchronous serial ports with Com expansion hardware; independent transmit and receive functions.

General Instructions

This data sheet represents the production release specification for the ADSP-21062 (5 V) and ADSP-21062L (3.3 V) processors for the 33 MHz and 40 MHz speed grades. The product name "ADSP-21062" is used in this data sheet to refer to all devices unless expressly stated otherwise.

General Instructions

The ADSP-21062 SHARC Super Harvard Architecture Computer is a signal processing microcomputer that provides a new level of functionality and performance. The ADSP-21062 SHARC is a 32-bit processor digital signal processor application optimized for high performance. The ADSP-21062 uses the ADSP-21000 digital signal processor as the core to form a complete system-on-chip, adding a dual-port on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

The ADSP-21062 is manufactured in a high-speed, low-power CMOS process with an instruction cycle of 25ns and a working speed of 40MIPS. With the on-chip instruction cache, the processor can execute each instruction in one cycle. Table 1 shows the performance benchmarks of the ADSP-21062.

The ADSP-21062 SHARC represents a new signal computer integration standard that combines a high-performance floating-point digital signal processor core with integrated system-on-chip functionality, including a 2 Mbit SRAM memory (4 M bits on the ADSP-21060 megabits), host processor interface, DMA controller, serial and link ports, and glue-free parallel bus connections to DSP multiprocessing.

Figure 1 shows a block diagram of the ADSP-21062, illustrating the following architectural features: with shared data register file; data address generators (DAG1, DAG2); program sequencer with instruction cache; on-chip timing SRAM with off-chip memory and peripherals devices; host ports and multiprocessor interfaces; DMA controllers; serial and link ports; JTAG test access ports.

Figure 2 shows a typical uniprocessor system. The multiprocessing system is shown in Figure 3.

ADSP-21000 Series Core Architecture

The ADSP-21062 includes the following architectural features of the ADSP-21000 series core. The ADSP-21062 processor is code and function compatible with the ADSP-21020.

Independent parallel computing unit

The arithmetic/logic unit (ALU), multiplier, and shifter all execute single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. A single multifunction instruction performs parallel arithmetic unit and multiplier operations. These computational units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating-point, and 32-bit fixed-point data formats.

data register file

The general purpose data register file is used to transfer data between the computational unit and the data bus and to store intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows for unconstrained data flow between the compute unit and internal memory.

Single-Cycle Fetch of Instructions and Two Operands The ADSP-21062 has an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers instructions and data (see Figure 1). Thanks to its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from cache) in one cycle.

instruction cache

The ADSP-21062 includes an on-chip instruction cache that supports triple bus operations to fetch one instruction and two data values. The cache is selective, and only instructions that fetch conflict with PM bus data access are cached. This allows core, looping operations such as digital filter multiply-accumulate and FFT butterfly processing to be performed at full speed.

Data Address Generators with Hardware Circular Buffers The ADSP-21062's two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required for digital signal processing, typically used in digital filters and Fourier transforms. The two DAGs of the ADSP-21062 contain enough registers to create up to 32 circular buffers (16 primary register sets, 16 secondary register sets). DAGs automatically handle wrapping address pointers, reducing overhead, improving performance, and simplifying implementation. A circular buffer can start and end at any memory location.

Flexible instruction set

The 48-bit instruction word accommodates various parallel operations for concise programming. For example, the ADSP21062 can conditionally perform multiply, add, subtract, and branch in one instruction.

ADSP-21062/ADSP-21062L Features

Expanding the core of the ADSP-21000 series, the ADSP-21062 adds the following architectural features:

Dual-port on-chip memory

The ADSP-21062 contains two Mbits of on-chip SRAM, each organized into two 1 Mbits blocks that can be configured for different combinations of code and data storage. Each memory block is dual-ported and independently accessed in a single cycle by the core processor and the I/O processor or DMA controller. Dual-port memory and separate on-chip buses allow two data transfers from the core and one data transfer from the I/O in one cycle.

On the ADSP-21062, memory can be configured as a maximum of 64K words of 32-bit data, a maximum of 128K words of 16-bit data, a maximum of 40K words of 48-bit instructions (or 40-bit data), or a maximum of 2 Mbits of various word sizes combination. All memory can be accessed as 16-bit, 32-bit or 48-bit words.

A 16-bit floating-point storage format is supported, effectively doubling the amount of data that can be stored on-chip. Conversion between 32-bit floating-point and 16-bit floating-point formats is done in one instruction.

Although each memory block can store a combination of code and data, when one block stores data, the DM bus is used for transmission, and when another block stores instructions and data, the PM bus is used for transmission, and the access efficiency is the highest. Using the DM bus and PM bus in this way, each memory block has a dedicated bus, guaranteeing single-cycle execution of two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from the ADSP21062's external port.

Off-chip memory and peripheral interface The external port of the ADSP-21062 provides the interface between the processor and off-chip memory and peripheral devices. 4G of off-chip address space is contained in the unified address space of the ADSP-21062. Separate on-chip buses for PM address, PM data, DM address, DM data, I/O address, and I/O data are multiplexed on external ports to create a single 32-bit address bus and a single 48-bit (or 32-bit) data bus for the external system bus.

Addressing select signals for external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory banks. To simplify addressing of page-mode DRAMs, separate control lines are also generated. The ADSP-21062 provides programmable memory wait states and external memory acknowledgment control, allowing interfacing with DRAM and peripherals with variable access, hold, and disable time requirements.

host processor interface

The host interface of the ADSP-21062 allows easy connection to 16-bit and 32-bit standard microprocessor buses without additional hardware. Asynchronous transfers are supported at speeds up to the full clock rate of the processor. The host interface is accessed through the external port of the ADSP-21062, and the memory is mapped into the unified address space. The host interface has four DMA channels; code and data transfers are done with low software overhead.

The host processor requests the ADSP-21062's external bus using the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-21062, and can access the DMA channel settings and mailbox registers. Vectored interrupt support is provided for efficient execution of host commands.

DMA controller

The ADSP-21062's on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisible to the processor core, allowing DMA operations to occur while the cores are executing their program instructions concurrently.

DMA transfers can occur between the ADSP-21062's internal memory and external memory, external peripherals, or the host processor. DMA transfers can also occur between the ADSP-21062's internal memory and its serial or link ports. DMA transfers between external memory and external peripherals are another option. Perform external bus packing of 16-, 32- or 48-bit words during DMA transfers.

The ADSP-21062-2 provides 10 DMA channels through the link port, 4 through the serial port, and 4 through the processor's external port (for host processor, other ADSP-21062s, memory, or I/O transfers). Four additional link port DMA channels are shared with serial port 1 and external ports. Programs can be downloaded to the ADSP21062 using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using the DMA request/grant lines (DMAR1-2, DMAG1-2). Other DMA features include generating interrupts when DMA transfers are complete, and DMA chains for automatically chaining DMA transfers.

serial port

The ADSP-21062 features two synchronous serial ports that provide an inexpensive interface to a variety of digital and mixed-signal peripherals. The serial ports can run at the full clock rate of the processor, with a maximum data rate of 40mbit/s per port. Separate transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred between on-chip memories via DMA. Each serial port provides TDM multi-channel mode.

Serial ports can use little-endian or big-endian transfer formats, and word lengths can be selected from 3 to 32 bits. They offer selectable synchronization and transmission modes and selectable μ-law or A-law companding. Serial port clock and frame synchronization can be generated internally or externally.

multiprocessing

The ADSP-21062 provides powerful functions tailored for multiprocessor DSP systems. The unified address space (see Figure 4) allows direct inter-processor access to each ADSP21062's internal memory. Distributed bus arbitration logic is included on-chip for simple, glue-free connection of systems consisting of up to six ADSP-21062s and a host processor. The main processor switch incurs only one cycle of overhead. Bus arbitration can choose between fixed priority or rotating priority. Bus locks allow an indivisible read-modify-write sequence of semaphores. Provides vectored interrupts for interprocessor commands. On the link port or external port, the maximum throughput of data transfer between processors is 240 MB/s. Broadcast Write allows simultaneous transmission of data to all ADSP-21062s and can be used to implement reflected semaphores.

link port

The ADSP-21062 has six 4-bit link ports that provide additional I/O capabilities. Link ports can be clocked twice per cycle, allowing each port to transmit eight bits of data per cycle. Link port I/O is particularly useful for point-to-point interprocessor communication in multiprocessing systems.

Link ports can work independently and simultaneously, with a maximum data throughput of 240mbytes/s. Link port data is packed into 32-bit or 48-bit words that can be read directly by the core processor or transferred by DMA to on-chip memory.

Each link port has its own double-buffered input and output registers. The clock/answer handshake controls link port transfers. Transmissions can be programmed to send or receive.

program start

The ADSP-21062's internal memory can be booted from an 8-bit EPROM, the host processor, or through one of the link ports at system power-up. Boot source selection is controlled by the BMS (boot memory select), EBOOT (EPROM boot) and LBOOT (link/host boot) pins. 32-bit and 16-bit host processors are available for booting.

development tools

The ADSP-21062 supports a complete set of software and hardware development tools, including the EZ-ICE inner loop simulator, EZ-LAB® development board, EZ-KIT and development software. EZ-LAB includes an evaluation board with an ADSP-21062 (5 V) processor and provides a serial connection to a PC. SHARC EZ-KIT combines ADSP21000 series development software for PC and development board for EZ-LAB ADSP-21062 in one software package. In addition to the EZ-LAB development board, the EZ-KIT includes an optimizing compiler, assembler, instruction-level simulator, runtime libraries, diagnostic utilities, and a complete set of example programs.

The same EZ-ICE hardware can be used with the ADSP-21060/ADSP-21061 to fully emulate the ADSP-21062, except for the display and modification of two new motion registers. The simulator does not display these two registers, but your code can use them.

ADSP-21000 series development software for analog devices includes easy-to-use assembler based on algebraic syntax, assembly library/library, linker, instruction-level simulator, ANSI C optimizing compiler, CBug 8482 ; C-class source-level debugger, And a C runtime library containing DSP and math functions. The optimizing compiler includes numerical C extensions based on the work of the ANSI Numerical C Extensions group. Numerical C provides the C language with array selection, vector math, complex data types, loop pointers, and extended dimensional arrays of variables. ADSP-21000 series development software is available for PC and Sun platforms.

The ADSP-21062 EZ-ICE emulator uses the IEEE1149.1 JTAG test access port of the ADSP-21062 processor to monitor the target board processor during the emulation process. EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers, and the processor stack. Non-intrusive in-circuit emulation is ensured by using the processor's JTAG interface. The emulator does not affect the loading or timing of the target system.

More details and ordering information are available in the ADSP-21000 Series Hardware and Software Development Tools Data Sheet (ADDS-210xx-Tools). This data sheet is available from any analog sales office, dealer or documentation center.

In addition to the software and hardware development tools provided by the emulation devices, third parties also provide a range of tools that support the SHARC processor family. Hardware tools include SHARC PC add-in cards, multiprocessor SHARC VME boards, and daughter card modules with multiple SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third-party software tools include Ada compilers, DSP libraries, operating systems, and block diagram design tools.

Additional Information

This data sheet provides an overview of the architecture and functionality of the ADSP-21062. For details on the ADSP-21000 series core architecture and instruction set, refer to the ADSP-21062 SHARC User Manual Second Edition.

Pin function description

The ADSP-21062 pin definitions are shown below. All pins are the same on the ADSP-21062 and ADSP-21062L. Inputs identified as synchronous must meet the timing requirements of CLKIN (or TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asynchronously asserted as CLKIN (or asynchronously asserted as TCK for TRST).

Except for ADDR31-0, DATA47-0, FLAG3-0, SW and inputs with internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS), Unused inputs should be tied to VDD or GND or pulled and TDI) - these pins can be left floating. These pins have a logic level hold circuit that prevents the input from floating internally.

A = Asynchronous G = Ground I = Input O = Output P = Power S = Synchronous (A/D) = Active Drive (O/D) = Open Drain T = Three states (when SBTS is asserted, or when ADSP- 21062 is a bus slave).

EZ-ICE Probe Target Board Connector

The ADSP-2106x EZ-ICE emulator uses the IEEE1149.1JTAG test access port of the ADSP-2106x to monitor the target board processor during the emulation process. The EZICE probe requires that the CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals of the ADSP-2106x are accessible on the target system through a 14-pin connector (2 row x 7-pin strip header), as shown in Figure 5 . The EZ-ICE probe plugs directly into this connector for analog chips on the board. This connector must be added to the target board design if the ADSP-2106x EZ-ICE is to be used. The total trace length between the EZ-ICE connector and the farthest device sharing the EZ-ICE JTAG pins should be limited to a maximum of 15 inches for guaranteed operation. This length limit must include EZ-ICE JTAG signals routed to one or more ADSP-2106x devices, or a combination of ADSP2106x devices and other JTAG devices on the chain.

14-pin, two-row needle bar header keyed in pin 3 position - pin 3 must be removed from the header. Pins must be 0.025 inches square and at least 0.20 inches long. Pin spacing should be 0.1 x 0.1 inches. Pin leads are available from suppliers such as 3M, McKenzie, and Samtec.

BTMS, BTCK, BTRST and BTDI signals are provided so that the test access port can also be used for board level testing. When the connector is not used for emulation, place a jumper between the BXXX pin and the XXX pin as shown in Figure 5. If you are not going to use the test access port for board testing, connect BTRST to GND and BTCK to or pull up to VDD. The TRST pin must be asserted after power is applied (via BTRST on the connector) or held low for the ADSP-2106x to function properly. No BXXX pins (pins 5, 7, 9, 11) are connected to the EZ-ICE probes.

The JTAG signal is terminated on the EZ-ICE probe as follows:

Figure 6 shows the JTAG scan path connections for a system containing multiple ADSP-2106x processors. Connecting CLKIN to pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when instructed to perform operations such as starting, stopping, and single-stepping multiple ADSP-2106xs in a synchronous manner. If you don't need to synchronize these operations on multiple processors, just connect pin 4 of the EZ-ICE header to ground.

If simultaneous multiprocessor operation is required, CLKIN is connected, and the clock skew between multiple ADSP21062 processors and the CLKIN pins on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may shut down one or more cycles between processors. For synchronous multiprocessor operation, TCK, TMS, CLKIN, and EMU should be considered critical signals in terms of skew and should be scheduled on your board for as short a time as possible. If TCK, TMS and CLKIN are driving a large number of ADSP-21062s (more than 8) in your system, then treat them as "clock trees" using multiple drivers to minimize skew. (See "JTAG Clock Tree" and "Clock Distribution" in the "High-Frequency Design Considerations" section of the ADSP2106x User Manual, Second Edition, in Figure 7.)

If synchronous multiprocessor operation is not required (i.e. CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of tilt.

For complete information on SHARC EZ-ICE, see the ADSP-21000 Series JTAG EZ-ICE User Guide and Reference.

Power consumption ADSP-21062 (5V)

These specifications apply only to the internal power supply portion of VDD. Calculations of external supply current and total supply current can be found in the power dissipation section of this data sheet. For a full discussion of the code used to measure power consumption, see the tech note "SHARC Power Consumption Measurements".

Power consumption ADSP-21062L (3.3V)

These specifications apply only to the internal power supply portion of VDD. Calculations of external supply current and total supply current can be found in the power dissipation section of this data sheet. For a full discussion of the code used to measure power consumption, see the tech note "SHARC Power Consumption Measurements".

Timing Specifications

General Instructions

The ADSP-21062 will be available in two speed grades, 40MHz and 33.3MHz. Specifications shown are based on a CLKIN frequency of 40 MHz (tCK=25 ns). DT derating allows specification at other CLKIN frequencies (within the min-max range of the tCK specification; see Clock Inputs below). DT is the difference between the actual CLKIN period and the 25 ns CLKIN period:

Use the given precise timing information. Don't try to get arguments from other addition and subtraction operations. While addition or subtraction will yield meaningful results for a single device, the values given in this data sheet reflect statistical variation and worst-case scenarios. Therefore, parameters cannot be meaningfully added to get longer. See Figure 27 under test conditions for voltage reference levels.

Switch characteristics specify how the processor changes its signals. Timing circuits outside of the processor that you cannot control must be designed to be compatible with these signal characteristics. Switch characteristics tell you what the processor will do in a given situation. You can also use the toggle feature to ensure that any timing requirements of devices attached to the processor, such as memory, are met.

Timing requirements apply to signals controlled by circuits external to the processor, such as data inputs for read operations. Timing requirements ensure that the processor works properly with other devices.

(O/D) = open ditch

(A/D) = Active Drive

Memory read bus master

Use these specifications for asynchronous interfaces to memo (and memory mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing the external memory space. These switching characteristics also apply to bus master synchronous read/write timing (see Synchronized Read/Write - Bus Master below). Synchronous read/write times can be ignored if these timing requirements are met (and vice versa).

W = (number of wait states specified in the wait register) × tCK.

HI=tCK (if an address hold cycle or bus idle cycle occurs, as specified in the wait register; otherwise HI=0).

H=tCK (H=0 if the address hold period is specified in the wait register).

Notes: 1. Data Delay/Setup: User must meet tDAD or tDRLD or synchronization specification tSSDATI. 2. Data retention: the user must meet tHDA or tHDRH or synchronization specification tHSDATI. For holdup time calculations, see System Holdup Time Calculations under Test Conditions for a Given Capacitive and DC Load. 3. ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronization specification tSACKC for ACK release (low), ACK for acknowledgment (high) must meet all three specifications. 4. Refer to the falling edge of MSx, SW, and BMS.

memory write bus master

Use these specifications to asynchronously connect to memory (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21062 is the bus master accessing the external memory space. These switching characteristics also apply to bus master synchronous read/write timing (see Synchronized Read/Write - Bus Master). Synchronous read/write timing can be ignored if these timing requirements are met (and vice versa).

W = (number of wait states specified in the wait register) × tCK.

H=tCK (if an address hold cycle occurs, as specified in the wait register; otherwise H=0). I=tCK (if a bus idle cycle occurs, as specified in the wait register; otherwise I=0).

Notes: 1. ACK Delay/Setup: User must satisfy ACK deassertion (low) for tDAAK or tDSAK or synchronization specification tSACKC, all three specifications must satisfy ACK assertion (high). 2. Refer to the falling edge of MSx, SW, and BMS. 3. For hold-up time calculations for a given capacitance and DC load, see System hold-up time calculations under test conditions.

Synchronous read and write bus master

Use these specifications to connect to external memory systems that require CLKIN relative timing, or to access slave ADSP-21062 (in the multiprocessor memory space). These synchronous switching features are also valid during asynchronous memory reads and writes (see Memory Read Bus Mastering and Memory Write Bus Mastering).

When accessing the slave ADSP-21062, these switch characteristics must meet the timing requirements for slave synchronous read/write (see Synchronous Read/Write Bus Slave). The slave ADSP-21062 must also meet (bus master) timing requirements for data and acknowledge setup and hold times.

W = (number of wait states specified in the wait register) × tCK.

Notes: 1. Refer to the falling edge of MSx, SW, BMS. 2. ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronization specification tSACKC to de-assign ACK (low), assertion must meet all three specifications for acknowledgment (high). 3. For hold-up time calculations for a given capacitance and DC load, see System hold-up time calculations under test conditions.

Synchronous read and write bus slave

Use these specifications for ADSP-21062 bus master access to slave IOP registers or internal memory (in the multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.

Notes: 1. When the multiprocessor memory space wait state (MMSWS bit in the wait register) is disabled, tSRWLI(min)=9.5+5DT/16; when MMSWS is enabled, tSRWLI(min)=4+DT /8. 2. For the hold-up time calculation for a given capacitance and DC load, please refer to the system hold-up time calculation under test conditions. 3. tDACKAD is true only when the address and switch input setup time (before CLKIN) is greater than 10+DT/8 and less than 19+3DT/4. If the address and switch input have setup time greater than 19+3DT/4, ACK is valid 14+DT/4(max) after CLKIN. A slave that sees an address with a matching M field will respond with an ACK, regardless of the state of MMSWS or strobes. A slave will acknowledge the status three times per cycle with tACKTR.

Multiprocessor Bus Requests and Host Bus Requests

Use these specifications to pass bus mastership between multiprocessing ADSP-21062s (BRx) or host processors (HBR, HBG).

Notes: 1. For the first asynchronous access after HBR and CS are asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low, or tHBGRCSV low after HBG goes low. This is easily accomplished by driving a high address signal when the HBG is asserted. Please refer to the ADSP-21062 SHARC User Manual, Second Edition. 2. Identification is only required in the current cycle. 3. The CPA assertion must satisfy the CLKIN setting; the deassertion does not need to satisfy the CLKIN setting. 4. (O/D) = open drain, (A/D) = active drive.

Asynchronous read and write host to ADSP-21062

Use these specifications for asynchronous host processor access after the host asserts CS and HBR (low). After the ADSP-21062 returns to HBG, the host can drive the RD and WR pins to access the ADSP-21062's internal memory or IOP registers. HBR and HBG are assumed to be low at this timing.

Note: 1. Not required if RD and address are valid tHBGRCSV after HBG goes low. For the first access after asserting HBR, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR fall or tHBGRCSV fall after HBG fall. This is easily accomplished by driving a high address signal when the HBG is asserted. See the "Host Process or Control of the ADSP-21062" section in the ADSP-21062 SHARC User Manual, Second Edition.

Tri-state timing bus master, slave, HBR, SBTS

These specs show how to disable the memory interface (stop driving) or enable (keep driving) relative to the CLKIN and SBTS pins. This timing applies to the bus master transfer cycle (BTC) and master transfer cycle (HTC) and SBTS pins.

Notes: 1. Strobes=RD, WR, SW, page, DMAG. 2. These specifications apply to bus master/slave synchronous read/write in addition to bus master transition cycles. 3. Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, BMS (in EPROM boot mode).

DMA handshake

These specifications describe three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For hand crank mode, the DMAG controls the locking of data or enables external. For external handshake mode, data transfer is controlled by ADDR31-0, RD, WR, SW, PAGE, MS3-0, ACK and DMAG signals. For Paced Master mode, data transfer is controlled by ADDR31-0, RD, WR, MS3-0 and ACK (not DMAG). For Paced Master Mode, Memory Read Bus Master, Memory Write - Bus Master and Synchronous Read/Write - Bus Master Timing Specifications for ADDR31-0, RD, WR, MS3-0, SW, PAGE, DATA47- 0 and ACK also apply.

W = (number of wait states specified in the wait register) × tCK.

HI=tCK (if an address hold cycle or bus idle cycle occurs, as specified in the wait register; otherwise HI=0).

Notes: 1. Identification is only required in the current cycle. 2. If DMARx is not used to delay write completion, then tSDATDGL is the data setup requirement. Otherwise, if DMARx low delays the write completion, tDATDRH can be driven by DMARx high. 3. tVDATDGH is valid if DMARx is not used to delay read completion. If DMARx is used to extend the read time, then tVDATDGH=8+9DT/16+(n×tCK), where n is equal to the number of extra cycles to extend the access. 4. For holdup time calculations for a given capacitance and DC load, see System Holdup Time Calculations under Test Conditions.

Link Port: 2 CLK Speed Operation

To determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK, the setup and hold of the link receiver data relative to the link clock needs to be calculated. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK (Setup skew=tLCLKTWH min–tDLDCH–tSLDCL). Hold skew is the maximum delay introduced in LCLK relative to LDATA (Hold skew=tLCLKTWL min–tHLDCH–tHLDCL). Calculations made directly from the 2x speed specification will result in unusually small twist times since they include multiple tester protection zones. The setup and hold tilt times shown below are calculated to include only one detector protector and .

ADSP-21062 Set Deviation = 1.84 ns max

ADSP-21062 hold tilt = 2.78 ns max

ADSP-21062L Set Deviation = 2.10 ns max

ADSP-21062L hold slope = 1.87 ns max

output drive current

Figure 28 shows the typical IV characteristics of the ADSP-21062 output driver. These curves represent the current drive capability of the output driver as a function of output voltage.

Power consumption

There are two parts to the total power dissipation, one is due to the internal circuitry and the other is due to the switching of the external output driver. Internal power consumption depends on the instruction execution sequence and the number of data operands involved. The internal power consumption is calculated as follows:

The external component of the total power dissipation is caused by toggling of the output pins. Its size depends on:

– Number of output pins (O) toggled in each loop

– Maximum frequency of switching (f)

– Load capacitance (C)

- Its voltage fluctuation (VDD) is calculated by the following formula:

The load capacitance should include the package capacitance (CIN) of the processor. The switching frequency consists of driving the load up and down again. Address and data pins can be driven high and low at a maximum rate of 1/(2tCK). The write strobe can toggle every cycle at a frequency of 1/tCK. The select pin switches at 1/(2tCK), but the select can be turned on every cycle.

Example: Estimate PEXT based on the following assumptions:

– a system with a set of external data memory RAM (32 bits);

– Using four 128K×8 RAM chips, each with a load of 10 pF;

– External data memory writes occur every other cycle at a rate of 1/(4tCK), 50% of the pins toggle;

– The instruction cycle rate is 40 MHz (tCK=25 ns).

The PEXT equation is calculated for each type of pin that can drive:

Typical power dissipation under these conditions can now be calculated by adding the typical internal power dissipation:

Note that the conditions that lead to a worst-case PEXT are not the same as the conditions that lead to a worst-case PINT. The maximum pin count cannot occur when 100% of the output pins switch from all 1s to all 0s. Also note that it is not uncommon for applications to switch 100% or even 50% of the output at the same time.

Test conditions

Output disable time

When output pins stop driving, go into a high impedance state, and begin to decay from the high or low voltage they output, they are considered disabled. The time for the voltage on the bus to decay ∏V depends on the capacitive load CL and the load current IL. This decay time can be approximated by the following equation:

As shown in Figure 25, the output disable time tDIS is the difference between tMEASURED and tDECAY. The measured time t is the time interval from when the reference signal switches to when the output voltage decays ∏V from the measured output high voltage or output low voltage. tDECAY is calculated with test loads CL and IL, and ∏V equals 0.5 V.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time, tENA, is the interval between the reference signal reaching a high or low voltage level and the output reaching the specified high or low trip point, as shown in the output enable/disable diagram (Figure 25). If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

System Hold Time Calculation Example

To determine the data output hold time in a particular system, first calculate tDECAY using the formula given above. For devices that require hold time, ∏V is chosen as the difference between the output voltage and input threshold of the ADSP-21062. A typical ∏V is 0.4 V. CL is the total bus capacitance (per data line) and IL is the total leakage or tri-state current (per data line). The hold time is tDECAY plus the minimum disable time (ie, tDATRWH for the write cycle).

capacitive load

Output delay and hold are based on standard capacitive loading: 50 pF on all pins (see Figure 26). For loads other than the 50 pF rating, the given delay and hold specifications should be derated by 1.5 ns/50 pF. Figures 29-30, 33-34 show the output rise time as a function of capacitance. Figures 31, 35 graphically show how output delay and hold vary with load capacitance. (Note that this graph or derating does not apply to output disable delay; see the previous section for output disable time under test conditions.) The graphs of Figures 29, 30, and 31 may not be linear outside the ranges shown.

environmental conditions

Thermal characteristics

The ADSP-21062 is available in 240-lead thermally enhanced MQFP and 225-lead plastic ball grid array packages. The top surface of the thermally enhanced MQFP contains a copper slug from which most of the heat of the die is dissipated. The warhead is flush with the top surface of the package. Note that the copper slug is internally connected to GND through the device substrate.

Both packages are specified for one case temperature (TCASE). To ensure that TCASE is not exceeded, a heat sink and/or airflow source can be used. The heat sink should be attached with thermal adhesive.

TCASE = case temperature (measured on top of package); PD = power dissipation (W) (this value depends on the specific application; partial discharge is calculated under "Power consumption").

θCA=value in the table below.

Dimensions

Dimensions are in inches and (mm).