The ICL7660S and ICL7660A super voltage converters are monolithic CMOS voltage conversion chips with significant performance advantages compared to other similar devices. They are a drop-in replacement for the industry's standard ICL7660 offering extended operating power supplies up to 12V with lower supply current. A frequency boost pin has been incorporated to allow the user to use smaller capacitors though. All improvements are highlighted in the "Electrical" key parameter is a guaranteed temperature range across the commercial and industrial sector. The ICL7660S and ICL7660A perform the conversion of the supply voltage input range from positive to negative from 1.5V to 12V, producing complementary output voltages of -1.5V to -12V. Only two non-critical external capacitors are required for priming pump and priming tank functions. The ICL7660S and ICL7660A can be connected to function as a voltage doubler and will generate up to 22.8V from a 12V input. Can also be used as a voltage doubler or divider. Each chip contains a series DC power regulator oscillator, voltage level shifter and quad output power MOS switches. The oscillator operates with an input supply voltage of 5.0V at no load. This frequency can be added by adding

The "OSC" terminal or the oscillator's external capacitor may be overdriven by the external clock. The "LV" termination can be tied to GND to bypass the internal series regulator for improved low voltage operation. At medium and high voltage (3.5V to 12V), the low voltage pin floats on the left to prevent device latch-up. In some applications, an external Schottky diode cover - required to ensure lock-free operation.

feature

Guaranteed minimum maximum supply current temperature range for all devices

Wide operating voltage range: 1.5V to 12V

100% tested at 3V

Boost Pin (Pin 1) for Higher Switching Frequency

Guaranteed minimum power efficiency of 96%

Improved minimum open circuit voltage conversion efficiency of 99%

Improved thyristor latch-up protection

Simply convert +5V logic supply to ±5V supply

Simple voltage multiplication VOUT = (-) nVIN

Ease of use; requires only two external non-critical passive components

Improved drop-in replacement for the industry standard ICL7660 and other second source devices

Lead-free available (RoHS compliant)

application

Simply convert +5V supply to ±5V supply

Voltage Multiplier VOUT=? nVIN

Data Acquisition Systems and Instrumentation

RS232 power supply

Power splitter, VOUT=VS

notes:

1. Add "-T*" suffix to tape and reel. See TB347 for reel specifications.

2. These Intersil lead-free plastic packaged products feature a special lead-free material set, molding compound/mold join material and 100% matte tinplate plus annealing (e3 termination treatment, RoHS compliant, with SnPb and lead-free soldering operations compatible). Intersil's lead-free products meet or exceed IPC/JEDEC J Standard-020 at lead-free peak reflow temperatures.

3. For Moisture Sensitivity (MSL), see the device information pages for the ICL7660S and ICL7660A. For more information on MSL, see Technical Brief TB363.

4. Lead-free PDIPs can only be used for through-hole wave solder processing. They are not suitable for reflow process applications.

Absolute Maximum Ratings Thermal Information

voltage. +13.0V

Low Voltage and OSC Input Voltage (Note 5)

V+<5.5V. -0.3V to V++0.3V

V+>5.5V. V+-5.5V to V++0.3V

Current into low voltage (Note 5)

V+>3.5V. 20 microamps

short output

V power supply ≤ 5.5V. continuously

operating conditions

temperature range

ICL7660SI, ICL7660AI. -40°C to +85°C

ICL7660SC, ICL7660AC. 0°C to +70°C

Thermal Resistance (Typical, Note 6, 7) θJA (°C/Watt) θJC (°C/Watt)

8 Ld PDIP*. 110 59

8 Ld Plastic SOIC. 160 48

Storage temperature range. -65°C to +150°C

Lead-free reflow profile. Lead-free PDIPs are available for through-hole wave solder processing only. They are not intended for reflow soldering applications.

NOTE: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to these conditions may affect product reliability and

cause malfunctions not covered by the warranty.

notes:

5. Connecting any terminal to a voltage greater than V+ or less than GND may cause destructive latch-up. It is not recommended that an external power supply should be used until the ICL7660S and ICL7660A are "powered up".

6. θJA is measured in free air with components mounted on an inefficient thermal conductivity test board. See Technical Bulletin TB379 for details.

7. For θJC, the "case temp" position is taken at the top center of the package.

8. Lead-free PDIPs can only be used for through-hole wave solder processing. They are not suitable for reflow process applications.

Electrical Specifications ICL7660S and ICL7660A, V+=5V, TA=+25°C, OSC=free running (see Figure 12, “ICL7660S Test Circuit” on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7, unless otherwise specified .

Electrical Specifications ICL7660S and ICL7660A, V+=5V, TA=+25°C, OSC=free running (see Figure 12, “ICL7660S Test Circuit” on page 7 and Figure 13 “ICL7660A Test Circuit” on page 7, unless otherwise specified .

notes:

9. Unless otherwise specified, parameters with minimum and/or maximum limits are 100% tested at +25°C. Temperature limits determined by characterization are also not production testing.

10. In the test circuit, pin 7 has no external capacitor. However, when the device is plugged into the test socket, there is usually a small but limited stray capacitance of about 5pF.

11. The Intersil ICL7660S and ICL7660A operate without external diodes over the entire temperature and voltage range. This device will work in existing designs, integrating an external diode with no degradation in overall circuit performance.

12. All significant improvements to the industry standard ICL7660 are highlighted.

13. Linearly derate 5.5 MW/°C above 50°C.

Note:

14. These curves include, in supply current, the current from V+ directly into the load RL (see Figure 12). Therefore, about half of the supply current flows directly to the positive side of the load, and the other half flows to the negative side through the ICL7660S and ICL7660A

loaded. Ideally, VOUT ~ 2VIN is ~2IL, so VIN x is ~VOUT x IL

NOTE: For large values of COSC (>1000pF), the values for C1 and C2 should be increased to 100µF.

NOTE: For large values of COSC (>1000pF), the values for C1 and C2 should be increased to 100µF.

Detailed description

The ICL7660S and ICL7660A contain all necessary to complete the circuit of the negative voltage converter with the exception of two external capacitors, possibly of the inexpensive 10µF polarized electrolytic type. The operation of the mode device is best understood by considering Figure 14, which shows an ideal negative voltage converter. Capacitor C1 charges to voltage V+ for half-cycle when switches S1 and S3 are closed. (Note: switches S2 and S4 are open during this half cycle). During the second half cycle of operation, switches S2 and S4 are closed and S1 and S3 are open, thus shifting capacitors C1 to C2 so that the voltage on C2 is exactly V+, assuming ideal switches and C2 unloaded. The ICL7660 The ICL7660A is closer to this ideal than the existing non-mechanical loop.

In the ICL7660S and ICL7660A, the four switches in Figure 14 are MOS power switches; S1 is a P-channel device; S2, S3, and S4 are N-channel devices. The main difficulty with this approach is that when integrating switches, the substrates of S3 and S4 must always remain reverse biased to their source, but not so low as to reduce their "on" resistance. In addition, under circuit startup and output short-circuit conditions (VOUT=V+), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to do so will result in high power losses and possible device latch-up. In the ICL7660S and ICL7660A, a logic network that senses the output voltage (VOUT) works with the level converter to switch the reverse bias necessary to keep the S3 and S4 substrates at the correct level. The ICL7660S and ICL7660A are part of a latch-up prevention circuit; however, their inherent voltage drop reduces the low voltage. Therefore, to improve low voltage operation, the "LV" pin should be tied to GND, thereby disabling the regulator. The terminals must remain open when the supply voltage is greater than 3.5V to ensure anti-latching operation to prevent equipment damage.

Theoretical power efficiency

Precautions

In theory, the efficiency of a voltage converter can be close to 100% if certain conditions are met:

1. The power consumed by the drive circuit is minimal.

2. The on-resistance of the output switch is extremely low with almost no compensation.

3. The impedance of the pump and reservoir capacitors is negligible at the pump frequency. The ICL7660S and ICL7660A are close to these conditions if large values of C1 and C2 are used. Energy is only a voltage appearing on the charge between the capacitors. The energy loss is defined as Equation 1:

where V1 and V2 are the voltage on C1 during pump operation and the transfer period. If the impedances of C1 and C2 are relatively high for the pump frequency (see Figure 14) compared to the value of RL, the voltage difference between V1 and V2. Therefore, it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to use a correspondingly large value of C1 for operation. do and don't do

1. Do not exceed the maximum supply voltage.

2. Do not ground the low voltage terminal to obtain a power supply voltage greater than 3.5V.

3. Do not short the output to voltages above 5.5V on the V+ supply for extended periods of time; however, transient conditions including start-up are fine.

4. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of ICL7660S and ICL7660A, and the + terminal of C2 must be connected to ground.

5. If the power supply driving the ICL7660S and ICL7660A has a large source impedance (25Ω to 30Ω), then a 2.2µF capacitor from pin 8 to ground may be required to limit the input voltage rise rate to less than 2V/µs.

6. If the input voltage is above 5V and has a rate of rise greater than 2V/µs, the external Schottky diode from VOUT has a lid on it - needed to prevent latch-up (by keeping the output (pin 5) more active than the lid (pin 4).

7. The user should ensure that the output (pin 5) does not run more actively than the GND (pin 3). Device lockout will occur under these conditions. For extra protection, a 1N914 or similar diode in parallel with C2 will prevent the device from pulling up the output voltage (anode pin 5, cathode pin 3) before the IC activates when loading on VOUT creates a path.

typical application

Simple Negative Voltage Converter Most applications will undoubtedly use the ICL7660S and ICL7660A voltages used to generate the negative supply. Figure 15 shows that a negative supply is provided, a positive supply from +1.5V to +12V is available. Remember that pin 6 (LV) is connected to the power supply and is negative (GND) when the supply voltage is lower than 3.5V.

The output characteristics of the circuit in Figure 15 can be

Use ideal voltage sources and resistors as shown in Figure 15B. Voltage Source Value - (V+). The output impedance (RO) is the on-resistance of the internal MOS switch (see Figure 14), the switching frequency, the values of C1 and C2, and the ESR (equivalent series resistance) of C1 and C2. A good first-order approximation of RO is given by Equation 2:

The total switch resistance, RSW, is a function of supply voltage and temperature (see Figure 2, Figure 3, and Figure 11 for output source resistance), and is typically 23Ω at +25°C and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. A high value capacitor will reduce the 1/(fPUMP x C1) component, and an ESR capacitor will reduce the ESR term. Increasing the oscillator frequency will reduce the 1/(fPUMP x C1) term, but may have the side effect of a net increase in output when C1 > 10µF and not enough to fully charge the capacitor each cycle. Equation 4 shows a typical application at fOSC=10kHz, C=C1=C2=10µF:

Because the capacitor's ESRs are reflected in the output impedance multiplied by 5, high values can potentially overwhelm the low 1/fPUMP x C1 term, rendering switching frequency or filter capacitance increases ineffective. Typical electrolytic capacitors may have up to 10Ω. The output ripple ESR also affects the ripple voltage at the output. This peak-to-peak output ripple voltage is given by Equation 5:

Replacing the ICL7660S and ICL7660A Oscillator Frequency In some applications, it may be advisable to change the oscillator frequency due to noise or other reasons. This may simply be accomplished in one of several ways. By connecting the boost pin (pin 1) to V+, the oscillator charge and discharge currents increase, and thus the oscillator frequency increases by a factor of about 3.5. The result is a reduction in output impedance and ripple. This is important for surface mount applications where capacitor size and cost are critical. Smaller capacitors, such as 0.1µF, can be free-run at C1 = C2 = 10µF or 100µF with Boost Pin devices that achieve similar output currents (see Figure 11). Increasing the oscillator frequency can also be done by overdriving the oscillator from an external clock, as shown in Figure 16. To prevent device latch-up, a 1kΩ resistor must be used in series with the clock output. In some cases where the designer is generating the external clock frequency using TTL logic, adding a 10kΩ pull-up requires a resistor to the V+ supply. Note that the pump external clock frequency, like the internal clock frequency, will be half the clock frequency. Output transitions occur on the positive edge of the clock.

It can also be increased by reducing the oscillator frequency. This reduces switching losses and is shown in Figure 17. However, lowering the oscillator frequency will result in the impedance of the pump (C1) and reservoir (C2) capacitors; by increasing the values of C1 and C2 by the same factor that reduces the frequency. For example, adding a 100pF capacitor between pins 7 (OSC and V+) will reduce the oscillator frequency to 1kHz from the nominal frequency of 10kHz (multiples of 10), and thus requires a corresponding increase in C1 and C2 (from 10µF to 100μF).

Positive voltage multiplication

The ICL7660S and ICL7660A can be used to achieve positive voltage multiplication using the circuit shown in the figure. 18 In this application, the pump inverter switches ICL7660S and ICL7660A are used to charge C1 to the voltage V+-VF level, where V+ is the supply voltage, VF is the forward voltage on C1 plus the supply voltage (V+) applied to capacitor C2 through diode D2. So the voltage across C2 becomes (2V+)-(2VF) or twice the voltage of the power supply minus the combined forward voltage drop of the diodes D1 and D2. The source impedance of the output (VOUT) depends on the output current, but is about 60Ω for V+=5V and an output current of 10mA

Combining Negative Voltage Transition and Positive Supply Multiplication Figure 19 combines Figures 15 and 18 to provide negative voltage transition and positive voltage doubling simultaneously. This method, for example, is suitable for generating +9V and -5V from an existing +5V supply. In this case, capacitors C1C3 perform pump and reservoir functions, respectively, for generating negative voltages, while capacitors C2 and C4 are pump and reservoir, respectively, for double the positive voltage. There is a penalty here however, the source impedance of the resulting power supply is a bit high because of the common charge pump driver at pin 2 of the device.

partial pressure

The bidirectional feature can also be used to split halves into high supplies, as shown in Figure 20. The combined load will be evenly distributed on both sides and the resistor value of the low voltage pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in standard circuits, and more current can be drawn from the device. Using this circuit, then Figure 15, the +15V circuit can pass +7.5 and -7.5, with a rated voltage of -15V, despite the series higher output resistance (~250Ω). and -7.5, rated voltage -15V, despite the series higher output resistance (~250Ω).

Power Supply

The ICL7660S and ICL7660A can be a problem in some cases, especially when the load current varies widely. The circuit of Figure 21 can be used to maintain a nearly constant output voltage with the ICL7611 low power CMOS op amp by controlling the input voltage. Direct feedback is not desirable because the outputs of the ICL7660 and ICL7660A do not respond immediately to changes in the input, but only after a switching delay. The circuit shown supplies enough delay to accommodate the ICL7660S and ICL7660A, while maintaining sufficient feedback. An additional pump and storage capacitor is advisable, and the values shown provide an output impedance of less than 5Ω to a 10mA load.