With the continuous development of aerospace technology, the requirements for control are getting higher and higher, and higher response speed and stronger data processing capability are required. In the aerospace field, once the control is wrong, it will cause inestimable losses. Therefore, how to improve the reliability of control has been an important issue for a long time. This paper introduces a practical development scheme of SOC application mode, and focuses on the design and realization of the high reliability of the platform computer.

Main tasks of high reliability platform computer

The high reliability platform computer mainly completes the following main tasks: real-time recording of the rotational angle increment and apparent velocity increment output by the inertial measurement instrument; receiving the initial position, velocity and attitude data given by the on-board navigation system; real-time receiving the positioning satellite measurement data ;Complete the calculation of guidance and attitude control equations in real time, transform and synthesize the collected information according to the requirements of the control law and guidance law, form control/guidance instructions, and control the steering gear; integrate the 1553B bus communication function for bus communication and control; 4-way D/A outputs attitude control commands; has 8 levels of maskable interrupts; communicates with the ground computer through the 1553B interface for information exchange; provides three RS422 interfaces with photoelectric isolation.

The platform computer adopts the scheme of FPGA+S698IP core (abbreviated as SOC), takes the S698IP core of Obit as the main CPU, and integrates 1553B bus controller, VME bus controller, and 3 UARTs with FIFO. It reflects the flexibility and superior performance of the S698IP core of Orbit. And supports multiple operating systems. The use of SOC design saves expensive tape-out costs, increases the flexibility of system design, facilitates modification, and greatly shortens the design and development cycle.

High reliability platform computer

The functional block diagram of the high-reliability platform computer is shown in Figure 1.

Design of Platform Computer Using EP1C20 Chip and S698IP Core

Figure 1 High-reliability platform computer functional block diagram

The high-reliability platform computer is realized in the form of SOC of FPGA+S698IP core, and the FPGA adopts Cyclone series EP1C20 of ALTERA Company.

The high-performance S698IP core, as the core, integrates a large number of peripheral devices, and integrates all these modules into one FPGA device, which reduces the cost of the entire board-level system and reduces the size of the board-level system. above-grade devices, greatly improving the reliability of the system.

The functional block diagram of the S698IP core is shown in Figure 2.

Design of Platform Computer Using EP1C20 Chip and S698IP Core

Figure 2 S698IP core functional block diagram

The features of the S698IP core are as follows: Internal use of 5-stage pipeline, SPARCV8 instruction set; hardware multiplier and divider; support for 2 DSP instructions (MAC & UMAC); floating point operation: double precision (64-bit); with separate instruction and data cache Structure (Harvard structure), the capacity of the cache can be flexibly configured according to the needs, the size range is 1-64kbyte; the on-chip bus specification uses the AMBA2.0 specification, supports APB, and AHB standards; peripherals can be cut, including UART, timer , interrupt controller, memory management unit, I/O port, watchdog, etc.; user-designed new modules using AMBAAHB/APB bus structure can be easily added to the S698IP core to complete user-customized applications; integrated debugging support unit (DSU), supports hardware debugging function.

The high-reliability platform computer system board has the following hardware resources: FPGA (integrated S698, 1553B, VMEIP core); 1553B part; VME part; 4MBFLASH; 4MBSRAM; , of which 2 channels have 16-byte FIFO, 1 channel 1K byte FIFO; frequency standard frequency can be configured; timer; 8-level interrupt; FPGA provides JTAG, AS interface; 1 channel UART; DSU (hardware debugging unit).

High reliability design of S698IP core

In order to be suitable for high-reliability applications in aerospace, the S698IP core adopts a multi-level fault tolerance strategy; parity check, TMR (Tri-modular Redundancy) register, on-chip EDAC (error detection and correction), pipeline restart, forced Cache miss Wait. Although almost all CPUs now have some conventional fault tolerance measures, such as parity check, pipeline restart, etc., IBMS/390G5 also adopts the entire pipeline replication technology before the write stage. IntelItanium adopts technologies such as hybrid ECC and parity coding; however, it is far from adopting such comprehensive fault tolerance measures as the S698IP core.

The S698IP core takes the state reversal of the sequential (storage) unit as the main content of digital fault tolerance, and adopts different fault tolerance techniques and means according to the different characteristics and properties of sequential logic.

1) Cache fault tolerance. A large cache is critical for high-performance CPUs and is located on the critical (time) path of the processor. In order to reduce the complexity and time overhead, the error detection method adopts 2-bit parity check bit, 1 bit is used for odd check, and 1 bit is even check, so all error conditions can be checked, and the check is performed while reading the Cache. . When an error is found in the verification, the cache is forced to be lost, and the data is retrieved from the external storage.

2) Error protection of the processor register file. The register file is the internal register file of the processor, and the internal registers are very important for the running speed of the instruction and the flexibility of the user program design. The frequency of use of internal registers is very high, and the correctness of their states is also critical. The S698IP core uses 1, 2 parity bits and (32.7) BCH checksum for fault tolerance.

3) Error protection of flip-flops. The 2500 flip-flops of the processor are all fault-tolerant in the way of three-mode redundancy, and the correct output is determined by the voter.

Hardware high reliability design

3 RS422 interfaces and 1553B interfaces are the external interfaces of the system. RS422 adopts photoelectric isolation, and uses light as a medium to transmit information during operation. It has no contact, long life and fast response speed. The input and output are completely isolated electrically. A high-grade isolated power supply is used to supply power to the optocoupler alone, with strong anti-interference ability.

1553B is a determinable and reliable data bus, designed for dual redundancy, widely used in different military platforms (aviation systems, ground vehicle systems, ship systems) systems, and has developed into an internationally recognized data bus. bus standard.

The backplane data bus is VME (VersaModuleEurocard). VME bus is a general computer bus that defines a system that can interconnect data processing, data storage and connect peripheral control devices in a tightly coupled (closely coupled) hardware architecture. After years of transformation and upgrading, the VME system has developed very well, and the products developed around it have covered the fields of industrial control, military systems, aerospace, transportation and medical care.

Overall reliability design

The most prominent feature of SPARC microprocessor is its expansibility. This is the first microprocessor with expansibility function in the industry. Its infinite expansibility can cope with various data processing requirements. It has high structural design, fault tolerance and program protection design. Because of its unique performance, it has been favored in the aerospace field. Due to the SOC method, the internal integration is high and the external expansion work is small, which itself has strong anti-interference ability; at the same time, through the anti-interference design of external hardware circuits and software, the platform computer can achieve very high reliability.

RS422

The 3 UART controllers are implemented in the SOC, and the LVTTL level is converted to the RS422 level through the RS422 transceiver chip, of which 1 channel of RS422 has receive/transmit interrupts.

UART1 has a FIFO of 16 bytes, which can generate interrupts. After fetching, the interrupts are cleared, and the FIFO is emptied at the same time. UART2 has a FIFO of 1Kbyte, which is managed by an independent manager when data is sent, and does not occupy CPU time. UART3 has a 16byte FIFO and can generate interrupts.

Using RS422 bus interface, the maximum transmission distance: 1000m. In order to improve the anti-interference ability and high EMI protection performance, the optoelectronic isolation method is adopted, which improves the stability and security of the node.

Frequency marker and 5ms interrupt

The frequency marker and 5ms interrupt function are implemented in the SOC. The default frequency of the frequency marker is 1ms, compatible with TTL level, and 50% duty cycle. In the SOC, frequency scales with different frequencies can be output by configuring different values, and its startup and shutdown can be controlled by software operating the corresponding registers.

The 5ms timer module is used to generate periodic interrupt requests, the default period is 5ms, and its startup and shutdown can be controlled by software operating the corresponding registers.

Part 1553B

The 1553B bus is integrated with the S698IP core and implemented in the SOC. The transmission speed is 1M bits per second, the word length is 20 bits, the effective data length is 16 bits, the maximum length of information is 32 words, the transmission mode is half-duplex, the transmission protocol is command/response mode, failure Fault tolerance has a typical dual redundancy mode, and the second bus is in a hot backup state; 3 different terminals can be realized through software configuration, including bus controller (BC), remote terminal (RT) and bus monitor (BM) ; Information formats include BC to RT, RT to BC, RT to RT, broadcast mode and system control mode; 31 remote terminals can be connected, the transmission medium is shielded twisted pair, and the bus coupling mode adopts direct coupling mode. The platform computer realizes the complete communication of 1553B bus, which includes BC, RT, BM, and its function, communication and operation mode are basically the same as BU-6158X chip. A dedicated chip DDC61580 that can realize 1553B function is expensive and fully dependent on imports. Products that fully rely on imports are not suitable for use in special fields, and we have realized the same function of DDC61580 in a cost-effective FPGA.

There are two host interfaces of the 1553B bus controller: APB and AHB. The host (ie SPARCV8 processor) accesses registers through the APB interface (including the input bus APBI and output bus APBO), and accesses the memory through the AHB interface (including the input bus AHBI and the output bus AHBO). The output/input of ManchesterCODEC is a complementary Manchester code with a code rate of 1Mbps. The signals RXA, RXAN, TXA, TXAN, TXAEN, RXB, RXBN, TXB, TXBN and TXBEN are the interface signals between the 1553B bus controller and the external transceiver chip.

This computer platform can realize the functions of BC, RT and BM respectively by configuring the 1553B controller registers. It can be flexibly applied in different occasions.

VME section

VME bus is a commonly used computer interface bus with mature technology. At present, a large part of the onboard computer parallel bus at home and abroad adopts the VME bus structure. The VME bus is a high-speed, asynchronous parallel data transmission bus that supports 8-bit, 16-bit and 32-bit transmission on non-multiplexed, 32-bit data and address paths. The communication protocol is asynchronous and fully hooked. . It includes functional modules: master module, slave module, interrupt module and interrupt management module, and there are two other modules: bus timing module and IACK daisy chain drive module to assist each of the above functional modules.

The VME bus controller of the platform computer implements the standard VME bus in the SOC. After the VME bus signal comes out of the SOC, it is output to the backplane connector through the bus drive circuit. The bus chip adopts 74ALVC164245 to realize 3.3V~5V level conversion. The VME interface and backplane connector have 96 pins arranged in three rows of 32 pins each. The VME controller is attached to the external storage controller bus of the processor, the mapped area is the I/O area, and the address area allocated to it is: 0x24000000~0x24FFFFFF, a total of 16M space.

D/A conversion module

The D/A conversion module consists of the following three parts: D/A conversion chip, reference, and operational amplifier. 12-bit D/A conversion accuracy, can output 4 channels of +10V～-10V voltage

software programming

The S698IP core can support ucLinux, RTEMS, Vxworks and other operating systems; it can also support standard C programming without an operating system. And developed a graphical integrated development environment under Linux and Windows to support popular debugging methods; the development environment supports offline simulation debugging and target board online debugging.

Epilogue

This highly reliable platform computer no longer uses bulky, bulky and huge power consumption processor chips (such as DSP), but directly puts the S698IP core into the FPGA. At the same time, a variety of design measures to improve system reliability are adopted in hardware, software and board wiring. Most of the processing functions are hardwareized in the system, and the entire system is put into an FPGA chip by utilizing the abundant resources of FPAG. Among them, the S698IP core performs control management and some necessary calculation processing. Such a domestically produced high-performance processor has independent intellectual property rights and is used in some special fields, which is particularly important for national security. The performance of the S698IP core is not inferior to other similar processors, and the rich peripherals have built a chip-level high-reliability computer platform for users, which is extremely convenient to use.