The ISL6530 is a dual DC-DC converter DDRAM memory application optimized for high performance. It is designed to reduce vehicle speed in a topology DDRAM memory where the N-channel mosfet in the synchronous rectification buck efficiently generates 2.5V VDDQ, VREF for DDRAM differential signaling, and VTT for signal termination. The ISL6530 integrates control, output regulation, monitoring and protection functions into a single package. The converter's VDDQ output is held at 2.5V by an integrated precision voltage reference. The VREF output is precisely regulated to 1/2 the stored power supply with a maximum temperature tolerance of ±1% and line voltage variation. VTT precisely tracks VREF. In V2_SD sleep mode, the VTT output is controlled by the low power window regulator. The ISL6530 provides simple, single feedback loop, voltage mode control and fast transient response. It includes two phase-locked 300kHz triangle wave oscillators replacing 90 degrees to minimize interference between the two PWM regulators. The regulator features an error amplifier with a 15MHz gain-bandwidth product and a 6V/µs slew rate to enable high converter bandwidth performance for fast transients. The resulting PWM duty cycle ranges from 0% to 100%. The ISL6530 operates by inhibiting pulse width modulation. The ISL6530 monitors the current in the VDDQ regulator, using the upper rDS(ON) MOSFET resistor without the need for current sensing.

feature

Provides VDDQ, VREF, and VTT voltages for single- and dual-channel DDRAM memory systems

Excellent voltage regulation-VDDQ=2.5V±2% full scale-VREF=(VDDQ÷2)±1% over full operating range-VTT=VREF±30mV

Supports "S3" sleep mode - VTT is kept at VDDQ÷2 by low power window regulator to minimize wake-up time

Fast Transient Response - Full 0% to 100% Duty Cycle

Operation from +5V input

Overcurrent fault monitor on VDD - no additional current sensing element required - rDS(ON) using MOSFET

Driving cheap N-channel mosfets

Small converter size - 300kHz fixed frequency oscillator

24 leads, SOIC or 32 leads, 5mm×5mm QFN

Lead-free available (RoHS compliant)

application

VDDQ, VTT, and VREF Regulation System for DDRAM Memory - AMD® Athlon's Main Memory 8482 ; and K8™, Pentium III, Pentium IV, Transmeta, PowerPC™, Alpha PC™, and UltraSparc®-Based Computer Systems - in Graphics Systems Video Memory High Power Tracking DC-DC Regulator

Absolute Maximum Ratings Thermal Information

Supply voltage, VCC. +7.0V

Start-up voltage, VBOOTn-VPHASEn. +7.0V

Input, output or I/O voltage. Ground -0.3V to VCC+0.3V

Electrostatic discharge classification. level 2

operating conditions

Supply voltage, VCC. +5V±10%

Ambient temperature range. 0oC to 70oC

junction temperature range. 0oC to 125oC

Thermal resistance θJA (oC/W) θJC (oC/W)

SOIC package (Note 1). 65 knives

QFN package (Note 2). 33 4

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (10s for soldering). 300 degrees Celsius

(SOIC - lead only)

See Technical Brief TB389 for recommended soldering conditions.

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

2. θJA is measured in free air with the part mounted on a high-efficiency thermal conductivity test board with "direct-attach" characteristics. θJC "case temperature" is measured at the center of the exposed metal pad on the bottom of the package.

Operating conditions recommended by the electrical specification, Vcc=5V, unless otherwise stated

These pins, BOOT1 and BOOT2, provide bias for the upper MOSFET. A single capacitor bootstrap circuit can be used to create a bootstrap voltage suitable for driving standard N-channel MOSFETs. UGATE1 and UGATE2 connect UGATE1 and UGATE2 to the corresponding upper MOSFET gates. These pins are for upper MOSFETs. UGATE2 is also protected by adaptive breakdown to determine that the upper FET VTT regulator is turned off. LGATE1 and LGATE2 connect LGATE1 and LGATE2 to the corresponding lower MOSFET gates. These pins are low mosfets. These pins are protected by adaptive breakdown to determine when they have been turned off. PGND1 and PGND2 These are the power ground connections for the gate driver to control the pulse width modulation. Tie these pins to the ground plane through the lowest impedance connection available. Caten/SD A resistor (ROCSET) from this pin is connected to the upper MOSFET of the VDDQ regulator to set the overcurrent trip point. ROCSET, internal 40µA current source (IOCS) and upper MOSFET on-resistance (rDS(ON)) set the VDDQ converter overcurrent (OC) trip point according to the following formula:

Overcurrent trip cycle soft-start function. Pulling the OCSET/SD pin to ground resets the ISL6530 and all external mosfets off, allowing both output voltage supply rails to float. A high level on this open-drain output of Progood indicates that the VDDQ and VTT regulators are within the normal operating voltage range. GNDA is the signal ground of the company's IC. Tie this pin to the ground plane through the lowest impedance connection available. The 5V bias supply for the VCC company chip is connected to this pin. This pin is also the positive supply for the lower gate driver, LGATE2. Connect a well decoupled 5V supply to this pin. A high level on the secondary standard deviation V2-SD input puts the V2 controller into "sleep" mode. In sleep mode, UGATE2 and LGATE2 are driven low, effectively floating the VTT supply. When the VTT supply is "floating", it is held at VDDQ via the sensor 2 pin through the low current glass lifter driving the VTT. The glass regulator can overcome a leakage of at least ±10mA on the VTT. When V2_SD is high, PGOOD is low. Phase 1 and Phase 2 connect Phase 1 and Phase 2 to the corresponding upper MOSFET sources. This pin is used as part of the upper part of the MOSFET bootstrap driver. Phase 1 is used to monitor the voltage drop overcurrent protection regulator of the MOSFET on VDDQ. The Phase 1 pin is monitored by the adaptive shoot-through protection circuit to determine that the upper FET of the VDDQ supply is turned off. FB1, COMP1, FB2 and COMP2 COMP1, COMP2, FB1 and FB2 are the pins for the available external error amplifier. The FB1 and FB2 pins are the inverted inputs of each error amplifier and COMP1 and the COMP2 pin is the associated output. A suitable AC network across these pins is used for compensation

Voltage control feedback loop for each converter. The voltage produced by VREF and VREF_INVREF is equal to sense 1. This low current output is connected to the input of the DDRAM device that VREF is powering up. The same voltage is used as the reference input amplifier for the VTT error. Therefore VTT is controlled at 50% of VDDQ. VREF_-IN is used as an option to speed up the internal resistor divider network used to set the output voltage and the reference voltage for the VTT supply. A 100pF capacitor between VREFúIN and ground is recommended for proper operation

PVCC1 type

This is the positive supply for the lower gate driver LGATE1. Connect PVCC1 to a well decoupled 5V. Sensor 1 and Sensor 2 Both SENSE1 and SENSE2 are connected directly to the regulated outputs of the VDDQ and VTT supplies, respectively. SENSE1 is used as a reference voltage supply to create the VREF_ output voltage and VTT. Sensor 2 acts as a window regulator enabled in V2-SD mode.

Function description

Overview

The ISL6530 contains two control and drive circuits synchronous step-down PWM voltage regulators. The two regulators utilize a 5V bootstrap output topology, allowing the use of low-cost N-channel MOSFETs. The regulator is clocked by 300kHz. The clocks are phase locked and shifted 90 degrees to minimize noise coupling between controllers. The first regulator includes a reference voltage with an accuracy of 0.8V and is designed to provide a proper VDDQ system for DDRAM memory. The VDDQ controller implements overcurrent protection using the rDS(ON) of the upper MOSFET. After a fault, the VDDQ regulator is soft-started through a digital soft-start circuit. An accurate VREF reference output is included in the ISL6530. VREF is a buffered representation of .5xVDDQ. VREF is exported to the SENSE1 terminal through a precision internal resistor divider connected. The second PWM regulator is designed to provide termination for the VTTDDRAM signal lines. The VTT regulator is referred to as VREF. Therefore, the VTT regulator provides a termination voltage equal to .5xVDDQ. The MOSFET of the upper drain VTT power supply is connected to the VDDQ voltage. The VTT controller is designed to sink and source current on the VTT rail. The ISL6530 dual controller brings two benefits to the topology. First, since VREF is always .5xVDDQ, the VTT supply will track the VDDQ supply during the soft-start cycle. Second, the overcurrent protection in the VDDQ supply protects the VTT supply at the same time. Initialize the ISL6530 while applying input power. A special order of input power is necessary. A power-on reset (POR) function continuously monitors the input bias supply voltage at the VCC pin. This POR function initiates soft-start operation after a 5V bias supply voltage exceeds its POR threshold.

soft start

The POR function initiates a digital soft-start sequence. The pulse width modulated error amplifier reference input of this VDDQ regulator is clamped to a level proportional to the soft-start voltage. As the soft-start voltage rises, the PWM comparator produces an increased width phase pulse capacitor that charges the output. This method provides a fast and controllable output voltage rise. The soft-start sequence typically takes about 7 ms. The hold VTT regulator reference automatically tracks the ramp of the VDDQ soft-start, thus enabling soft-start for VTT. Figure 2 shows the soft-start sequence for a typical application. At t0, the +5V VCC bias voltage begins to rise. Once the voltage on VCC exceeds the POR threshold at time t1, both outputs begin their soft-start sequence. A triangular wave from the PWM oscillator is compared to the rising error amplifier output voltage. As the error amplification voltage increases, the pulse width on the molar pin increases to reach its steady state duty cycle at time t2.

Penetration Protection When both upper and lower MOSFETs turn on simultaneously, effectively shorting the input voltage to ground. To protect the regulator from shoot-through states, the ISL6530 contains specialized circuitry to ensure that complementary MOSFETs are not turned on at the same time. The adaptive shoot-through protection regulator employed by VDDQ looks at the lower gate drive pin LGATE1 and the phase node, Phase 1, to determine if the MOSFET is on or off. If Phase 1 is below 0.8V, the upper gate is defined as off. Likewise, if LGATE1 is below 0.8V, the lower MOSFET is defined as off. This method of shoot-through protection allows the VDDQ regulator to source current only. Due to the necessity of sinking current, the VTT regulator uses an improved protection scheme, the VDDQ regulator. If the voltage from UGATE2 or LGATE2 to GND is less than 0.8V, then the MOSFET is defined as OFF and the other MOSFET is ON. Because the lower MOSFET gate and higher MOSFET gate voltages are measured at the MOSFET gate of the VT power supply to determine the state of the MOSFET, designers are encouraged to consider the introduction of gate drivers and external components between them for practical implementation these measures before the respective MOSFET gates. Doing so may interfere with firing through protection.

Power down mode

DDRAM systems include a sleep state in which the voltage to the VDDQ memory remains unchanged, but the signal is suspended. In this mode, the VTT termination voltage is no longer required. The only loads on the VTT bus are the DDRAM and memory controller ICs. The VTT regulator is in a "sleep" state when the V2_SD input of the ISL6530 is driven high. In sleep states that the main VTT regulator is disabled, while the upper and lower mosfets are turned off. The VTT bus is kept close to .5xVdd through a low current window to drive the VTT regulator through the sensor 2 pin. Keeping VTT at .5xVDDQ consumes negligible power and requires a soft-start VTT regulator when not in use. During this power down mode, PGOOD remains low. OUTPUT VOLTAGE SELECTION The output voltage of the VDDQ regulator can be programmed as VIN (ie +5V) and the internal reference, 0.8V. The output voltage is adjusted relative to the reference voltage using an external resistor divider and fed back to the inverting input of the error amplifier, see Figure 3. However, as the value of R1 affects the value of other compensation components it is recommended to keep its value below 5kΩ. R4 can be calculated according to the following formula:

If the desired output voltage is 0.8V, just route VOUT1 back to the FB pin through R1, but don't fill R4.

The VTT reference overdrive ISL6530 allows the designer to bypass the internal 50% tracking of VDDQ as the VTT reference. The ISL6530 is designed to divide the VDDQ voltage by 50% through two internal termination resistors. These resistors are typically 200kΩ. One that can be used to bypass the internal VTT reference generation is to provide an external reference directly connected to the VREF_IN pin. When doing this, the Sensor 1 pin must be left unconnected. When the VTT regulator does not use its own soft-start. The second method is to speed up the internal resistors. Figure 4 shows how to implement this method. This external resistor for the overdrive internal resistor should be less than 2kΩ with a tolerance of 1% or better. This method remains on the resistor network and any loads on the VREF pin. No need to load the VREF pin if any, no buffering and the reference voltage generated by the resistor network can be tied directly to VREF

Inverter stops

Pulling the OCSET/SD pin below 0.8V turns off both regulators. In this state, PGOOD will keep a low profile. After releasing the OCSET/SD pin, the IC enters a soft-start cycle that brings both outputs back into regulation. Voltage Monitoring The ISL6530 provides a PGOOD signal that communicates whether the regulation of VDDQ and VTT is within ±15% of regulation, the V2_SD pin is held low, and the voltage of the bias IC is above the POR level. If all criteria above are true, the PGOOD pin will be at a high impedance level. If one or more of the criteria listed above are false, the PGOOD pin will remain low. Over-Current Protection The over-current function prevents the converter from short-circuiting VDDQ using the upper MOSFET on-resistance rDS(on) output to monitor the current. This approach enhances the efficiency of the inverter and reduces the cost of current sense resistors. Over-current function Cyclic soft-start function provides fault-protected hiccup mode. A resistor (ROCSET) programs the overcurrent trip level (see Figure 1). The internal 40µA (typ) current sink produces a voltage on the ROCSET referring to the VIN. When the voltage across the upper VDDQ MOSFET (also referred to as VIN) exceeds the voltage across ROCSET, the overcurrent function initiates a soft-start sequence. Figure 5 illustrates the response to an overcurrent event on VDDQ. At time T0, the overcurrent is sensed to the state regulator through the upper MOSFET of VDDQ. Therefore, both regulators quickly turn off the internal soft-start function and begin to generate a soft-start ramp. The delay interval seen by the output is equivalent to three soft-start cycles. The fourth internal soft-start cycle is at time T1. Both outputs pass time t2 as long as the overcurrent event has cleared. If the cause of the overcurrent is in the delay interval, the overcurrent condition will be detected by both regulators due to another delay interval of three soft-start cycles. As a result the hiccup protection method will continue to repeat indefinitely

current sink

The ISL6530 VTT regulator uses a MOSFET shoot-through protection method that allows the converter to sink and source current. Caution should be exercised when designing converters using the ISL6530 as it is known that the converter may draw current. When the converter sinks current, it behaves as a boost converter regulating the input voltage. This means that the converter is injecting the current regulator rail into the input. If this current has nowhere to go, such as on a rail or through a voltage limiting protection device, a capacitor on that rail will sink current. This condition will allow the voltage to increase the height of the input rail. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of any components connected to the input rail, then those components may fail irreversibly or experience stress that may shorten their life. Making sure the addition of the capacitors on the rails will prevent this failure mode. To ensure that the current does not increase the voltage of the input rail VTT regulator, it is recommended that the input rail of the VTT regulator be the output regulator of VDDQ. The current generated by the voltage transformer regulator will go into the VDDQ rail, then into the DDR SDRAM memory module and back to the VTT regulator. Figure 6 shows the recommended configuration and generating current loop

Application Guide

Layout Considerations

Layout is very important in high frequency switching converter design. Powering devices at 300kHz, the resulting current transitions from one device to another are due to voltage spike impedances and parasitic circuit elements on the interconnects. These voltage spikes reduce efficiency, radiate noise into the circuit, and cause device overvoltage stress. Careful component layout and printed circuit board design minimize voltage spikes in the converter. For example, consider a PWM turn-off switching MOSFET. The MOSFET will carry current before turning off. During the off period, current stops at and is received by the lower MOSFET. Parasitic inductance in any switching current path produces larger voltage spikes during switching intervals. Careful component selection, tight placement of critical components, and short, wide traces minimize the magnitude of voltage nails. There are two sets of key components in the DC-DC converter that use the ISL6530. Switching elements are the most critical because they generate a lot of noise as a result. The next step is to connect sensitive nodes or provide critical bypass current for signal coupling. A multilayer printed circuit board is recommended. Figure 7 shows the key components in the connection converter. Note that capacitors CIN and COUT represent many physical capacitors. Dedicate a solid layer, usually the middle layer of the PC board, for grounding. Make plane and ground connections to all critical components. This layer has vias. Using another entity layer as a powered plane divides this plane into a common voltage level. Keep the metal shorted from the phase terminals of the output inductor. Power planes should support input power and output power nodes. Fill the circuit layers of the polygon phase node with copper on the top and bottom. Use the remaining printed content for circuit layers for small signal routing. The trace of the wire from the gate pin to the gate of the MOSFET should be kept short and wide enough to easily handle 1A of drive current.