The ISL6753 is a high-performance, low-pin-count alternative, zero-voltage switching (ZVS) full-bridge PWM controller. Like the ISL6551, it adjusts the resonant switching delay by driving the high-side FET at a fixed 50% duty cycle while the trailing edge of the low-side FET modulates the switching delay. In contrast, this algorithm provides the equivalent efficiency and improved overcurrent and light load performance of common phase-shift control methods, in a lower pin count package with less complexity. This advanced BiCMOS design features low computational current, adjustable oscillator frequency up to 2 MHz, adjustable soft-start, internal thermal protection, precise dead-time and resonance delay control, and propagation delay. Additionally, multi-pulse suppression ensures that alternate output pulses at low duty cycles may experience pulsing.

feature

Adjustable resonance delay for ZVS operation

Voltage or Current Mode Operation

3% Current Limit Threshold

175µA starting current

Supply UV

Adjustable Deadband Control

Adjustable soft start

Adjustable oscillator frequency up to 2 MHz

Tight tolerance error amplifier reference on line, load and temperature

5MHz GBWP Error Amplifier

Adjustable cycle-by-cycle peak current limit

Fast current sense output delay

70ns leading edge blanking

multipulse suppression

Buffered oscillator sawtooth output

Internal overheat protection

Lead free + annealed and ELV, WEEE available, RoHS compliant

application

ZVS full bridge converter

Telecom and Datacom Power Supplies

Wireless base station power supply

file server power

Industrial Power Systems

Absolute Maximum Ratings Thermal Information

Supply voltage, VDD. Ground -0.3V to +20.0V

out. Ground -0.3V to VDD

signal pin. Ground -0.3V to VREF+0.3V

VREF. Ground -0.3V to 6.0V

Peak gate current. 0.1 Amp

Electrostatic discharge classification

Human body model (per MIL-STD-883 method 3015.7). 3000 volts

Charger model (according to EOS/ESD DS5.3, 4/14/93). 1000 volts

operating conditions

temperature range

ISL6753AAxx. -40°C to 105°C

Supply voltage range (typical). 9-16 VDC

Thermal Resistance (Typical) θJA (°C/Watt)

16-lead QSOP (Note 1). 95

maximum junction temperature. -55°C to 150°C

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius

(QSOP - lead only)

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. θJA is measured with components mounted on a high-efficiency thermal conductivity test board in free air. See Technical Bulletin TB379 for details.

2. All voltages are related to ground.

Operating conditions recommended by electrical codes unless otherwise stated. Refer to the block diagram and typical application schematic. 9V

Operating conditions recommended by electrical codes unless otherwise stated. Reference Block Diagram and Typical Applications

Schematic. 9V

notes:

3. Specifications at -40°C and 105°C are guaranteed by the 25°C test with margin limitations.

4. Guaranteed by design, not 100% tested in production.

5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Use other values for these components to obtain larger or smaller maximum duty cycles. See Equations 1-5.

6. Adjust VDD below the UVLO stop threshold before setting to 7V.

Pin Description

VDD—VDD is the power supply connection for the integrated circuit. To optimize noise immunity, bypass VDD to GND with ceramic capacitors as close as possible to the VDD and GND pins. Supply voltage undervoltage lockout (UVLO) start and stop thresholds track each other resulting in relatively constant hysteresis. GND—The signal and power ground connections for this device. A low impedance layout is necessary due to high peak currents and high frequency operation. Ground plane and short traces are strongly recommended. VREF-5.00V reference voltage output with 3% line, load and operating temperature tolerance. Bypass to ground with a 0.1 to 2.2µF low ESR capacitor. The CT-Oscillator timing capacitor is connected between this pin and ground. It uses an internal 200µA charge current source and a user adjustable current discharge source controlled by an RTD. RTD - This is the oscillator timing capacitor discharge current control pin. The current flowing into the resistor The connection between this pin and GND determines the magnitude of the CT discharge current. The CT discharge current is nominally 20 times the resistor current. The PWM dead time is determined by the timing capacitor to the discharge time. The voltage at the RTD is nominally 2.00V. This is the input to the overcurrent comparator. This overcurrent comparator threshold is set to 1.00V nominal. The CS pin is a PWM output. Depending on the current sense source impedance, a series input resistor may be required between the internal clock and the external power switch due to delays. This delay may cause the CS to shut down at the power switch device. Ramp - This is the input PWM comparator for the sawtooth wave. Ramp pin at the termination of the PWM signal. Sawtooth Voltage This input requires a waveform. For current mode control this pin is connected to CS and the current loop feedback signal is applied to both inputs. For voltage mode control, the oscillator sawtooth wave can be buffered and used. To generate a proper signal, a ramp can be connected through an RC network before the input voltage To control, or ramp can be connected to VREF through an RC network to generate the desired sawtooth waveform.

OUTUL and OUTUR - These outputs control the upper bridge FET and run an alternating sequence at a fixed 50% duty cycle. OUTUL controls the top left FET and OUTUR controls the top right FET. As long as the left and right are turned on, you can switch the name to connect with the lower FET output, output and output. RESDEL - Sets the switching of the upper FET and the lower FET. The voltage applied to RESDEL determines when the upper FET switches on and off relative to the rotation of the lower FET. Changing the control voltage from 0 to 2.00V increases the resonance delay duration by 0-100% of the dead time. This control voltage divided by 2 means that the dead time is equal to the resonance delay. In practice the maximum resonant delay must be set below 2.00V to ensure that at maximum duty cycle, the lower FET turns off before the upper FET switches. OUTLL and OUTLR - These outputs control the lower bridge FETs and are pulse width modulated, in alternating order. OUTLL controls the lower left FET and OUTLR controls the lower right FET. Left and right as long as turn on, you can switch the name and upper FET output, output and O'Toole. VERR - Control voltage input to the PWM comparator. The output of the external error amplifier (EA) is applied to this input for closed-loop regulation. Vail has a nominal 1mA pull-up current source. FB-FB is the inverting input of the error amplifier (EA). SS - Connect a soft-start timing capacitor across this pin to control the soft-start duration. The value of the capacitor determines the rate of increase in the duty cycle during startup cycles. SS can also be used to suppress the output by grounding it through a small transistor configuration in the collector/drain. CTBUF-CTBUF is a sawtooth buffered output CT with oscillator waveforms that can source 2mA. It is offset from ground by 0.40V and has a nominal valley-to-peak gain of 2. Can be used for slope compensation.

Function description

feature

The ISL6753 PWM is the best choice for low-cost zero-voltage switching rectification of full-bridge applications with conventional outputs. If simultaneous correction is required, consider the ISL6752 or ISL6551 products. Highly flexible designs with minimal external components are possible with many of the protection and control functions of the ISL6753. Its many features include support for current and voltage mode control, very precise overcurrent limit thresholds, thermal protection, buffered sawtooth oscillator output suitable for slope compensation, voltage controlled resonance delay, adjustable frequency with precise dead time control. Oscillator ISL6753 has a programmable oscillator frequency range of 2 MHz, programmable with external resistors and capacitors. The switching period is the total charge and discharge duration of the timing capacitors. Charge time is determined by CT and a fixed 200µA internal current source. The duration of discharge is determined by RTDs and current transformers.

where TC and TD are the charge and discharge times, TSW is the oscillation period, and FSW is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual time will be calculated about 10ns/transition due to the internal propagation delay of . This delay directly increases the switching duration, but also causes the timing to overshoot the capacitor peak-to-valley voltage threshold, effectively increasing the peak-to-peak voltage across the timing capacitor. Also, if you use a very small discharge current, you will increase the error pin due to the input impedance of the CT. The maximum duty cycle D and the percentage of dead time DT can be calculated as:

soft start operation

The ISL6753 has a soft-start function using an external capacitor connected to an internal current source. Soft-start reduces component stress and inrush current during startup. At start-up, the soft-start circuit limits the error voltage input (VERR) to a value equal to the soft-start voltage. This output pulse width increases as the soft-start capacitor increases and the voltage rises. This increases the duty cycle from zero to adjust the pulse width during soft-start. When the soft-start voltage exceeds the error voltage, the soft-start is completed. Soft-start occurs after startup and fault recovery. The soft-start charge cycle is calculated as follows:

where t is the charge cycle in ms and C is the soft-start capacitor in microF. The soft-start voltage is clamped to 4.50V with a 2% tolerance. It is suitable as a "soft start" reference if the current consumption is kept below the 70µA charging current. Use the SS pin as the disable input. Pull SS below 0.25V and all outputs will go low. An open collector/drain configuration can be used to couple a disable signal into the SS pin. The output of the gate drive ISL6753 is capable of sourcing and sinking 10mA (nominal VOH, VOL) for use in combination with integrated FET drivers or discrete bipolar totem pole drivers. The typical on-resistance of the output is 50 ohms. Cycle-by-cycle peak current limiting for overcurrent operation results in a pulse-by-pulse current feedback signal that reduces the duty cycle by more than 1.0V. When the peak current exceeds the threshold, the active output pulse is terminated immediately. This results in a decrease in the output voltage beyond the current limit threshold as the load current increases. The ISL6753 operates continuously in an overcurrent state without shutting down. If voltage-mode control is used in a bridge topology, it should be noted that peak current limiting causes inherently unstable operation. The DC blocking capacitor bridge topology in voltage mode becomes unbalanced, like a transformer core. The method of latching overcurrent shutdown using external components is recommended. The CS propagation delay exceeds the current limit output pulse termination threshold and increases through the leading edge blanking (LEB) interval. The effective delay is the sum of the two delays, nominally 105ns. Voltage Feedforward Operation Voltage feedforward is an intervention in the control loop used to regulate the output voltage as the input voltage changes. Voltage feedforward is usually implemented in the voltage mode control loop, but redundancy is not necessary in the peak current mode control loop. Voltage feedforward works by adjusting the sawtooth to operate on a ramp proportional to the input voltage. Figure 5 demonstrates the concept.

Input voltage feedforward can use ramp input. The RC network connected between the input terminals, as shown in Figure 7, voltage and ground, produces a voltage ramp whose charging rate varies with the amplitude of the source voltage. The pulses are ramped to ground at the active output to generate a sawtooth wave. The ramp waveform is compared with the VERR voltage to determine the duty cycle. The choice of this reinforced concrete member depends on the desired input voltage operating range and oscillator. In a typical application, the reinforced concrete member is selected to have the minimum input voltage at which the ramp amplitude is within half a cycle.

When switching, the UR-LL power transfer cycle is terminated as a result of the pulse width modulation and the LL is turned off. The water flow must find an alternate path in the primary path. The water flow injects the parasitic switched capacitor, charges the node to the VIN, and then forward biases the upper body diode to switch UL. As before, the output inductor current contributes to this transition. The primary leakage inductance, LL, holds the current, which now circulates around the path switch UR, transformer primary, and switch UL. when? The switch LL is turned on, and the output inductor currentless wheel mainly passes through the diode D1. Diode D2 can actually have little or no free-wheeling current, depending on circuit parasitics. This condition persists for the remainder of the half cycle. You have to find another way when the switch is up. It charges/discharges the parasitic capacitance of the switch until the body diode of the LR is forward biased. If RESDEL is set correctly, switch LR will be on at this time. When switching LR, the first power transfer cycle begins to turn off and the cycle repeats. ZVS conversion requires leakage inductance to have enough energy stored to fully charge the parasitic capacitance. Because the energy stored current is proportional to the square of the current (1/2 LLIP2), the ZVS resonance transition is load dependent. If the leakage inductance cannot store enough energy for the ZVS, a discrete inductance can be combined with the transformer primary. Fault condition if VREF or VDD falls below the undervoltage lockout (UVLO) threshold or protection is triggered. When a fault is detected, the soft-start capacitor is rapidly discharged and the output is disabled low. The soft-start cycle begins when the fault condition clears and the soft-start voltage falls below the reset threshold. An overcurrent condition is not considered a fault and will not result in a shutdown. Thermal protection provides internal mold over-temperature protection. An integrated temperature sensor protects the device from a junction temperature over 140°C with a hysteresis of approximately 15°C. The ground plane requires careful layout for the installation. A good ground plane must be used. VDD and VREF should be bypassed directly to high frequency capacitors to ground.