Summary

High-performance signaling computer for communications, audio, automotive, instrumentation, and industry; Super Harvard Architecture Computer (SHARC); four independent buses for dual data, instruction, and I/O fetches on a single cycle; 32-bit fixed-point arithmetic; 32-bit and 40-bit floating point operations; 544kbits of on-chip SRAM memory and integrated I/O; Peripherals: I2S support, 8 simultaneous receive and transmit channels; Key Features: 66mips, 198 MFLOPS peak, 132 MFLOPS sustained; Performance: user configurable 544kbits On-chip SRAM memory; two external ports, DMA channels and eight serial ports, DMA channels; low cost glueless interface SDRAM controller; external memory (@66 MHz); 64M words external address range; 12 programmable I/ O pin and two timers with events; capture option; code compatible with ADSP-2106x series; 208 lead MQFP or 196 fans in your BGA package; 3.3 volt operation; flexible data format and 40-bit extended precision; 32-bit Single and 40-bit extended precision IEEE; floating-point data format; 32-bit fixed-point data format, integer and fractional, with dual 80-bit accumulators; parallel computing; single-cycle multiply and arithmetic operations in parallel with dual memory read/write and instruction fetch ; Multiply with addition and subtraction to speed up the FFT, but simple to compute; 1024-point complex FFT benchmark: 0.274 ms (18221 cycles).

544kbits configurable on-chip SRAM; dual ports with independent access via core processor and DMA; configurable as a combined DMA controller for 16, 32, 48-bit data and program words in block 0 and block 1; 10 DMA channels, 2 8 dedicated to external ports; 8 dedicated to serial ports; parallel, up to 66 MHz background DMA transfers; performed using full-speed processor; transfers performed between: internal RAM and host; internal RAM and serial port; internal RAM and master/slave SHARC; internal RAM and external memory or I/O devices; external memory and external devices; host processor interface; -21065L IOP registers; multiprocessing; glueless parallel distributed on-chip bus arbitration; bus connection between two ADSP-21065Ls Plus hosts; 132mbytes/s parallel bus transfer rate; serial port; independent transmit and receive functions; Programmable 3-bit to 32-bit serial word width; I2S supports 8 transmit and 8 receive channels; glueless interface to industry standard codecs; TDM multi-channel mode companding with -law/A-law hardware; multichannel signaling protocol.

General Instructions

The ADSP-21065L is a powerful member of SHARC's family of 32-bit processors optimized for cost-sensitive applications. SHARC Super Harvard architectures provide the highest levels of performance and memory integration of any 32-bit DSP in the industry. They are also the only DSPs in the industry to offer both fixed and floating-point functionality without compromising precision or performance.

The ADSP-21065L is manufactured in a high-speed, low-power CMOS process using 0.35-micron technology and has the highest performance of 32-bit DSP-66 MIPS (198 MFLOPS). With the on-chip instruction cache, the processor can execute each instruction in one cycle. Table 1 lists the ADSP-21065L.

The ADSP-21065L SHARC combines a floating-point digital signal processor core with integrated system-on-chip functions, including 544kbit of SRAM memory, a host processor interface, a DMA controller, an SDRAM controller, and an enhanced serial port.

Figure 1 shows a block diagram of the ADSP-21065L illustrating the following architectural features: with shared data register file; data address generators (DAG1, DAG2); program sequencer with instruction cache; timer with event capture mode; on-chip Dual port SRAM; interfacing with off-chip memory and peripherals; host port and SDRAM; DMA controller; enhanced serial port; JTAG test access port.

ADSP-21000 Series Core Architecture

The ADSP-21065L is code and function compatible with the ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L includes the following architectural features at the heart of the SHARC family.

Independent parallel computing unit

The arithmetic/logic unit (ALU), multiplier, and shifter all execute single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. A single multifunction instruction performs parallel arithmetic unit and multiplier operations. These computational units support IEEE 32-bit single-precision floating-point, extended-precision 40-bit floating-point, and 32-bit fixed-point data formats.

data register file

The general purpose data register file is used to transfer data between the computational unit and the data bus, and to store intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows for unconstrained data flow between the compute unit and internal memory.

Single-Cycle Fetch of Instructions and Two Operands The ADSP-21065L employs an enhanced Super Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers instructions and data (see Figure 1). With its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from cache) in one cycle.

instruction cache

The ADSP-21065L includes an on-chip instruction cache that supports triple bus operations to fetch one instruction and two data values. The cache is selective and only caches fetch instructions that conflict with PM bus data accesses. This allows core, looping operations such as digital filter multiply-accumulate and FFT butterfly processing to be performed at full speed.

Data Address Generators with Hardware Circular Buffers The ADSP-21065L's two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required for digital signal processing, typically used in digital filters and Fourier transforms. The two DAGs of the ADSP-21065L contain enough registers to create up to 32 circular buffers (16 primary register sets, 16 secondary register sets). DAGs automatically handle wrapping address pointers, reducing overhead, improving performance, and simplifying implementation. A circular buffer can start and end at any memory location.

Flexible instruction set

The 48-bit instruction word accommodates various parallel operations for concise programming. For example, the ADSP21065L can conditionally perform multiply, add, subtract, and branch in one instruction.

ADSP-21065L Features

The ADSP-21065L is designed to achieve the highest system throughput for maximum system performance. It can be clocked by a crystal or a TTL compatible clock signal. The frequency of the input clock used by the ADSP-21065L is equal to half the instruction rate - an input clock of 33 MHz yields 15 nanoseconds of processor cycles (equivalent to 66 MHz). The interface operation on the ADSP-21065L is shown below. Later in this article, 1x = input clock frequency, 2x = instruction rate of the processor.

The following clock operating ratings are based on 1x=33MHz (instruction rate/core=66MHz):

SDR 66 MHz

External SRAM 33 MHz

Serial port 33 MHz

Multiprocessing 33 MHz

Host (asynchronous) 33 MHz

Expanding the core of the ADSP-21000 series, the ADSP-21065L adds the following architectural features:

Dual-port on-chip memory

The ADSP-21065L contains 544kbits of on-chip SRAM, divided into two groups: 0 group of 288kbits and 1 group of 256kbits. The 0th column is arranged with 9 columns of 2K×16 bits, and the first column is arranged with 8 columns of 2K×16 bits. Each memory block is dual-ported and independently accessed in a single cycle by the core processor and the I/O processor or DMA controller. The dual-port memory and separate on-chip bus allow two data transfers from the core and one data transfer from the I/O in one cycle (see Figure 4 for the ADSP-21065L memory map).

On the ADSP-21065L, memory can be configured for a maximum of 16K words of 32-bit data, a maximum of 34K words of 16-bit data, a maximum of 10K words of 48-bit instructions (and 40-bit data), or a combination of different word sizes of up to 544kbits. All memory can be accessed as 16-bit, 32-bit or 48-bit.

Although each memory block can store a combination of code and data, when one block stores data, the DM bus is used for transmission, and when another block stores instructions and data, the PM bus is used for transmission, and the access efficiency is the highest. Using the DM and PM buses in this way, each memory block has a dedicated bus, ensuring that two data transfers are performed in a single cycle. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from the ADSP21065L's external port.

Off-chip memory and peripheral interface The external port of the ADSP-21065L provides the interface between the processor and off-chip memory and peripheral devices. The off-chip address space of 64M words is contained in the unified address space of the ADSP-21065L. Separate on-chip buses for program memory, data memory, and I/O are multiplexed on external ports to create an external system bus with a single 24-bit address bus, four memory selects, and a single 32-bit data bus. The on-chip Super Harvard architecture provides triple-bus performance, and the off-chip unified address space provides flexibility for designers.

SDRAM interface

The SDRAM interface enables the ADSP-21065L to transfer data between Synchronous DRAM (SDRAM) at 2x clock frequency. The synchronization method plus 2x the clock frequency supports high throughput data transfer up to 220mbytes/sec.

The SDRAM interface provides a glueless interface with standard SDRAM - 16mb, 64mb and 128mb, including the option to support additional buffers between the ADSP-21065L and SDRAM. The SDRAM interface is flexible enough to connect SDRAM to any of the four external memory banks of the ADSP-21065L.

Systems with multiple SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The ADSP-21065L supports pipelining of address and control signals to implement this buffering between itself and multiple SDRAM devices.

host processor interface

The host interface of the ADSP-21065L provides simple connection to standard microprocessor buses (8-bit, 16-bit and 32-bit) without additional hardware. Supporting asynchronous transfer speeds up to 1x clock frequency, the host interface is accessed through the external port of the ADSP-21065L. The host interface provides two DMA channels; code and data transfers are done with low software overhead.

The host processor requests the ADSP-21065L's external bus using the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the IOP register of the ADSP-21065L, and can access the DMA channel settings and mailbox registers. Vectored interrupt support enables efficient execution of host commands.

DMA controller

The ADSP-21065L's on-chip DMA controller allows zero-overhead, non-intrusive data transfers without processor intervention. The DMA controller operates independently and invisible to the processor core, allowing DMA operations to occur while the cores are executing their program instructions concurrently.

DMA transfers can occur between the ADSP-21065L's internal memory and external memory, external peripherals, or the host processor. DMA transfers can also occur between the ADSP-21065L's memory and the serial port. DMA transfers between external memory and external peripherals are another option. Perform external bus packing of 16-, 32-, or 48-bit internal words during DMA transfers.

There are 10 DMA channels on the ADSP-21065L, 8 through the serial port and 2 through the processor's external port (for host processor, other ADSP-21065L, memory, or I/O transfers). Programs can be downloaded to the ADSP21065L using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using the DMA request/grant lines (DMAR1-2, DMAG1-2). Other DMA features include interrupt generation when a DMA transfer is completed and DMA linking to automatically link DMA transfers.

serial port

The ADSP-21065L features two synchronous serial ports that provide an inexpensive interface to a variety of digital and mixed-signal peripherals. Serial ports can operate at 1x clock frequency, providing a maximum data rate of 33 Mbit/s per port. Each serial port has a set of primary and a set of secondary transmit and receive channels. Separate transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred between on-chip memories via DMA. Each serial port supports three modes of operation: DSP serial port mode, I2S mode (a common interface for audio codecs), and TDM (time division multiplexing) multi-channel mode.

Serial ports can use little-endian or big-endian transfer formats, with optional word lengths from 3 bits to 32 bits. They offer selectable synchronization and transmission modes and selectable μ-law or A-law companding. Serial port clock and frame synchronization can be generated internally or externally. The serial port also includes keyword and key masking capabilities to enhance interprocessor communication.

Programmable Timers and General Purpose I/O Ports The ADSP-21065L has two independent timer blocks, each of which performs two pulse width generation and pulse count and capture functions.

In pulse width generation mode, the ADSP-21065L can generate modulated waveforms with arbitrary pulse widths within a maximum period of 71.5 seconds.

In pulse counter mode, the ADSP-21065L can measure the high or low pulse width and period of the input waveform.

The ADSP-21065L also contains 12 programmable general-purpose I/O pins that can be used as inputs or outputs. As outputs, these pins can send signals to peripheral devices; as inputs, these pins can provide tests for conditional branches.

program start

The internal memory of the ADSP-21065L can be accessed from an 8-bit EPROM, the host processor, or external memory at system power-up. Boot source selection is controlled by the BMS (boot memory select) and BSEL (boot from EPROM) pins. An 8-bit, 16-bit or 32-bit host processor can be used for booting. For more information, see the BMS and BSEL pin descriptions in the Pin Descriptions section of this datasheet.

multiprocessing

The ADSP-21065L provides powerful functions for multiprocessing digital signal processing systems. The unified address space allows direct inter-processor access to the IOP registers of the two ADSP-21065Ls. Distributed bus arbitration logic is included on-chip for simple, glue-free connection of systems consisting of up to two ADSP-21065Ls and a host processor. The main processor switch incurs only one cycle of overhead. Bus locks allow an indivisible read-modify-write sequence of semaphores. Provides vectored interrupts for interprocessor commands. The maximum throughput of data transfer between processors on the external port is 132 MB/sec.

development tools

The ADSP-21065L supports a full suite of software and hardware development tools, including the EZ-ICE® InCircuit simulator and development software.

The EZ-ICE hardware for the ADSP-21060/ADSP-21062 also fully emulates the ADSP-21065L.

The ADSP-21065L is supported by both the SHARC family of development tools and the VisualDSP® integrated project management and debug environment. The VisualDSP project management environment enables you to develop and debug applications from a single integrated program.

SHARC development tools include an easy-to-use assembler based on an algebraic syntax; an assembly library/library; a linker; a loader; a loop-accurate instruction-level simulator; a C compiler; The C runtime library.

Using the Visual DSP debugger to debug C and assembler, you can:

8226 ; View mixed C and assembly code

• Insert breakpoints

• Set up observation points

• Track bus activity

• Summary program execution

• Fill and dump memory

• Create custom debugger windows

Visual IDE enables you to define and manage multi-user projects. Its dialogs and property pages allow you to configure and manage all SHARC development tools. This feature enables you to:

• Control how the development tool handles input and generates output.

• Maintain one-to-one communication with the tool's command line switches.

The EZ-ICE emulator uses the IEEE 1149.1jtag test access port of the ADSP-21065L processor to monitor the target board processor during the emulation process. EZ-ICE provides full-speed emulation, allowing inspection and modification of memory, registers, and the processor stack. Non-intrusive in-circuit emulation is ensured by using the processor's JTAG interface. The emulator does not affect the loading or timing of the target system.

In addition to the software and hardware development tools provided by the emulation devices, third parties also provide a range of tools that support the SHARC processor family. Hardware tools include SHARC-PC add-in cards, multiprocessor SHARC-VME boards, submodules and modules with multiple SHARCs and additional memory. These modules are based on the SHARCPAC™ module specification. Third-party software tools include Ada compilers, DSP libraries, operating systems, and block diagram design tools.

Additional Information

For more information on the ADSP-21065L instruction set and architecture, see the ADSP-21065L SHARC User Manual 3rd Edition and the ADSP-21065L SHARC Technical Reference.

Pin Description

The ADSP-21065L pin definitions are shown below. Inputs to be recognized as synchronous must meet timing requirements related to CLKIN (or to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asynchronously asserted as CLKIN (or asynchronously asserted as TCK for TRST).

Except for ADDR23-0, DATA31-0, FLAG11-0, SW, and inputs with internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI), unused inputs should be VDD or GND connected or pulled - these pins can be left floating. These pins have a logic level hold circuit that prevents the input from floating internally.

I = Input S = Synchronous P = Power (O/D) = Open Channel O = Output A = Asynchronous G = Ground

T = three states (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

clock signal

The ADSP-21065L can use an external clock or crystal. See CLKIN pin description. The ADSP-21065L can be configured to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. You can use crystals that work in fundamental mode or crystals that work in overtones. Figure 4 shows the component connections used by the crystal operating in fundamental mode, and Figure 5 shows the component connections used by the crystal operating in overtones.

EZ-ICE Probe Target Board Connector

The ADSP-2106x EZ-ICE emulator uses the IEEE1149.1JTAG test access port of the ADSP-2106x to monitor the target board processor during the emulation process. The EZ-ICE probe requires that the CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals of the ADSP-2106x are accessible on the target system through a 14-pin connector (2 rows x 7-pin strip header), as shown in Figure 6 Show. The EZ-ICE probe plugs directly into this connector for analog chips on the board. If you plan to use the ADSP-2106x EZ-ICE, you must add this connector to your target board design.

The total trace length between the EZ-ICE connector and the farthest device sharing the EZ-ICE JTAG pins should be limited to a maximum of 15 inches for guaranteed operation. The limitation on length must include EZ-ICE JTAG signals routed to one or more 2106x devices or a combination of 2106x and other JTAG devices on the chain.

The pin 3 position of the 14-pin, double-row pin strap header is key, you must remove pin 3 from the header. Pins must be 0.025 inches square and at least 0.20 inches long. Pin spacing should be 0.1 x 0.1 inches. Needle headers are available from suppliers such as 3M, McKenzie, and Samtec.

BTMS, BTCK, BTRST and BTDI signals are provided so that the test access port can also be used for board level testing. When the connector is not used for emulation, place a jumper between the Bxxx pins and the xxx pins. If you are not going to use the test access port for board testing, connect BTRST to GND and BTCK to VDD. The TRST pin must be asserted after power is applied (via BTRST on the connector) or held low for the ADSP-2106x to function properly. No Bxxx pins (pins 5, 7, 9, 11) are connected to the EZ-ICE probes.

The JTAG signal is terminated on the EZ-ICE probe as follows:

Connecting CLKIN to pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when instructed to perform operations such as starting, stopping, and single-stepping two ADSP-21065Ls in a synchronous manner. If you don't need to do these things synchronously on both processors, just connect pin 4 of the EZ-ICE header to ground.

For systems using an internal clock generator and an external discrete crystal, do not connect the CLKIN pin directly to the JTAG probe. This loads the oscillator circuit and may cause it to fail to oscillate. Instead, the CLKIN of the JTAG probe can be driven from the XTAL pin through a high impedance buffer.

If simultaneous multiprocessor operation is required and CLKIN is connected, the clock skew between multiple ADSP-2106x processors and the CLKIN pins on the EZ-ICE header must be minimal. If the deviation is too large, synchronous operations may be shut down for a cycle between processors. For simultaneous multiprocessor operation, TCK, TMS, CLKIN, and EMU should be considered critical signals in terms of skew and should be placed as short as possible on your board.

If synchronous multiprocessor operation is not required (i.e. CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of tilt.

For complete information on SHARC EZ-ICE, see the ADSP-21000 Series JTAG EZ-ICE User Guide and Reference.

Timing Specifications General Notes

The ADSP-21065L offers two speed grades: 60MHz and 66MHz instruction rate. The specifications shown are based on a CLKIN frequency of 30 MHz (tCK=33.3 ns). DT derating allows specification at other CLKIN frequencies (within the min-max range of the tCK specification; see Clock Inputs below). DT is the difference between the actual CLKIN period and the 33.3 ns CLKIN period:

Use the given precise timing information. Don't try to get arguments from other addition and subtraction operations. While addition or subtraction will yield meaningful results for a single device, the values given in this data sheet reflect statistical variation and worst-case scenarios. Therefore, parameters cannot be meaningfully added to get longer. For voltage reference levels, see Equivalent Device Loading for AC Measurements (including all fixtures) in Figure 27.

Switch characteristics specify how the processor changes its signals. Timing circuits outside of the processor that you cannot control must be designed to be compatible with these signal characteristics. Switch characteristics tell you what the processor will do in a given situation. You can also use the toggle feature to ensure that any timing requirements of devices attached to the processor, such as memory, are met.

Timing requirements apply to signals controlled by circuits external to the processor, such as data inputs for read operations. Timing requirements ensure that the processor works properly with other devices.

(O/D) = open channel (A/D) = active drive

Memory read bus master

Use these specifications to asynchronously connect to memory (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching characteristics also apply to the bus master synchronous read/write timing (see Synchronized Read/Write Bus Master below). Synchronous read/write timing can be ignored if these timing requirements are met (and vice versa). The exception is the ACK pin timing requirement as described in the note below.

W = (number of wait states specified in the wait register) × tCK.

HI=tCK (if an address hold cycle or bus idle cycle occurs, as specified in the wait register; otherwise HI=0). H=tCK (H=0 if the address hold period is specified in the wait register).

Notes: 1. Data Delay/Setup: User must meet tDAD or tDRLD or synchronization specification tSSDATI. 2. Refer to the falling edge of MSx, SW, and BMS. 3. ACK is not sampled on external memory accesses using internal wait state mode. For the first CLKIN cycle of a new external memory access, the ACK must be valid for either external wait state mode or both (or both if the internal wait state is zero) via tDAAK or tDSAK or the synchronization specification tSACKC. For the second and subsequent cycles of an external memory access of a wait state, the synchronization specifications tSACKC and tHACKC for the external wait state mode, or both (after completion of the internal wait state), must be satisfied.

memory write bus master

Use these specifications to asynchronously connect to memory (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching characteristics also apply to the bus master synchronous read/write timing (see Synchronized Read/Write Bus Master below). Synchronous read/write timing can be ignored if these timing requirements are met (and vice versa). The exception is the ACK pin timing requirement as described in the note below.

W = (number of wait states specified in the wait register) × tCK.

H=tCK (if an address hold cycle occurs, as specified in the wait register; otherwise H=0). I=tCK (if a bus idle cycle occurs, as specified in the wait register; otherwise I=0).

Notes: 1. ACK is not sampled on external memory accesses using internal wait state mode. For the first CLKIN cycle of a new external memory access, the ACK must be valid for either external wait state mode or both (or both if the internal wait state is zero) via tDAAK or tDSAK or the synchronization specification tSACKC. For the second and subsequent cycles of an external memory access of a wait state, the synchronization specifications tSACKC and tHACKC for the external wait state mode, or both (after completion of the internal wait state), must be satisfied. 2. Refer to the falling edge of MSx, SW and BMS. 3. For hold-up time calculations for a given capacitance and DC load, see System hold-up time calculations under test conditions.

Synchronous read and write bus master

Use these specifications to connect to external memory systems that require CLKIN-relative timing, or to access slaves from the ADSP-21065L (in the multiprocessor memory space). These synchronous switching features are also valid during asynchronous memory reads and writes (see Memory Read Bus Mastering and Memory Write Bus Mastering).

When accessing the slave ADSP-21065L, these switching characteristics must meet the timing requirements for slave synchronous read/write (see Synchronous Read/Write Bus Slave). The slave ADSP-21065L must also meet (bus master) timing requirements for data and acknowledge setup and hold times.

W = (number of wait states specified in the wait register) × tCK.

Notes: 1. Data Retention: User must meet tHDA or tHDRH or synchronization specification tHDATI. For holdup calculations for a given capacitive and DC load, see System Holdup Calculations Under Test Conditions. Mistaken on external memory access using internal wait state mode. 2. ACK is sampled. For the first CLKIN cycle of a new external memory access, the ACK must be valid for either external wait state mode or both (or both if the internal wait state is zero) via tDAAK or tDSAK or the synchronization specification tSACKC. For the second and subsequent cycles of an external memory access of a wait state, the synchronization specifications tSACKC and tHACKC for the external wait state mode, or both (after completion of the internal wait state), must be satisfied. 3. For hold-up time calculations for a given capacitance and DC load, see System hold-up time calculations under test conditions.

Synchronous read and write bus slave

Use these specifications for ADSP-21065L bus master access to slave IOP registers or internal memory (in the multiprocessor memory space). The bus master must meet these (bus slave) timing requirements.

Notes: 1. When the multiprocessor memory space wait state (MMSWS bit in the wait register) is disabled, specify tSRWLI; when MMSWS is enabled, tSRWLI(min)=17.5+18 DT. 2. For the hold-up time calculation for a given capacitance and DC load, please refer to the system hold-up time calculation under test conditions.

To make two ADSP-21065Ls communicate as master and slave synchronously, a certain combination of master and slave specifications must be met. Do not directly compare the specification values to calculate the master/slave clock skew for the following specifications. The following table shows the appropriate clock offset margins.

Multiprocessor Bus Requests and Host Bus Requests

Use these specifications on multiprocessing ADSP-21065Ls (BRx) or host processors (HBR, HBG).

Notes: 1. For the first asynchronous access after HBR and CS are asserted, ADDR23-0 must be a non-ms value of 1/2 tCK before RD or WR goes low, and must be tHBGRCSV low after HBG goes low. This is easily accomplished by driving a high address signal when the HBG is asserted. Please refer to the ADSP-21065L SHARC User Manual, Second Edition. 2. Identification is only required in the current cycle. 3. The CPA assertion must satisfy the CLKIN setting; the deassertion does not need to satisfy the CLKIN setting. 4. (O/D) = open drain, (A/D) = active drive.

Asynchronous read and write host to ADSP-21065L

Asynchronous host processor accesses to the ADSP-21065L use these specifications after the host asserts CS and HBR (low). After the ADSP-21065L returns to HBG, the host can drive the RD and WR pins to access the IOP registers of the ADSP-21065L. HBR and HBG are assumed to be low at this time point. Writes can occur with a minimum interval of (1/2) tCK.

Note: Not required if RD and address are valid tHBGRCSV after HBG goes low. For the first access after asserting HBR, ADDR23-0 must be a non-minimum 1/2 tCLK before RD or WR goes low, or tHBGRCSV after HBG goes low. This is easily accomplished by driving a high address signal when the HBG is asserted. See Host Interfaces in the ADSP-21065L SHARC User Manual, Rev. 2.

Tri-state timing bus master, slave, HBR, SBTS

These specifications show how the memory interface can be disabled (stop driving) or enabled (resume driving) with respect to the CLKIN and SBTS pins. This timing applies to the bus master conversion cycle (BTC) and host conversion cycle (HTC) and SBTS pins.

Notes: 1. Strobe = RD, WR, SW, DMAG. 2. These specifications apply to bus master/slave synchronous read/write in addition to bus master transition cycles. 3. Memory Interface = Address, RD, WR, MSx, SW, DMAGx, BMS (in EPROM boot mode).

DMA handshake

These specifications describe three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For hand crank mode, the DMAG controls the locking or enabling of external data. For external handshake mode, control data transfer is through ADDR23-0, RD, WR, SW, MS3-0, ACK and DMAG signals. External mode cannot be used for transfers with SDRAM. For master mode, data transfer is controlled by ADDR23-0, RD, WR, MS3-0 and ACK (not DMAG). For rhythmic master mode, the memory read bus master, memory write bus master, and synchronous read/write bus master timing specifications ADDR23-0, RD, WR, MS3-0, SW, DATA31-0, and ACK also apply.

W = (number of wait states specified in the wait register) × tCK.

HI=tCK (if an address hold cycle or bus idle cycle occurs, as specified in the wait register; otherwise HI=0).

Notes: 1. Identification is only required in the current cycle. 2. If DMARx is not used to delay write completion, then tSDATDGL is the data setup requirement. Otherwise, if DMARx low delays the write completion, tDATDRH can be driven by DMARx high. 3. tVDATDGH is valid if DMARx is not used to delay read completion. If DMARx is used to stretch the read time, then tVDATDGH = 8 + 9 DT + (n × tCK), where n is equal to the number of additional cycles for which the access is stretched. 4. For holdup time calculations for a given capacitance and DC load, see System Holdup Time Calculations under Test Conditions.

SDRAM interface bus master

This specification applies to ADSP-21065L bus master access to SDRAM.

Notes: 1. Command = SDCKE, MSx, RAS, CAS, SDWE, DQM and SDA10. 2. The SDRAM controller adds a SDRAM CLK three-state cycle delay (tCK/2) after the read.

SDRAM interface bus slave

These timing requirements allow the bus slave to sample SDRAM commands from the bus master and detect when a refresh occurs.

JTAG test access port and emulation

Notes: 1. System input = DATA31-0, ADDR23-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR2-1, ID1-0, IRQ2-0, FLAG11-0 , DR0x, DR1x, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BSEL, BMS, CLKIN, RESET, SDCLK0, RAS, CAS, SDWE, SDCKE, PWM event x.

2. System output = DATA31-0, ADDR23-0, MS3-0, RD, WR, ACK, SW, HBG, REDY, DMAG1, DMAG2, BR2-1, CPA, FLAG11-0, PWM event x, dtx, DT1x , TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, SDCLK0, SDCLK1, DQM, SDA10, RAS, CAS, SDWE, SDCKE, BM, XTAL.

output drive current

Test Condition Output Disable Time

When output pins stop driving, go into a high impedance state, and begin to decay from the high or low voltage they output, they are considered disabled. The time for the voltage on the bus to decay ∏V depends on the capacitive load CL and the load current IL. This decay time can be approximated by the following equation:

The output disable time, tDIS, is the difference between tMEASURED and tDECAY, as shown in Figure 26. The measured time t is the time interval from when the reference signal switches to when the output voltage decays ∏V from the measured output high voltage or output low voltage. tDECAY is calculated with test loads CL and IL, and ∏V equals 0.5 V.

Output enable time

An output pin is considered enabled when it transitions from a high-impedance state to start driving. The output enable time, tENA, is the interval from when the reference signal reaches a high or low voltage level to when the output reaches the specified high or low trip point, as shown in the output enable/disable diagram. If multiple pins are enabled (such as a data bus), the measurement is the measurement of the first pin to start driving.

System Hold Time Calculation Example

To determine the data output hold time in a particular system, first calculate tDECAY using the formula given above. For devices that require hold time, choose ∏V as the difference between the ADSP-21065L output voltage and the input threshold. A typical ∏V is 0.4 V. CL is the total bus capacitance (per data line) and IL is the total leakage or tri-state current (per data line). The hold time is tDECAY plus the minimum disable time (ie, tDATRWH for the write cycle).

capacitive load

Output delay and hold are based on standard capacitive loading: 50 pF on all pins. For loads other than the 50 pF rating, the given delay and hold specifications should be derated by 1.8 ns/50 pF. Figure 28 and Figure 29 show how the output rise time varies with capacitance. Figure 30 graphically shows how output delay and hold vary with load capacitance. (Note that this graph or derating does not apply to output disable delay; see the previous section for output disable time under test conditions.) The graphs of Figure 28, Figure 29, and Figure 30 may not be linear outside the ranges shown.

Power consumption

There are two parts to the total power dissipation: one is due to the internal circuitry and the other is due to the switching of the external output driver. Internal power consumption depends on the order of instruction execution and the number of data operands involved. See IDDIN calculation in the Electrical Characteristics section. The internal power consumption is calculated as follows:

The external component of the total power dissipation is caused by toggling of the output pins. Its size depends on:

– Number of output pins (O) toggled in each loop

– Maximum frequency at which the pin can be switched (f) – Load capacitance of the pin (C) – Voltage swing of the pin (VDD).

Calculate the external components using the following formula:

The load capacitance should include the package capacitance (CIN) of the processor. The frequency f consists of driving the load up and down again. In SDRAM burst mode, the address and data pins can drive high and low at a maximum rate of 1/tCK.

Example: Estimate PEXT based on the following assumptions:

– Systems with a set of external memory (32-bit)

– Two 1m x 16 SDRAM chips, each with a control signal load of 3 pF and a data signal load of 4 pF

– External data writes occur in burst mode, twice every 1/tCK cycle, with a potential frequency of 1/tCK cycle/s. Assuming 50% pin switching

– The external SDRAM clock frequency is 60 MHz (2/tCK).

For each type of pin that can be driven, the PEXT equation is calculated:

Typical power dissipation under these conditions can now be calculated by adding the typical internal power dissipation. (IDDIN see calculation in Electrical Characteristics section):

Note that the conditions that lead to a worst-case PEXT are not the same as the conditions that lead to a worst-case PINT. The maximum pin count cannot occur when 100% of the output pins switch from all 1s (1s) to all 0s (0s). Also note that it is not uncommon for applications to switch 100% or even 50% of the output at the same time.

Ambient Conditions Thermal Characteristics

The ADSP-21065L comes in a 208-lead MQFP and 196-fan BGA package.

The ADSP-21065L is specified for case temperature (TCASE). To ensure that TCASE is not exceeded, an airflow source can be used.

TCASE = case temperature (measured on top of package)

PD = power consumption (W) (this value depends on the specific application; the method for calculating partial discharge is shown under power consumption)

θJC=7.1°C/W, 208-lead MQFP

θJC=5.1°C/W, suitable for 196 fans of your BGA

Dimensions

Dimensions are in inches and (mm).

Notes: 1. The deviation between the actual position of each wire and the ideal value is within 0.003 (0.08) of the lateral measurement position.

2. Unless otherwise stated, center plots are typical.

3. The 208 lead MQFP is a metric package. Dimensions provided in English are approximate and should not be used for board design purposes.

Dimensions

Dimensions are in mm.

Notes: 1. The actual position of the ball grid is relative to the edge of the package. The actual position of each ball is within 0.10 of its ideal position relative to the ball grid.

2. Since this is a metric package, all measurements are provided in metric units. Analog Devices strongly recommend that you design with metric measurements only.

3. The diameter of the steel ball has been changed from the nominal 0.50 mm to 0.60 mm to comply with JEDEC Standard Publication 95 Box Outline Drawing MO-151. The 0.60 nominal ball DIAMETER product will be available in July 2000.