TSMC first announced its innovative system-integrated single-chip (SoIC) multi-chip 3D stacking technology to the outside world at the 24th Annual Technical Symposium in Santa Clara, California, USA in April 2018 .

Advancing Moore's Law TSMC Pushes SoIC 3D Packaging Technology

As the advanced nano-fabrication process is approaching the physical limit, the development of Moore's Law has become unsustainable, and it is no longer possible to reduce the line width while meeting the requirements of performance, power consumption, area and signal transmission speed; in addition, the packaging technology is difficult to keep up with the advanced process. The development process, so Samsung, TSMC, Intel and other foundry giants have stepped into the packaging field one after another, relying on advanced packaging technology to achieve higher performance, lower power consumption, smaller size, and faster signal transmission products. .

Even after gradually entering the post-Moore's Law era, the development focus of large wafer foundries has gradually shifted from the pursuit of more advanced nano-processes in the past to the innovation of packaging technology. However, SoIC was born under such a premise.

If it is estimated that TSMC officially entered the packaging field in 2009, SoIC is a sword that TSMC has spent ten years grinding out.

Wafer-to-wafer 3D IC technology

According to TSMC's description at the 24th Annual Technical Symposium, SoIC is an innovative multi-chip stacking technology and a wafer-on-wafer bonding technology. This is a 3D IC process technology that enables TSMC to produce 3D ICs directly for customers.

Figure 2: TSMC SoIC design architecture schematic. (source: vlsisymposium.org, Graphics: CTIMES)

What amazes the outside world is that the SoIC technology uses through-silicon (TSV) technology, which can achieve a bump-free bonding structure, and can integrate many adjacent chips of different properties together, and the most critical and mysterious part is , it lies in the bonding material, which is known as a confidential material worth up to one billion US dollars, so it can directly communicate with multi-layer chips through tiny pores, and achieve performance that is more than doubled in the same volume. In short, it can be sustained Maintain the advantage of Moore's Law.

Figure 3: Microchip floor plan of the SoIC. (source: vlsisymposium.org)

It is understood that SoIC is a new generation of innovative packaging technology developed based on TSMC's CoWoS (Chip on wafer on Substrate) and multi-wafer stacking (WoW) packaging technology. It will be applied to advanced processes of ten nanometers and below for wafer-level packaging. Bonding technology is regarded as a powerful tool to further strengthen the competitiveness of TSMC's advanced nano-process. In October 2018, TSMC has given a clear mass production time for the much-anticipated SoIC technology at the third-quarter legal conference. It is expected that TSMC's revenue contribution will begin in 2020, and will be mass-produced by 2021. more significant revenue contribution.

In June, when TSMC went to Japan to participate in the VLSI technology and circuit seminar to publish a technical paper, it also disclosed the paper on SoIC technology. The paper stated that the SoIC solution stacks bare die of different sizes, process technologies and materials. Compared to traditional 3D integrated circuit solutions using micro-bumps, TSMC's SoICs offer several times higher bump density and speed while significantly reducing power consumption. In addition, the SoIC can leverage TSMC's InFO or CoWoS back-end advanced packaging-to-technology to integrate other chips to create a powerful 3D×3D system-level solution.

It is widely recognized by the outside world that from the 2.5 version of CoWoS technology originally proposed by TSMC to the InFO (Integrated Fan Package) technology, which is a weapon that only eats Apple, the next thing to dominate the foundry industry is SoIC technology.

Spreading out TSMC's first quarter financial report for 2019, the revenue contribution of 10-nanometer and below nano-processes has greatly exceeded that of 16-nanometer process, highlighting that advanced processes of 10 nanometers and below are unstoppable in the future.

Therefore, in 2019, major electronic design automation (EDA) manufacturers, such as Cadence, Mentor, and ANSYS, have successively launched solutions that support TSMC SoIC, and have passed TSMC certification, ready to meet The glorious era of SoIC is coming.

Intel's "Foveros" 3D packaging technology creates the first heterogeneous processor

Intel (Intel) finally officially announced at this year's COMPUTEX that its 10-nanometer processor "Ice Lake" began mass production, but another 10-nanometer product "Lakefiled" was absent.

Although the same 10nm process is used, "Lakefiled" is a higher-end product and will be Intel's first heterogeneous integration processor using 3D packaging technology.

Figure 4: Stacking analysis diagram of Intel Foveros (source: intel)

According to information released by Intel, the "Lakefield" processor not only uses a 10nm FinFET process "Sunny Cove" architecture main core in a single chip, but also configures four "Tremont" architecture also produced in 10nm FinFET process. small core. In addition, there is a built-in LP-DDR4 memory controller, L2 and L3 cache memory, and an 11th-generation GPU.

The ability to pack so many processing cores and computing units into a single chip with an overall volume of only 12 x 12mm relies on the "Foveros" 3D packaging technology.

Figure 5: The block and architecture principle of Intel Foveros (source: intel)

On the Architecture Day at the beginning of the year, Intel also specifically explained the "Foveros" technology. Intel pointed out that, unlike past 3D chip stacking technology, Foveros can achieve direct bonding of logic chips to logic chips.

Intel said that the advent of Foveros can bring higher performance, high density and low power consumption processing chip technology to devices and systems. Foveros can surpass current chip stacking technology of passive interposers, while stacking memory on top of high-performance logic chips such as CPUs, graphics chips and AI processors for the first time.

In addition, Intel emphasized that the new technology will provide excellent design flexibility, especially when developers want to put mixed IP blocks of different types of memory and I/O elements in new device form factors. It can break down products into smaller "chiplets" structures, allowing I/O, SRAM and power delivery circuits to be built on the underlying die, followed by high-performance logic microchips. stacked on top of it.

Intel even emphasized that the advent of Foveros technology is a major progress in the company's 3D packaging, a major breakthrough after EMIB (Embedded Multi-die Interconnect Bridge) 2D packaging technology.

TSV and μbumps technology is the key to mass production

From the technical information disclosed by Intel, it can be seen that Foveros itself is a 3D IC technology. Through the Through-Silicon Via (TSV) technology and micro-bumps (micro-bumps), different logic chips are connected. stack up.

Its architectural concept is to stack other computing dies (die) and microchips (chiplets), such as GPU and memory, even in the form of TSV plus micro-bumps, on a basic computing chiplet (compute chiplet). It is RF components, etc., and finally the entire structure is packaged and packaged.

The current process used by Intel has reached 10 nanometers, and it is expected to be able to smoothly advance to 7 nanometers. Through this 3D packaging technology, it will be able to achieve excellent computing performance in a single chip and continue to advance Moore's Law.

Intel specifically calls this technology "Face-to-Face" packaging, emphasizing the characteristics of its chip-to-chip packaging. To achieve this technology, advanced process technology of TSV and micro bumps (μbumps) is the key, especially the pitch of bump contacts is only about 36 microns (micron), how to achieve this through excellent wire bonding process , it is a very test of Intel's production technology.

Figure 6: Foveros TSV and micro-bump overlay schematic (source: intel)

But Intel also pointed out that there are still three challenges in Foveros technology, namely heat dissipation, power supply, and yield. Due to the stacking of multiple chips, the heat source density is bound to be greatly increased; and the power supply performance of the upper and lower logic chips will also be challenged; how to overcome the above problems and mass production and supply at a reasonable cost is the last a hurdle.

According to Intel's previously announced schedule, the "Lakefield" processor should be launched later this year, but since Intel has not updated the progress of this product in COMPUTEX, it remains to be seen whether it can be launched smoothly.