Serial Peripheral Interface (SPI) is one of the most widely used interfaces between microcontrollers and peripheral ICs such as sensors, ADCs, DACs, shift registers, SRAMs, etc. This article begins with a brief description of the SPI interface, and then describes Analog Devices' SPI-enabled analog switches and multiplexers, and how they can help reduce the number of digital GPIOs in system board designs.

SPI is a synchronous, full-duplex, master-slave interface. Data from the master or slave is synchronized on the rising or falling edge of the clock. The master and slave can transmit data at the same time. The SPI interface can be 3-wire or 4-wire. This article focuses on the commonly used 4-wire SPI interface.

Figure 1. SPI configuration with master and slave

4-wire SPI devices have four signals:

► Clock (SPI CLK, SCLK)
► Chip Select (CS)
► Master output, Slave input (MOSI)
► Master input, slave output (MISO)

The device that generates the clock signal is called the master. The data transferred between the master and the slave is synchronized with the clock generated by the master. Compared to the I2C interface, SPI devices support higher clock frequencies. Users should consult the product data sheet for clock frequency specifications for the SPI interface.

The SPI interface can only have one master, but can have one or more slaves. Figure 1 shows the SPI connection between the master and slave.

The chip select signal from the master is used to select the slave. This is usually an active low signal, when pulled high the slave is disconnected from the SPI bus. When using multiple slaves, the master needs to provide a separate chip select signal for each slave. The chip select signal in this article is always an active low signal.

MOSI and MISO are data lines. MOSI sends data from master to slave and MISO sends data from slave to master.

data transmission

To start SPI communication, the master must send a clock signal and select the slave by enabling the CS signal. Chip select is usually an active low signal. Therefore, the master must send a logic 0 on this signal to select the slave. SPI is a full-duplex interface, and the master and slave can send data simultaneously through the MOSI and MISO lines, respectively. During SPI communication, data is sent (serially shifted out onto the MOSI/SDO bus) and received (sampled or read into the data on the bus (MISO/SDI)) simultaneously. The serial clock edge synchronizes the shifting and sampling of data. The SPI interface allows the user the flexibility to select the rising or falling edge of the clock to sample and/or shift data. To determine the number of data bits transferred using the SPI interface, refer to the device data sheet.

Clock Polarity and Clock Phase

In SPI, the master can choose the clock polarity and clock phase. During the idle state, the CPOL bit sets the polarity of the clock signal. The idle state refers to a period during which CS is high and transitions to a low level at the beginning of the transmission, and a period when CS is low and transitions to a high level at the end of the transmission. The CPHA bit selects the clock phase. Depending on the state of the CPHA bit, the rising or falling edge of the clock is used to sample and/or shift the data. The master must select the clock polarity and clock phase according to the requirements of the slave. There are four SPI modes available depending on the selection of the CPOL and CPHA bits. Table 1 shows the 4 SPI modes.

Table 1. SPI Mode Selection via CPOL and CPHA

Figure 2 to Figure 5 show examples of communication in the four SPI modes. In these examples, the data is displayed on the MOSI and MISO lines. The start and end of the transfer are indicated by green dashed lines, sampling edges are indicated by orange dotted lines, and shifted edges are indicated by blue dotted lines. Note that these graphics are for reference only. For successful SPI communication, the user must consult the product data sheet and ensure that the device's timing specifications are met.

Figure 2. SPI Mode 0, CPOL = 0, CPHA = 0: CLK idle = low, data is sampled on rising edge and shifted out on falling edge.

Figure 3. SPI Mode 1, CPOL = 0, CPHA = 1: CLK idle state = low, data is sampled on falling edge and shifted out on rising edge.

Figure 4. SPI Mode 2, CPOL = 1, CPHA = 1: CLK idle state = high, data is sampled on falling edge and shifted out on rising edge.

Figure 5. SPI Mode 3, CPOL = 1, CPHA = 0: CLK idle state = high, data is sampled on rising edge and shifted out on falling edge.

Figure 3 shows the timing diagram for SPI Mode 1. In this mode, the clock polarity is 0, indicating that the idle state of the clock signal is low. The clock phase in this mode is 1, meaning that data is sampled on the falling edge (shown by the orange dotted line) and data is shifted out on the rising edge of the clock signal (shown by the blue dotted line).

Figure 4 shows the timing diagram for SPI Mode 2. In this mode, the clock polarity is 1, indicating that the idle state of the clock signal is high. The clock phase in this mode is 1, meaning that data is sampled on the falling edge (shown by the orange dotted line) and data is shifted out on the rising edge of the clock signal (shown by the blue dotted line).

Figure 5 shows the timing diagram for SPI Mode 3. In this mode, the clock polarity is 1, indicating that the idle state of the clock signal is high. The clock phase in this mode is 0, meaning that data is sampled on the rising edge (shown by the orange dotted line) and data is shifted out on the falling edge of the clock signal (shown by the blue dotted line).

Multi-slave configuration

Multiple slaves can be used with a single SPI master. Slaves can be connected in regular mode, or in daisy-chain mode.

Figure 6. Multi-Slave SPI Configuration

Regular SPI Mode In regular mode, the master needs to provide a separate chip select signal for each slave. Once the master enables (pulls low) the chip select signal, the clock and data on the MOSI/MISO lines are available to the selected slave. If multiple chip selects are enabled, the data on the MISO line will be corrupted because the master cannot identify which slave is transmitting data.

As can be seen from Figure 6, as the number of slaves increases, the number of chip select lines from the master also increases. This quickly increases the number of inputs and outputs the master needs to provide and limits the number of slaves that can be used. Other techniques can be used to increase the number of slaves in regular mode, such as using a multiplexer to generate a chip select signal.

Daisy Chain Mode

Figure 7. Multi-Slave SPI Daisy Chain Configuration

In daisy-chain mode, the chip select signals of all slaves are connected together and data is propagated from one slave to the next. In this configuration, all slaves receive the same SPI clock at the same time. Data from the master goes directly to the first slave, which feeds the data to the next slave, and so on.

With this method, since data is propagated from one slave to the next, the number of clock cycles required to transfer data is proportional to the position of the slaves in the daisy chain. For example, in the 8-bit system shown in Figure 7, 24 clock pulses are required to enable the third slave to obtain data, while only 8 clock pulses are required in conventional SPI mode. Figure 8 shows the clock cycles and data propagation through the daisy chain. Not all SPI devices support daisy-chain mode. Please refer to the product data sheet to confirm if daisy chaining is available.

Figure 8. Daisy-chain configuration: data propagation

Analog Devices' SPI-Enabled Analog Switches and Multiplexers

The latest generation of SPI-enabled switches from Analog Devices offers significant space savings without compromising precision switching performance. This part of the article will discuss a case study of how an SPI-enabled switch or multiplexer can greatly simplify system-level design and reduce the number of GPIOs required.

The ADG1412 is a quad, single-pole, single-throw (SPST) switch that requires four GPIOs connected to the control inputs of each switch. Figure 9 shows the connection between the microcontroller and an ADG1412.

Figure 9. Microcontroller GPIOs are used as control signals for switches.
, As the number of switches on the board increases, the number of GPIOs required will also increase significantly. For example, when designing a test instrumentation system, numerous switches are used to increase the number of channels in the system. In a 4x4 crosspoint matrix configuration, four ADG1412s are used. This system requires 16 GPIOs, limiting the GPIOs available in standard microcontrollers. Figure 10 shows four ADG1412s connected using the microcontroller's 16 GPIOs.

One way to reduce the GPIO count is to use a serial-to-parallel converter, as shown in Figure 11. The parallel signals output by the device can be connected to switch control inputs, and the device can be configured through the serial interface SPI. The downside of this approach is that adding extra components increases the bill of materials.

Another way is to use SPI controlled switches. The advantage of this approach is that it reduces the number of GPIOs required and also eliminates the overhead of an external serial-to-parallel converter. As shown in Figure 12, instead of 16 microcontroller GPIOs, only 7 microcontroller GPIOs are required to provide SPI signals to 4 ADGS1412s.

The switches can be daisy-chained to further optimize the number of GPIOs. In a daisy-chain configuration, no matter how many switches the system uses, only the four GPIOs of the host (microcontroller) are used.

Figure 10. In a multi-slave configuration, the number of GPIOs required increases dramatically.

Figure 11. Multi-Slave Switch Using Serial-to-Parallel Converter

Figure 12. SPI-enabled switch saves microcontroller GPIO

Figure 13. SPI switches in a daisy-chain configuration further optimize GPIO.

Figure 13 is for illustration purposes. The ADGS1412 data sheet recommends using a pull-up resistor on the SDO pin. Refer to the ADGS1412 data sheet for more information on daisy-chain mode. For simplicity, this example uses four switches. The advantages of board simplicity and space saving are important as the number of switches in a system increases. ADI's SPI-enabled switches can save 20% of total board space in a 4x8 crosspoint configuration by placing eight quad SPST switches on a 6-layer board.