feature

Signal-to-noise ratio of 78.3 dBFS at 70 MHz and 125 MSPS; SFDR=93 dBc at 70 MHz and 125 ms/s; low power: 371 MW at 125 msps; 1.8V analog supply operation; 1.8V CMOS or LVDS output supply; Integer 1 to 8 input clock divider; 200 Ω input impedance at 70 MHz and 125 MSPS if sampling frequency reaches 300 MHz - 153.4 dBm/Hz small signal input noise; selectable on-chip dithering; programmable internal ADC voltage reference integrated ADC sample and hold input; flexible analog input range: 1 V pp to 2 V pp; differential analog input with 650 MHz bandwidth; ADC clock duty cycle stabilizer; serial port control; user-configurable built-in self-test (BIST ) function energy saving power down mode.

application

Communications; Multimode Digital Receivers (3G); GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA; Smart Antenna Systems; Universal Software Radio; Ultrasound Equipment for Broadband Data Applications.

Product Highlights

1. On-chip dithering option to improve SFDR performance of low-power analog inputs.

2. Proprietary differential input, maintains good signal-to-noise performance at input frequencies up to 300 MHz.

3. Operation of a 1.8V power supply and a separate digital output driver power supply that can accommodate 1.8V CMOS or LVDS outputs.

4. Standard Serial Port Interface (SPI) that supports various product features and functions, such as data formatting (offset binary, duplex or gray coding), enabling clock DCS, power down, test mode and voltage reference mode .

5. It is pin compatible with AD9265, allowing simple migration of up to 16 bits.

General Instructions

The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter (ADC). The AD9255 is designed to support communications applications that combine high performance, low cost, small size, and versatility.

The ADC core adopts a multi-stage differential pipeline structure, integrates output error correction logic, provides 14-bit accuracy at a data rate of 125 MSPS, and guarantees no missing codes over the entire operating temperature range.

The ADC has a wide bandwidth differential sample and hold analog input amplifier that supports a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in continuous channels, as well as sampling single-channel inputs at frequencies well beyond the Nyquist rate. Compared to previously available ADCs, the AD9255 offers power and cost savings for applications in communications, instrumentation, and medical imaging.

The differential clock input controls all internal conversion cycles. The duty cycle stabilizer provides a means of compensating for variations in the duty cycle of the ADC clock, allowing the converter to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference simplifies design considerations.

The ADC output data format is parallel 1.8V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing of the receive logic.

Programming for setup and control is done using a 3-wire SPI-compatible serial interface. Flexible power-down options provide significant energy savings when needed. An optional onchip dithering function can be used to improve the SFDR performance of low-power analog input signals.

The AD9255 is available in a lead-free, 48-lead LFCSP and is specified over the industrial temperature range of -40°C to +85°C.

Typical performance characteristics

AVDD=1.8 V, DRVDD=1.8 V, SVDD=1.8 V, sample rate=125 MSPS, DCS enabled, 1.0 V internal reference, 2 V pp differential input, VIN=-1.0 dBFS, and 32k samples, TA=25°C ,Unless otherwise indicated.

Equivalent Circuit

theory of operation

Using the AD9255, the user can use appropriate low-pass or band-pass filtering at the ADC input to sample any fS/2 frequency band from dc to 200mhz with little loss of ADC performance. Operation on the 300 MHz analog input is allowed, but at the expense of increased ADC noise and distortion. Synchronization is provided to allow synchronized timing between multiple devices.

Programming and control of the AD9255 is done using a 3-wire SPI compatible serial interface.

ADC Architecture

The AD9255 architecture consists of a front-end sample-and-hold input network and a pipelined switched-capacitor ADC. In the digital correction logic, the quantized outputs from each stage are combined into a final 14-bit result. The pipelined architecture allows the first stage to operate on new input samples and the remaining stages to operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched-capacitor digital-to-analog converter (DAC) and an interstage residual amplifier. The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage can be AC or DC coupled in differential or single-ended mode. The output scratch block aligns the data, corrects errors, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

Analog Input Considerations

The analog input to the AD9255 is a differential switched capacitor network designed for optimum performance when processing differential input signals.

The clock signal alternates between sample and hold modes (see Figure 64). When the input switches to sampling mode, the signal source must be able to charge the sampling capacitor and settle within 1/2 of the clock period.

Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. A parallel capacitor can be placed at the input to provide dynamic charging current. This passive network creates a low-pass filter at the ADC input; therefore, the exact value depends on the application.

In IF undersampling applications, any parallel capacitors should be reduced. Combined with the drive source impedance, the shunt capacitor limits the input bandwidth. Refer to AN-742 Application Note, Frequency Domain Response of Switched Capacitor ADCs; AN-827 Application Note, Resonance Methods for Interfacing Amplifiers to Switched Capacitor ADCs; and the Analog Dialogue article, "Transformer-Coupled Front Ends for Wideband A/D Converters."

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched and the inputs should be differentially balanced.

An internal differential reference buffer generates positive and negative reference voltages that define the input range of the ADC core. This buffer sets the span of the ADC core to 2×VREF.

Input common mode

The analog inputs of the AD9255 have no internal dc bias. In AC-coupled applications, the user must provide this bias externally. Set the device to VCM=0.5×AVDD for best performance, but the device has a wider range of functions and reasonable performance (see Figure 52). An on-board common-mode voltage reference is included in the design, available from the VCM pin. Best performance is obtained when the common-mode voltage of the analog inputs is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be separated from ground by a 0.1µF capacitor, as described in the Applications Information section.

jitter

The AD9255 has a selectable dithering mode with the option of using the dither pins or using the SPI bus. Dithering is the act of injecting a known but random amount of white noise (often called dithering) into the input of an ADC. Dithering has the effect of improving the local linearity of the ADC transfer function at various points. Dithering can significantly improve SFDR when quantizing small-signal inputs, typically at input levels below -6dbfs.

As shown in Figure 65, the jitter added to the ADC input by the dither DAC is precisely digitally subtracted to minimize SNR degradation. When dithering is enabled, the dithering DAC is driven by a pseudo-random number generator (PN-gen). In the AD9255, the dither DAC is precisely calibrated to cause only very little degradation in SNR and SINAD. With dither enabled, typical SNR and SINAD attenuation values are only 1db and 0.8db, respectively.

Large Signal FFT

In most cases, dithering will not improve SFDR for large signal inputs near full scale, e.g. with -1 dBFS inputs. For large signal inputs, SFDR is usually limited by front-end sampling distortion, and jitter cannot be improved. However, even for such large signal inputs, dithering may be useful for some applications because it makes the noise floor whiter. As is often the case in pipelined ADCs, the AD9255 contains small DNL errors caused by random component mismatches that produce pops or tones that randomly color parts of the noise floor. While these tones are typically at very low levels and do not limit SFDR when the ADC quantizes large signal inputs, dithering converts these tones into noise and produces a whiter noise floor.

Small Signal FFT

For small-signal inputs, the front-end sampling circuit typically contributes very little distortion, so SFDR is likely to be limited by tones due to DNL errors due to random component mismatches. So for small signal inputs (typically below -6dbfs) dithering can significantly improve SFDR by converting these DNL tones to white noise.

static linearity

Dithering also removes sharp local discontinuities in the ADC's INL transfer function and reduces the overall peak-to-peak INL.

In receiver applications, utilizing dither can help reduce DNL errors that contribute to small-signal gain errors. Typically, this problem is overcome by setting the input noise 5dB to 10dB above the converter noise. Correcting DNL errors with dither inside the converter reduces input noise requirements.

Differential Input Configuration

Best performance is obtained when driving the AD9255 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and flexible interface to ADCs.

The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9255 (see Figure 66), and the driver can be configured in the filter topology shown to provide band limiting of the input signal.

For baseband applications where signal-to-noise ratio is a critical parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 67. To bias the analog input, the VCM voltage can be connected to the center tap of the transformer secondary winding.

Signal characteristics must be considered when selecting a transformer. Most RF transformers have saturation frequencies below a few megahertz (MHz). Excessive signal power can also cause the core to saturate, resulting in distortion.

At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is insufficient to achieve the true SNR performance of the AD9255. For applications where signal-to-noise ratio is a critical parameter, differential double balun coupling is recommended (see Figure 68). In this configuration, the inputs are AC coupled, and CML is provided to each input through 33Ω resistors. These resistors compensate for losses in the input balun, providing a 50Ω impedance to the driver.

In dual balun and transformer configurations, the values of the input capacitors and resistors depend on the input frequency and source impedance and may need to be reduced or removed. Table 10 shows suggested values for setting up the RC network. However, these values are dependent on the input signal and should only be used as a start-up guide.

An alternative to using transformer-coupled inputs at the second Nyquist zone and higher is to use the ADL5562 differential driver. The ADL5562 offers three selectable gain options up to 15.5 dB. An example circuit is shown in Figure 69; additional filtering between the ADL5562 output and the AD9255 input may be required to reduce out-of-band noise. See the ADL5562 data sheet for more information.

voltage reference

A stable and accurate voltage reference is built into the AD9255. The input range can be adjusted by changing the reference voltage applied to the AD9255, using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage. The following sections summarize the various reference modes. The Reference Decoupling section describes the reference best practice PCB layout.

Internal reference connection

The comparator within the AD9255 senses the potential at the sense pin and configures the reference into four possible modes, as shown in Table 11. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 70) to set VREF to 1.0 V for the 2.0 V pp full-scale input. In this mode, the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of Register 0x18 with the sensor grounded. These bits can be used to change the full scale to 1.25 V pp, 1.5 V pp, 1.75 V pp, or the default value of 2.0 V pp, as shown in Table 17.

Connect the sense pin to the VREF pin, switch the reference amplifier output to the sense pin, complete the loop, and provide a 0.5 V reference output for a 1 V pp full-scale input.

As shown in Figure 71, if the resistor divider is connected outside the chip, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

If the AD9255's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows the effect of load on the internal reference voltage.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0V mode.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 55). Internal buffers generate positive and negative full-scale references for the ADC core. Therefore, the external reference voltage must be limited to 1.0V maximum.

Clock Input Considerations

For best performance, the AD9255 sample clock inputs (CLK+ and CLK-) should be clocked with differential signals. Signals are typically AC coupled to the CLK+ and CLK- pins through transformers or capacitors. These pins are internally biased (see Figure 74) and do not require external biasing.

Clock input options

The AD9255 has a very flexible clock input structure. The clock input can be CMOS, LVDS, LVPECL, or a sine wave signal. Regardless of the type of signal used, clock source jitter is of greatest concern, as described in the Jitter Considerations section.

Figure 75 and Figure 76 show the two preferred methods for timing the AD9255. Use an RF transformer or RF balun to convert a low-jitter clock source from a single-ended signal to a differential signal.

For clock frequencies of 625 MHz, an RF balun configuration is recommended; for clock frequencies from 10 MHz to 200 MHz, an RF transformer is recommended. Back-to-back Schottky diodes on the secondary side of the transformer/balun limit the clock skew of the AD9255 to approximately 0.8V pp differential.

This limit helps prevent large voltage fluctuations of the clock from being fed through other parts of the AD9255, while maintaining fast rise and fall times for signals that are critical for low jitter performance.

If a low-jitter clock source is not available, another option is to AC-couple the differential PECL signal to the sampling clock input pins, as shown in Figure 77. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/AD9522 clock drivers provide excellent jitter performance.

A third option is to AC couple the differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/AD9522 clock drivers provide excellent jitter performance. In some applications, it is acceptable to drive the sampling clock input with a single-ended CMOS signal. In this application, drive the CLK+ pin directly from the CMOS gate and use a 0.1µF capacitor to bypass the CLK- pin to ground (see Figure 79).

clock duty cycle

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a ±5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9255 contains a duty cycle stabilizer (DCS) that retimes the non-sampling (falling) edges to provide an internal clock signal with a 50% nominal duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9255. With DCS enabled, the noise and distortion performance is nearly flat over a wide range of duty cycles. Jitter on the rising edge of the input is still the most important issue and is not easily reduced by the internal stabilization circuit.

The duty cycle control loop is generally not suitable for clock frequencies less than 20 MHz. In applications where the clock rate can vary dynamically, the time constant associated with the loop must be considered. After the dynamic clock frequency is increased or decreased, a wait time of 1.5 microseconds to 5 microseconds is required before the DCS loop relocks to the input signal. During the period when the loop is not locked, the DCS loop is bypassed and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In some cases, when using the input clock divider circuit, DCS can also be disabled, see the input clock divider section for more information. In all other applications, it is recommended to enable the DCS circuit to maximize AC performance.

When operating in external pin mode, enable DCS by setting the SDIO/DCS pin high (see Table 12). If SPI mode is enabled, DCS is enabled by default and can be disabled by writing 0x00 to address 0x09.

input clock divider

The AD9255 includes an input clock divider capable of dividing the input clock by an integer value between 2 and 8. For divider ratios of 2, 4, 6 or 8, no duty cycle stabilizer (DCS) is required because the output of the divider inherently produces a 50% duty cycle. Enabling DCS with clock divider in these divider modes may result in a slight decrease in SNR, so it is recommended to disable DCS. For other divide ratios, divide by 3, divide by 5, and divide by 7, the duty cycle of the clock divider output is related to the duty cycle of the input clock. In these modes, if the input clock has a 50% duty cycle, DCS is no longer required. However, if the 50% duty cycle input clock is not available, the DCS must be enabled for proper part operation.

To synchronize the AD9255 clock divider, use an external synchronization signal applied to the synchronization pins. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after a register write. A valid signal at the sync pin resets the clock divider to its initial state. This synchronization feature allows alignment of clock dividers in multiple sections to ensure simultaneous input sampling. If the sync pin is not used, it should be tied to AGND.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (fINPUT), the signal-to-noise ratio drop in low-frequency signal-to-noise ratio (SNRLF) due to jitter (tJRMS) can be obtained by:

In this equation, rms aperture jitter represents the clock input jitter specification. If the undersampling application is particularly sensitive to jitter, as shown in Figure 80.

Treat the clock input as an analog signal where aperture jitter can affect the dynamic range of the AD9255. To avoid modulating the clock signal with digital noise, separate the power supply of the clock driver from the power supply of the ADC output driver. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), the output clock should be retimed by the original clock in the last step. Refer to AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and AN-756 Application Note, Sampling System and Effects of Clock Phase Noise and Jitter (see ) for more information on ADC jitter performance.

Power Consumption and Standby Modes

As shown in Figure 81, the power consumption of the AD9255 is proportional to its sampling rate. In CMOS output mode, the digital power consumption depends primarily on the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be approximately calculated as:

where N is the number of output bits (14 output bits plus one DCO).

This maximum current occurs when each output bit toggles on every clock cycle, i.e. a full-scale square wave at the Nyquist frequency of fCLK/2. In practical applications, the DRVDD current is determined by the switching quantity of the average output bits, which is determined by the sampling rate and the characteristics of the analog input signal.

Reducing the capacitive loading of the output driver can minimize digital power consumption. The data in Figure 81, Figure 82, and Figure 83 were acquired using a 70 MHz analog input signal with a 5 pF load on each output driver.

By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9255 is placed in power-down mode. In this state, the ADC typically dissipates 0.05mW. During power down, the output drivers are in a high impedance state; asserting the PDWN pin low returns the AD9255 to its normal operating mode.

Low power consumption in shutdown mode is achieved by turning off the reference, reference buffer, bias network and clock. Internal capacitors are discharged when entering power-down mode and must then be recharged when normal operation is resumed.

When using the SPI port interface, the user can place the ADC in power-down or standby mode. Standby mode allows the user to keep the internal reference circuit powered up when a faster wake-up time is required. Additionally, when using SPI mode, the user can change the function of the external PDWN pin to put the part in power-down or standby mode. See the Memory Mapped Register Descriptions section for more details.

digital output

The AD9255 output driver can be configured to interface with 1.8V CMOS logic families. The AD9255 can also be configured as an LVDS output using a DRVDD supply voltage of 1.8V. The AD9255 defaults to CMOS output mode, but can be put into LVDS mode by setting the LVDS pin high or by using the SPI port to put the part into LVDS mode. Since most users do not switch between CMOS and LVDS modes during operation, it is recommended to use LVDS pins to avoid output power-up loading issues for CMOS configurations.

In CMOS output mode, the output drivers are sized to provide enough output current to drive various logic families. However, large drive currents tend to cause current glitches on the power supply, which can affect the performance of the converter. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches. In LVDS output mode, two output driver levels can be selected, ANSI LVDS or reduced swing LVDS mode. Using reduced swing LVDS mode reduces DRVDD current and reduces power consumption. The reduced swing LVDS mode can be selected by asserting the LVDS pin or by selecting the mode through the SPI port.

When operating in external pin mode, select the output data format for offset binary or duplex complement by setting the SCLK/DFS pins (see Table 12).

As described in the AN-877 application note, interfacing with high-speed ADCs via SPI, when using SPI control, the data format can be selected for offset binary, two's complement, or gray code.

Digital output enable function (OEB)

The AD9255 has flexible tri-state capability for digital output pins. Tri-state mode is enabled using the OEB pin or via the SPI interface. If the OEB pin is low, the output data driver and dco are enabled. If the OEB pin is high, the output data driver and dco are in a high impedance state. This OEB function is not intended for fast access to the data bus. Note that OEB refers to the digital output driver supply (DRVDD) and should not exceed this supply voltage.

When using the SPI interface, data and DCO outputs can be asserted three times by using the output enable bar bits in Register 0x14.

opportunity

The AD9255 provides latched data with a pipeline delay of 12 clock cycles (12.5 clock cycles in LVDS mode). The data output is available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length and loading of the output data lines to reduce transients within the AD9255. These transients degrade the dynamic performance of the converter. The minimum typical conversion rate of the AD9255 is 10 msec/sec. Dynamic performance degrades when the clock rate is lower than 10ms/sec.

Data Clock Out (DCO)

The AD9255 provides a single data clock output (DCO) pin in CMOS output mode and two differential data clock output (DCO) pins in LVDS mode for capturing data in external registers. In CMOS output mode, the data output is valid on the rising edge of the DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, data is output at a double data rate, with odd-numbered output bits transitioning near the rising edge of DCO, and even-numbered output bits transitioning near the falling edge of DCO. See Figure 2 for a graphical timing description.

Built-in Self-Test (BIST) and Output Test

The AD9255 includes a built-in self-test function designed to verify the integrity of the part and facilitate board-level debugging. A built-in self-test (BIST) function is included to verify the integrity of the AD9255's digital datapath. Various output test options are also provided to place predictable values on the outputs of the AD9255.

Built-in Self-Test (BIST)

BIST is a thorough test of the digital portion of the selected AD9255 signal path. When enabled, the test is run from an internal pseudorandom noise (PN) source through the digital datapath starting from the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value is placed in Register 0x24 and Register 0x25. During this test, the output is not disconnected, so the PN sequence can be observed at runtime. The PN sequence can be either continued from its last value or reset from the beginning according to the value programmed in Register 0x0E, Bit 2. BIST signature results vary by part configuration.

output test mode

The output test options are shown in Table 17. When the output test mode is enabled, the analog portion of the ADC is disconnected from the digital backend block, and the test mode is run through the output formatting block. Some test patterns are bound by the output format, and some are not bound by the output format. The seed value for the PN sequence test can be forced if the PN reset bit is used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encoded clock. For details, see the AN-877 Application Note, Interfacing with High Speed ADCs via SPI.

Serial Port Interface (SPI)

The AD9255 serial port interface (SPI) allows the user to configure the converter for a specific function or operation through the structured register space provided within the ADC. SPI provides users with additional flexibility and customization, depending on the application. The address is accessed through the serial port and can be written or read through the port. Memory is organized into bytes, which can be further divided into fields, which are recorded in the memory-mapped section. For detailed operational information, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Configuration using SPI

Three pins define the SPI for this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 14). SCLK/DFS (serial clock) is used to synchronize the read and write data of the ADC. SDIO/DCS (Serial Data Input/Output) is a dual purpose pin that allows data to be sent and read from the internal ADC memory mapped registers. CSB (chip select bar) is an active low control that enables or disables read and write cycles.

The falling edge of CSB and the rising edge of SCLK together determine the start of the frame. See Figure 84 and Table 5 for an example of serial timing and its definition. Other modes involving CSB are also available. CSB can be held low indefinitely, which will permanently enable the device; this is called streaming. CSB can be suspended high between bytes to allow for additional external timing. When CSB is tied high at power-up, the SPI function is put into high impedance mode. This mode enables any SPI pin auxiliary functions. When CSB is toggled low after power up, the part will remain in SPI mode and will not revert to pin mode.

In the command phase, a 16-bit command is sent. The data follows the instruction phase and its length is determined by the W0 and W1 bits. All data consists of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether to issue a read or write command. This allows the serial data input/output (SDIO) pins to change the input direction to the output direction.

In addition to word length, the instruction stage determines whether the serial frame is a read or write operation, allowing the serial port to be used to program the chip and read the contents of on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pins to change from input to output at the appropriate point in the serial frame.

Data can be sent in MSB first mode or LSB first mode. MSB first is the default value at power-on and can be changed through the SPI port configuration registers. For more information on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

hardware interface

The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9255. When using the SPI interface, the SCLK pin and the CSB pin are used as inputs. The SDIO pins are bidirectional and act as inputs during the write phase and as outputs during readback.

The AD9255 has a separate power supply pin, SVDD, for the SPI interface. The SVDD pin can be set to any level between 1.8 V and 3.3 V for operation with the SPI bus at these voltages without the need for level shifting. If the SPI port is not used, SVDD can be tied to the DRVDD voltage.

The SPI interface is flexible enough to be controlled by FPGAs or microcontrollers. One SPI configuration method is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9255 to prevent these signals from transitioning at the converter input during critical sampling. Some pins have dual functions when the SPI interface is not used. During device power-up, when pins are tied to AVDD or ground, they are associated with a specific function. The Digital Outputs section describes the alternate functions supported by the AD9255.

Configuration without SPI

In applications that do not interface with the SPI control registers, the SDIO/DCS pins and the SCLK/DFS pins are used as separate CMOS compatible control pins. When the device is powered up, it is assumed that the user intends to use the pin as a static control line for duty cycle stabilizer and output data format characteristic control. In this mode, connect the CSB chip select to AVDD, which disables the serial port interface.

OEB pins, dither pins, LVDS pins, LVDS pins, and PDWN pins are active control lines in both external pin mode and SPI mode. Inputs to these pins or SPI register settings (logical OR of SPI bits and pin functions) are used to determine the part's operating mode.

SPI accessible functions

Table 16 briefly describes the general features accessible through the SPI. These features are described in detail in the AN-877 application note, which interfaces to high-speed ADCs via SPI. Part-specific features of the AD9255 are described in detail under Table 17 (External Memory Mapped Register Table).

memory map

Read Memory Mapped Register Table

Each row in the memory-mapped register table has eight bit positions. The memory map is roughly divided into four parts: chip configuration registers (address 0x00 to address 0x02); transfer registers (address 0xFF); ADC function registers, including setup, control and test (address 0x08 to address 0x30); digital feature control registers ( address 0x100).

The memory-mapped register table records the default hex value for each hex address shown. The column titled bit 7 (MSB) is the start of the given default hex value. For example, address 0x18 (the VREF select register) has a default hex value of 0xC0. This means that bit 7=1, bit 6=1, and the remaining bits are 0. This setting is the default reference selection setting. Default uses 2.0 V pp reference. For details on this and other features, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x30. The remaining registers at register 0x100 are documented in the Memory Mapped Register Descriptions section.

open location

Unused bits in valid address locations should be written with 0. These locations only need to be written if part of the address location is open (for example, address 0x18). If the entire address location is open (for example, address 0x13), this address location should not be written.

Defaults

After the AD9255 is reset, the key registers are loaded with default values.

logic level

Logic level terms are explained as follows:

• "Bit is set" is synonymous with "Bit is set to Logic 1", or "A logic 1 is being programmed for a bit."

• "Clear a bit" is synonymous with "bit is set to Logic 0", or "A logic 0 is being written to the bit."

transfer register map

Address 0x08 to address 0x18 are hidden. Writing to these addresses does not affect part of the operation until a transfer command is issued by writing 0x01 to address 0xFF and setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. Internal updates occur when the transfer bit is set and the bit is automatically cleared.

Memory Mapped Register Description

For more information on the functions of Register 0x00 controls to Register 0xFF, see the AN-877 Application Note, Connecting to High Speed ADCs via SPI.

Synchronization Control (Register 0x100)

Bits[7:3] - reserved

These bits are reserved.

Bit 2 clock divider, next sync only

If the Master Sync Enable bit (Address 0x100, Bit 0) and the Clock Divider Sync Enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and ignore the rest . The clock divider synchronization enable bit (Address 0x100, Bit 1) resets after synchronization.

Bit 1 Clock Splitter Sync Enable

Bit 1 gates the sync pulse to the clock divider. When bit 1 is high and bit 0 is high, the sync signal is enabled. This is continuous sync mode.

Bit 0 Master Sync Enable

Bit 0 must be high to enable any synchronization functions. If synchronization is not used, this bit should be kept low to save power.

application information

Design Guidelines

Before beginning to design and lay out the AD9255 as a system, designers are advised to familiarize themselves with these guidelines, which discuss the special circuit connections and layout requirements required for certain pins.

Power and Grounding Recommendations

When connecting power supplies to the AD9255, two separate 1.8 V supplies are recommended. Use one analog supply (AVDD); use a separate digital output supply (DRVDD). Several different decoupling capacitors are available to cover high and low frequencies. Place these capacitors close to PCB layer entry points and close to part pins with minimal trace lengths. The power supply to the SPI port SVDD should not contain excessive noise and should also be bypassed near the part.

When using the AD9255, a single PCB ground plane should be sufficient. Optimum performance is easily achieved with proper decoupling and intelligent partitioning of the analog, digital and clock sections of the PCB.

LVDS operation

The AD9255 can be configured for CMOS or LVDS output mode at power-up using LVDS pin 44. If LVDS operation is required, connect pin 44 to AVDD. LVDS operation can also be enabled through the SPI port. If CMOS operation is required, connect pin 44 to AGND.

Exposed Blade Hot Slug Recommendations

For best electrical and thermal performance, the exposed switch on the bottom of the ADC must be connected to analog ground (AGND). A continuous, exposed (no solder mask) copper plane on the PCB should match the exposed paddle (pin 0) of the AD9255. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation through the bottom of the PCB. Fill or plug these vias with non-conductive epoxy.

To maximize coverage and adhesion between the ADC and the PCB, overlay a silkscreen to divide the continuous plane on the PCB into several uniform sections. This provides several connection points between the ADC and the PCB during reflow. Using a continuous plane with no partitions ensures that there is only one connection point between the ADC and the PCB. For more information on packaging and PCB layout for chip scale packages, see AN-772 Application Note, Design and Manufacturing Guidelines for Lead Frame Chip Scale Packages (LFCSPs), available at .

VCM

Separate the VCM pin from ground with a 0.1µF capacitor, as shown in Figure 67.

Indian Rupee

The AD9255 requires a 10 kΩ resistor to be placed between the RBIAS pin and ground. This resistor sets the primary current reference for the ADC core and should have a tolerance of at least 1%.

Reference decoupling

Connect the VREF pin externally to ground with a low ESR, 1.0µF capacitor in parallel with a low ESR, 0.1µF ceramic capacitor.

SPI port

The SPI port should not be active during periods when full dynamic performance of the converter is required. Since the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise on these signals can degrade converter performance. If the onboard SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9255 to prevent these signals from transitioning at the converter input during critical sampling.

Dimensions