feature

●pin compatible with ADC7802 and ADS7803

●Single power supply: +5V or +3.3V

●Low power: 14mW plus power off

●Signal to noise ratio at temperature: 69dB minimum, fIN = 1kHz; 66dB minimum, fIN = 50kHz

Fast conversion time: 8.5 microseconds; includes acquisition (117kHz sampling price); four-channel input multiplexer

● Automatic calibration: no offset or gain adjustment required

illustrate

The ADS7832 is a monolithic CMOS 12-bit analog-to-digital converter with internal sample/hold and quad multiplexer. It has been thoroughly designed and tested for dynamic performance with an input signal of 50kHz. A single 5V supply requirement and standard CS, RD and WR control signals make the part easy to use in microprocessor applications. The result of the conversion is a two-byte output bus with 8-bit 3-state.

The ADS7832 has a 28-pin plastic dip and 28-lead PLCC and is fully specified for the industrial –40°C to +85°C temperature range.

theory of operation

The ADS7832 takes advantage of advanced CMOS technology (logic density, stable capacitance, accurate analog switching, and low power consumption) to provide an accurate 12-bit analog-to-digital converter with on-chip sampling and a four-channel analog input multiplexer .

The input stage consists of an analog multiplexer and an address latch for selecting from four input channels.

The converter stage consists of an advanced successive approximation structure that uses charge redistribution across a capacitive network to digitize the input signal. In order to reduce the offset error of the comparator, a temperature-stable differential auto-zero circuit is used.

Linearity errors in the binary weighted main capacitor network are corrected using the capacitor trimming network and correction factors stored in on-chip memory. Correction terms are calculated by the on-chip microcontroller during a calibration cycle that is initiated by power-up or the application of an external calibration signal at any time. During the conversion process, the correct trimmer capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. All capacitors in the main and trim arrays are located on the same chip, resulting in excellent stability both over temperature and over time.

For flexibility, sequential circuits include an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and tri-state input/output registers simplify interfacing the ADS7832 with most microcontrollers, microprocessors, or digital storage systems.

On-chip sampling provides excellent dynamic performance for a 50 kHz input signal with a full power 3dB bandwidth of 4MHz. In critical applications, the sample-and-hold time can be fully controlled.

Finally, this performance is matched by the low-power benefits of the CMOS structure, allowing a typical 10mW power dissipation, with a 50-µW power-down option.

operate

Basic operation

Figure 1 shows the simple circuit required to operate in transparent mode, converting a single input channel. The convert command on pin 20 (WR) initiates the conversion. Pin 22 (busy) will go up during the conversion process (including sample acquisition and conversion), after the conversion is complete. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE).

start conversion

Conversion begins on the rising edge of the WR input, with valid signals on A0, A1, and CS. The selected input channel is sampled for five clock cycles. Continued Figure 1. Basic operation.

The approximate transition occurs between clock cycles 6 and 17. Figures 2 and 3 show the complete conversion sequence and the time to initiate a conversion.

A conversion can also be initiated by a rising edge on pin 26 if D2 of the Special Function Register has been written high, as described below.

calibration

The calibration cycle starts automatically after power-up (or power-down). The user can also start calibration at any time with a minimum 100ns rising edge - a wide low pulse on the CALIBRATE pin (pin 26), or by setting D1 high in the Special Function Register (see SFR section). The calibration command will initiate a calibration cycle whether or not a conversion is in progress. During a calibration cycle, conversion commands are ignored.

Calibration takes 4608 clock cycles, and normal conversions (17 clock cycles) are added automatically. Therefore, at the end of the calibration cycle, in the output register. For maximum accuracy, the supply and reference need to be stable during calibration. To ensure that the supply voltage is stable, an internal timer provides a latency of 37393 clock cycles between power up/down and the start of the calibration cycle.

read data

The data of the ADS7832 is read in two 8-bit bytes, where the low byte contains 8 LSB data and the high byte contains 4 MSB data. The output is encoded in straight binary (0V=000 hex, 5V=FFF hex), and the data is displayed in right-justified format (LSB is the rightmost bit in a 16-bit word). Two read operations are required to transfer the high and low bytes, and the bytes are displayed according to the input level on the high byte enable pin (HBE).

Bytes can be read in any order, depending on the state of the HBE input. If HBE changes while CS and RD are low, the output data will change to correspond to the HBE input. Figure 4 shows the timing of reading the low byte first, followed by the high byte.

The ADS7832 offers two modes for reading conversion results. When powered up, the converter is set to transparent mode.

transparent mode

This is the default mode of the ADS7832. The conversion decision register for successive approximation in this mode is latched into the output register as it is generated. Therefore, the high byte (4 MSBs) can be read after the ninth clock cycle (setup, sampling, and autozero of the mux's five clock cycle splitter, followed by four clock cycles of 4MSB decision.) After busy, the full 12-bit data available has gone high, or the internal status flag has gone low (D7 when HBE is high).

Latch output mode

This mode is passed in the SFR with CS and WR LOW and SFR and HBE HIGH. (See the discussion of special functions registered below.) In this mode, data from a conversion is latched into the output buffer only after the conversion is complete, and remains unchanged until the next conversion is complete. The result of this conversion is valid during the next conversion. This allows data to be read even after a new conversion is started to improve system throughput.

Timing Considerations

Table 1 and Figures 3 through 9 show the ADS7832 in various modes of operation. All key parameters are guaranteed over the -40°C to +85°C operating range for ease of system design.

Special Function Registers (SFRs)

There is an internal register that is used to determine additional data related to the ADS7832, or to write additional data converter descriptions.

Table 2 shows that the data in the special function registers will be transferred to the output bus by driving HBE HIGH (SFR high) and starting the read cycle (driving RD and CS LOW and WR HIGH) in the Power Fail flag when the supply voltage drops to 2.7V In the following cases, set SFR. The sign also means that a new calibration has started,

All data written to the SFR has been lost. So the ADS7832 will be in transparent mode again. Write an SFR as low as D5 to reset the power failure flag. An error flag in the Carl SFR sets calibration when an overflow occurs during the following period, which can occur in very noisy systems. It is reset by starting the calibration, and the calibration is completed without overflow.

Table 3 shows how to transfer an instruction to the SFR by driving HBE HIGH (with SFR) high) and initiating a write cycle (driving WR and CS low with RD high). Note that writing to SFR initiates a new conversion.

Power down mode

Writing SFR high to D3 will place the ADS7832 in power down mode. Power consumption is reduced to 50 microwatts, and D3 remains high. Internal clocks and analog circuits are turned off, although output registers and SFRs can still be accessed normally. To exit power-down mode, write a low level to D3 in the SFR, or initiate calibration by sending a low level to the calibration pin or writing a high level to D1. Note that if the supply voltage drops below 3V and then resumes, the calibration will start automatically and the SFR will reset. D3 will be high and the ADS7832 will be in power down mode.

In power-down mode, a pulse on CS and WR will initiate a conversion, then the ADS7832 will resume power-down. Additionally, writing D1 and D3 in the SFR will initiate calibration, perform a single conversion and return to power-down mode within 4625 clock cycles. The exact conversion result will be available in the output register.

The sampling time includes the activation delay from power down to normal operation. No additional time is required, either in power-down mode or when making a conversion in power-down mode.

Sample/Hold Control Mode

When D2 is at SFR high, a rising edge input on pin 26 switches the ADS7832 from sample mode to hold mode with a 5ns aperture delay. This also starts the conversion, which will start within 1.5 CLK cycles.

This mode allows full control over samples to keep timing, which is especially useful when external events trigger sample timing.

In sample/hold control mode, between conversions, pin 26 must be held low for a minimum of 2.5 microseconds to allow accurate acquisition of the input signal. In addition, the offset error will increase in this mode because the autozero of the comparator is not synchronized with the sampling. The minimum offset is achieved by synchronizing the sampled signal to CLK, either internal or external. Ideally, the rising edge of the sampled signal should be delayed by 20ns from the falling edge of CLK. This will keep the offset error around 1LSB.

In sample/hold control mode, a low pulse on WR (CS low) will not initiate a conversion, but the rising edge will be based on the inputs on A0 and A1. When changing channels, at least 2.5 microseconds must complete before pin 26 goes high (to initiate the transition.)

control line

Table 4 shows the ADS7832. The use of standard CS, RD and WR control signals simplifies the use of most microprocessors. At the same time, the availability of the state guarantees flexibility through the SFR and directly on the pins.

Install

input resistance

The ADS7832 has high input impedance (100nA maximum input overtemperature bias current) and low 50pF input capacitance. To ensure conversions are accurate to 12 bits, the analog source must be able to charge 50pF and settle within the first five clock cycles after starting the conversion. During this time, the input is also very sensitive to noise on the analog input as it can be injected into the capacitor array.

In many applications, a simple passive low-pass filter as shown in Figure 10a can be used to improve signal quality. In this case, the source impedance needs to be less than 5kΩ to keep the induced offset error below 1/2LSB and meet the acquisition time of five clock cycles. The values in Figure 10a meet these requirements and will maintain the full power bandwidth of the system. For higher source impedances, a buffer as shown in Figure 10b should be used.

input protection

The input signal range must not exceed ±VREF or VA by more than 0.3V. The analog input is internally fixed on VA. To prevent damage to the ADS7832, the current that can flow into the input must be limited to 20 mA. One way is to use an external resistor in series with the input filter resistor. For example, a 1kΩ input resistance allows overvoltages up to 20V without damage.

reference input

A 10µF tantalum capacitor is recommended between VREF+ and VREF to ensure low source impedance. These capacitors should be placed as close as possible to the ADS7832 to reduce dynamic errors because the reference provides the current package when performing the successive approximation step.

VREF+ must not exceed VA. While VREF+=5V and VREF–=0V specify accuracy, the inverter can operate with VREF+ as low as 4.5V and VREF- as high as 1V.

As long as there is at least a 4.5V difference between VREF+ and VREF-, the absolute value of the error will not change significantly, so the accuracy is typically within ±1LSB. During system design, the supply of the reference source needs to be considered to prevent VREF+ from exceeding (or overshooting) rush) VA, especially when powered. Also, after power-up, if the reference is not stable within 33056 clock cycles, additional calibration cycles may be required.

power supply

The digital and analog power lines to the ADS7832 should be bypassed with 10µF tantalum capacitors as close to the part as possible. Although the ADS7832 has excellent power supply rejection, a linear regulated power supply is recommended even at higher frequencies.

Care should be taken to ensure that the VD does not appear before the VA, otherwise permanent damage to the part may occur. Figure 11 shows a good way to power VA and VD from a clean linear supply, with a 10Ω resistor between VA and VD ensuring that VD comes after VA.

This is also a good way to further isolate the ADS7832 from the digital power supplies in a system where significant switching currents can reduce conversion accuracy.

ground

To maximize the accuracy of the ADS7832, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feedback to the analog ground. The VREF–pin is used as the reference point for the input signal, so it should be connected directly to AGND to reduce potential noise issues.

External Clock Operation

The circuit external source required to drive the ADS7832 clock is shown in Figure 12a. The external clock must provide a maximum of 0.8V for low voltage and a minimum of 3.5V for high voltage, with rise and fall times of no more than 200ns. The duty cycle of this external clock can be at least 200ns wide with both low and high times. In microprocessor applications, it is recommended to synchronize the conversion clock with an external system clock to prevent beat frequency problems.

Note that the electrical spec sheet is based on using an external 2 MHz clock. Typically, the specified clock frequency is kept between 0.5 and 2.4 MHz.

Internal clock operation

Figure 12b shows how to use the internal clock generation circuit. The clock frequency depends only on the resistors, as in "Internal Clock Frequency vs "RCLOCK" in the Typical Performance Curves section. The clock generator can operate between 100kHz and 2MHz. When R = 100kΩ, the clock frequency will nominally be 800kHz The internal clock oscillator may vary by up to 20% per device, with temperature, as shown in the typical performance curves. Therefore, control of transition timing using an external clock source is critical in applications where synchronization is required or converters need to be synchronized .

application

Bipolar Input Range

Figure 13 shows an accurate and simple conversion circuit bipolar ±5V input signal to unipolar 0 to 5V signal converted by ADS7832, using high precision and low cost fully differential amplifier, INA105.

Figure 14 shows the ADS7832 circuit that converts a bipolar ±10V input signal into a unipolar 0 to 5V signal. The accuracy of this circuit will depend on the matching and tracking of the three resistors.

In order for this circuit to achieve full 12-bit accuracy, R2 and R3 need to be adjustable within the appropriate range. First trim the ADS7832 for continuous conversion and apply +9.9927V at the input (+10V–1.5LSB). Adjust R3 until the ADS7832 output switches between codes FFE hex and FFF hex. This makes R3 very close to R1. Then, apply –9.9976V to the input (–10V + 0.5LSB) and adjust R2 until the ADS7832 output switches between 000 hex and 001 hex. At each trim point, the current through the third resistor is nearly zero, so one trim iteration will suffice in most cases. If the selected op amp has a large bias voltage or bias current, or if the +5V reference is inaccurate.

This circuit can also be used to adjust the gain and offset errors due to the components preceding the ADS7832, to match the self-calibration performance provided by the inverter.