feature

AD5280 : 1 channel; AD5282: 2 channels; 256 positions; +10 V to +15 V single supply; ±5.5 V dual supply operation; fixed terminal resistance: 20kΩ, 50kΩ, 200kΩ; Scale preset; programmable reset; operating temperature: -40oC to +85oC; I2C compatible interface.

application

Multimedia, Video and Audio; Communications; Mechanical Potentiometer Replacement; Instrumentation: Gain, Offset Adjustment; Programmable Voltage Sources; Programmable Current Sources; Line Impedance Matching.

General Instructions

The AD5280/AD5282 are single- and dual-channel, 256-bit digitally controlled variable resistors (VRs). These devices perform the same electronic adjustment functions as potentiometers, trimmers or variable resistors. Each VR provides a fully programmable resistance value between the A terminal and the wiper or the B terminal and the wiper. The 20 kΩ, 50 kΩ, or 200 kΩ fixed A-to-B terminal resistors have a 1% channel-to-channel matching tolerance. Both parts have a nominal temperature coefficient of 30 parts per million per degree Celsius (ppm/degree Celsius). Another key feature is that the part can operate to +15 V or ±5 V.

Wiper position programming defaults to mid-scale when the system is powered up. When powered up, the virtual reality wiper position is programmed by an IC-compatible 2-wire serial data interface. The AD5280/AD5282 feature sleep mode programmability. This allows any level of presets at power up and is an expensive EEPROM solution. Both parts have additional programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers and analog switches in their systems.

The AD5280/AD5282 are available in thin, surface mount 14-lead TSSOPs and 16-lead TSSOPs. All parts are guaranteed to operate over the extended industrial temperature range (from -40°C to +85°C).

1. Assert shutdown and program the device during power-up, then de-shutdown to the desired preset level.

2. The terms digital potentiometer, virtual reality and RDAC are used interchangeably.

Absolute Maximum Ratings

T=25°C unless otherwise noted.

1. The maximum terminal current is limited by the maximum current handling of the switch, the maximum power dissipation of the package, and the maximum applied voltage to any two of the A, B, and W terminals at a given resistance.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal resistance

θ is specified in the worst case, i.e., a device soldered in a circuit board in a surface mount package. Package power dissipation = = (TJMAX − TA)/ θJA .

Typical performance characteristics

test circuit

Figures 33 to 43 define the test conditions used in the product specification sheet.

theory of operation

The AD5280/AD5282 are single- and dual-channel, 256-bit digitally controlled variable resistors (VRs). To program the virtual reality setup, see the Digital Interface section. Both parts have a built-in power-up preset that places the wipers in mid-scale when powered up, which simplifies fault recovery when powered up. The operation of the power-on preset function also depends on the state of the Vl pin.

Rheostat operation

The nominal resistances of the RDAC between Terminal A and Terminal B are 20 kΩ, 50 kΩ, and 200 kΩ, respectively. The last two or three digits of the part number determine the nominal resistance value, such as 20 kΩ=20, 50 kΩ=50, and 200 kΩ=200. The nominal resistance (R) of VR has 256 points of contact through the wiper terminal and the B terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings. Assuming a 20 kΩ part is used, the first connection to the wiper starts at the B terminal of data 0x00. Because of the wiper contact resistance of 60Ω, such a connection creates a minimum resistance of 60Ω between terminal W and terminal B.

The second connection corresponds to 138Ω for data 0x01 (R=R/256+R=78Ω+60Ω). The third connection is the next tap point, representing 216Ω (78×2+60) of data 0x02, and so on. With each additional LSB data value, the wipers move up the resistor ladder until the last tap point reaches 19982Ω (R – 1 LSB+R). Figure 46 shows a simplified diagram of the equivalent RDAC circuit without the last resistor string connected; therefore, the nominal resistance at full scale is 1LSB less in addition to the wiper resistance.

The general formula for determining the digitally programmed output resistance between W and B is:

where: D is the decimal equivalent of the binary code loaded in the 8 bits of the RDAC register. RAB is the nominal end-to-end resistance. RW is powered by an internal switch.

Note that there is a finite wiper resistance of 60Ω under zero-scale conditions. In this state, care should be taken to limit the current between W and B to a maximum pulsed current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Like the mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. The resistance value for setting R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

The typical distribution of the nominal resistance R from one channel to the other is within ±1%. Equipment-to-equipment matching is process batch dependent and may vary by ±30%. Since the resistive element is processed with thin film technology, the variation of R with temperature is small (30ppm/°C).

Potentiometer Operation

The digital potentiometer easily creates a voltage divider at wiper to B and wiper to a proportional to the input voltage at a to B. Unlike the polarity of V–V, which must be positive, the voltages between a to B, W to a, and W to B can be of any polarity, provided that V is powered by a negative supply.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground will produce an output voltage with the wiper connected to B, starting at 0 V and ending at 1 LSB less than 5 V. The voltage of each LSB is equal to the voltage applied between A to B divided by the 256 positions of the potentiometer divider. Because the AD5280/AD5282 can be powered by dual supplies, the general equation that defines the output voltage of any active supply with respect to ground at V applied to the input voltage at Terminal A and Terminal B is:

For a more precise calculation including the effect of wiper resistance, V can be taken as:

The operation of the digital potentiometer in voltage divider mode allows for more precise operation when the temperature is too high. Unlike the varistor mode, the output voltage is mainly determined by the ratio of the internal resistances R and R, not the absolute value; therefore, the temperature drift is reduced to 5ppm/°C.

digital interface

2-wire serial bus

The AD5280/AD5282 are controlled via an IC-compatible serial bus. The RDAC is connected to this bus as a slave device. As shown in Figure 45, Figure 46, and Table 6, the first byte of the AD5280/AD5282 is the slave address byte. It has a 7-bit slave address and an R/W bit.

5 msb is 01011, the next two bits are determined by the state of AD0 pin and AD1 pin of the device. AD0 and AD1 allow the user to place up to four IC-compatible devices on a single bus. The 2-wire IC serial bus protocol operates as follows.

The master initiates a data transfer by establishing a start condition, which occurs when a high-to-low transition occurs on the SDA line while SCL is high (see Figure 45). The following bytes are the slave address byte, consisting of the 7-bit slave address followed by an R/W bit (this bit determines whether data is read from or written to the slave device).

The slave whose address corresponds to the transmit address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, while the selected device waits, all other devices on the bus remain idle to write or read data to the serial registers. If the R/W bit is high, the master device reads from the slave device. On the other hand, if the R/W bit is low, the master writes to the slave.

A write operation contains one more instruction byte than a read operation. The instruction byte for this write mode follows the slave address byte. The most significant bit (MSB) of the instruction byte marked A/B is the RDAC subaddress select. Low selects RDAC1 and high selects RDAC2 of the dual AD5282. Set A/B low for AD5280.

RS, the second MSB, is the midscale reset. A logic high on this bit moves the wiper of the selected channel to the center tap, where RWA=RWB. This function effectively overwrites the contents of the register, so when exiting reset mode, the RDAC remains at midscale.

SD, the third MSB, is an off bit. When the wiper is shorted to terminal B, a logic high causes the selected channel to be open at terminal A. This operation produces almost 0Ω in rheostat mode and 0 V in potentiometer mode. This SD bit serves the same function as the SHDN pin, except that the SHDN pin responds to an active low voltage. Also, the SHDN pin affects both channels (AD5282), not the SD bit, which only affects the channel being written to. Note that the close operation does not interfere with the contents of the registers. When resuming from a shutdown state, the previous settings will be applied to the RDAC.

The following two are O and O. They are additional programmable logic outputs that can be used to drive other digital loads, logic gates, LED drivers, analog switches, and more. The three LSBs are don't care bits (see Figure 45).

After acknowledging the command byte, the last byte in the write mode is the data byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledge bit). A transition on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 45).

In read mode, the data byte follows the acknowledgment of the slave address byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (slightly different from write mode, which has 8 data bits followed by an acknowledge bit). Likewise, transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 46).

When all data bits have been read or written, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line when SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 45). In read mode, the master responds with a no to the ninth clock pulse (ie the SDA line is held high). The master then pulls the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 46).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after only addressing and indicating the part once. During a write cycle, the RDAC output is updated with each data byte. For example, after the RDAC has confirmed its slave address and instruction byte, the RDAC output will be updated after these two bytes. If another byte is written to the RDAC while it is still being addressed to a specific slave with the same instruction, that byte will update the output of the selected slave. If a different instruction is required, the write mode must start with a new slave address, instruction and data bytes. Likewise, the repeated read function of the RDAC is also allowed.

Read back RDAC value

The AD5280/AD5282 allow the user to read the RDAC value in read mode. However, for the dual-channel AD5282, the channel of interest is the channel previously selected in write mode. When the user needs to read the RDAC values of two channels in the AD5282, they can program the first subaddress in write mode and then change to read mode to read the first channel value. After that, they can switch back to write mode using the second subaddress and read the second channel value again in read mode. The user does not need to issue frame 3 data bytes in write mode for subsequent readback operations. The user should refer to Figure 45 and Figure 46 for the programming format.

Additional programmable logic outputs

The AD5280/AD5282 have additional programmable logic outputs O and O that can be used to drive digital loads, analog switches, and logic gates. O and O default to logical 0. The logic states of O and O can be programmed in the write mode of frame 2 (see Figure 45). These logic outputs have sufficient current drive capability to sink/source mA loads.

The user can also activate O and O in three ways without affecting the wiper settings by programming:

• Execute Start, Slave Address, Acknowledge and Command bytes, Acknowledge, Stop using the specified O and O.

• Complete the write cycle, stop first, then start, from address byte, acknowledge, instruction byte specifying 0 and 0, acknowledge, stop.

• Do not complete a write cycle by issuing a stop, then start, slave address byte, acknowledge, instruction byte with 0 and 0 specified, acknowledge, stop.

Independent shutdown function and programmable presets

Shutdown can be activated by swiping on the SHDN pin or by programming the SD bit in the write mode command byte. As shown in Figure 44, when shutdown is asserted, the AD5280/AD5282 open the switch, leaving the A terminal floating and shorting the W terminal to the B terminal. In shutdown mode, the AD5280/AD5282 consume negligible power and continue with a previous setting after releasing the SHDN pin.

Additionally, shutdown can be accomplished using the device digital outputs, as shown in Figure 47. In this configuration, the device shuts down during power up, but allows the user to program the device at any preset level. When it is complete, the user program O high with valid encoding and the device exits shutdown and responds to the new settings. This self-contained shutdown capability allows absolute shutdown during power-up, which is critical in hazardous environments, without adding additional components. Additionally, sleep mode programming during shutdown allows the AD5280/AD5282 to have programmable presets at any level, a solution that can be as effective as using other high-cost EEPROM devices. Because of the extra power on R, note that a high value should be chosen for R.

Multiple devices on a bus

Figure 48 shows four AD5282 devices on the same serial bus.

Each has a different slave address because of the different states of their Pin AD0 and Pin AD1. This allows each RDAC in each device to be independently written to or read from. The master output bus driver is an open-drain drop-down menu in a fully integrated circuit compatible interface.

Bidirectional interface level conversion

While most older systems can operate at one voltage, new components can be optimized at another. Proper level shifting is required when two systems run the same signal at two different voltages. For example, a 3.3v EEPROM can interface with a 5v digital potentiometer. A level shifting scheme is required to enable bidirectional communication so that the settings of the digital potentiometers can be stored to and retrieved from the EEPROM. Figure 49 shows one such implementation. M1 and M2 can be any N channel signal fet, if V is below 2.5v, it can be a low threshold FDV301N.

Level Shift for Negative Voltage Operation

Digital potentiometers are popular in laser diode driver applications and certain telecom equipment level setting applications. These applications sometimes operate between ground and a negative supply voltage so that the system can be biased at ground to avoid large bypass capacitors that can severely hinder AC performance. Like most digital potentiometers, the AD5280/AD5282 can be configured with a negative supply (see Figure 50).

However, the digital inputs must also be level shifted to allow correct operation, since ground is referenced to a negative potential. Figure 51 shows one with several transistors and several resistors. When the VIN is below the third quarter threshold, Q3 is off, Q1 is off, and Q2 is on. In this state, VOUT is close to 0 V. When the VIN is higher than 2 V, Q3 is on, Q1 is on, and Q2 is off. In this state, VOUT is pulled to VSS. Be aware that success also requires appropriate time transitions to communicate with the device.

ESD protection

All digital inputs are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 52. This protection applies to digital inputs SDA, SCL and SHDN.

Terminal voltage operating range

The AD5280/AD5282 positive VDD and negative VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. The power supply signal turns on resistor terminal A, resistor terminal B and wiper terminal W above VDD or VSS is clamped by internal forward biased diodes (see Figure 53).

power-on sequence

Because there are ESD protection diodes that limit the voltage compliance of Terminal A, Terminal B, and Terminal W (see Figure 53), apply any voltage across the A, B, and W terminals. Otherwise, the diodes are forward biased, causing VDD/VSS to inadvertently energize, potentially affecting other parts of the user circuit. The ideal power ascending sequence is as follows: GND, VDD, VSS, digital input and VA/VB/VW. VA/VB/VW supply sequence and digital inputs are not important as long as they are powered up after VDD/VSS.

Layout and Power Bypass

It is a good practice to design a compact, minimal layout with minimum lead lengths. Wires leading to the input should be as direct as possible to the minimum conductor length. The ground path should have low resistance, low inductance.

Also, it is a good practice to bypass the power supply with good quality capacitors for best stability. Power lines should be bypassed with 0.01µF to 0.1µF discs, or chip ceramic capacitors. Low ESR 1µF to 10µF tantalum or electrolytic capacitors should also be used to minimize any transient disturbances and filter low frequency ripple (see Figure 54). Note that the digital ground should also be remotely connected to a point on the analog ground to minimize digital ground bounce.

application information

Dual Power Bipolar DC or AC Operation

The AD5280/AD5282 can be operated with dual power supplies, allowing control of ground-referenced AC signals or bipolar operation. AC signals up to V/V can be applied directly to terminal B through terminal A, and the output is taken from terminal W. A typical circuit connection is shown in Figure 55.

Gain Control Compensation

Digital potentiometers are often used in gain control applications, such as the non-rotating gain amplifier shown in Figure 56.

Note that the RDAC B terminal parasitic capacitance is connected to the op amp non-converting node. It introduces 0,20 dB/dec for the 1/β term, whereas a typical op-amp GBP has a -20 dB/dec characteristic. A large R2 and limited C1 can result in a 0 frequency well below the crossover frequency. Therefore, the closing rate becomes 40db/dec and the system has 0° phase margin at the crossover frequency. If the input is a rectangular pulse or step function, the output may ring or oscillate. Also, it can be loud when switching between two gain values, as this is equivalent to a step change at the input.

According to the op amp GBP, reducing the feedback resistance can extend the frequency of the zero enough to overcome the problem. A better approach is to include compensation capacitor C2 to remove the effect caused by C1. The best compensation occurs when R1×C1=R2×C2. This is not an option unless C2 is scaled by the maximum value of R2. Doing so may overcompensate and affect performance slightly when R2 is set to a low value. However, it avoids gain peaking, ringing or oscillation in the worst case. For critical applications, C2 should be found empirically to meet the needs. In general, a C2 in the range of a few picofarads (pF) to no more than a few tenths of a picofarad is usually sufficient to compensate.

Similarly, there are W and A terminal capacitors connected to the output (not shown); fortunately, they have less effect at this node and compensation can be avoided in most cases.

The AD5280/AD5282 can be configured as high voltage DACs up to 15 V. The output is:

Figure 58 shows a low-cost 8-bit bipolar DAC. It provides the same number of adjustable steps, but not the same precision as traditional DACs. Linearity and temperature coefficients, especially at low value codes, can be skewed by the wiper resistance of the digital potentiometer. The output of this circuit is:

Bipolar Programmable Gain Amplifier

For applications requiring bipolar gain, Figure 59 shows an implementation similar to the previous circuit. Digital potentiometer U sets the adjustment range. Therefore, for a given U setting, the wiper voltage at W can be programmed to be between V and –KV. Configuration A in non-vertical mode allows linear gain and attenuation. The transfer function is:

where K is the ratio of RWB1/RWA1 set by U1.

As in the previous example, in the simpler and more common case of K=1, a single digital AD5280 potentiometer is used. U is replaced by a matched pair of resistors to apply V and −V at the ends of the digital potentiometer. The relationship becomes:

If R2 is large, a compensation capacitor with a small amount of pF may be required to avoid any gain peaking.

Table 7 shows the results of adjusting D, A2 configured for unity gain, gain 2, and gain 10. The result is a bipolar amplifier with linear programmable gain and 256 steps of resolution.

Programmable Voltage Source with Boost Output

For applications that require high current regulation, such as laser diode drivers or tunable lasers, a boost power supply can be considered (see Figure 60).

In this circuit, the inverting input of the op amp forces V to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the power supply via the N-channel FET N1. N1 power handling must be sufficient to dissipate (VV) × I power. The circuit can be powered from a 5V supply with a maximum current of 100mA. A1 needs to be a railto-rail input type. For precision applications, a voltage reference such as the ADR423, ADR292, or AD1584 can be applied to the input of a digital potentiometer.

Programmable Current Source

A programmable current source can be implemented with the circuit shown in Figure 61. The REF191 is a unique, low supply headroom and high current handling accuracy reference that can output 20mA at 2.048V. The load current is simply the voltage from the B terminal to the W terminal of the digital potentiometer divided by R.

The circuit is simple, but two things must be noted. First, a dual-supply op amp is ideal because the ground potential of the REF191 can swing from -2.048 V at zero scale to V at full scale set by the potentiometer. Although the circuit operates from a single supply, it reduces the programmable resolution of the system.

For applications requiring higher current capability, a few changes to the circuit in Figure 61 can produce adjustable currents in the hundreds of milliamps range. First, the voltage reference needs to be replaced with a high-current, low-loss regulator, such as the AD3333, and the operational amplifier needs to be replaced with a high-current dual-supply mode, such as the AD8532. Depending on the desired current range, an appropriate value for R must be calculated. Due to the large current flowing to the load, the user must be careful about the load impedance to avoid driving the op amp beyond the positive rail.

Programmable Bidirectional Current Source

For applications requiring bidirectional current control or higher voltage compliance, a Howland current pump can be used (see Figure 62). If the resistors are matched, the load current is "

"

In theory, R2 can be made as small as needed to achieve the desired current within the A output current drive capability. In this circuit, the OP2177 can output ±5ma in any direction, and the voltage compliance is close to 15v:

If resistor R1' and resistor R2' are precisely matched to R1 and R2+R2, respectively, the output impedance can be infinite. On the other hand, if the resistors don't match, it could be negative. Therefore, C1 must be in the range of 1 pF to 10 pF to prevent oscillation.

Programmable Low Pass Filter

In analog-to-digital conversion applications, anti-aliasing filters are often included to limit the frequency band of the sampled signal.

A two-channel digital potentiometer can be used for a second-order Sallen key low-pass filter (see Figure 63). This design equation is:

The user can start by choosing some convenient values for the capacitors. To achieve a maximum flat bandwidth of Q = 0.707, let C1 be twice C2 and let R1 = R2. As a result, R1 and R2 can be adjusted to the same setting to obtain the desired bandwidth.

programmable oscillator

In a classic Wien bridge oscillator (Figure 64), the Wien network (R, R', C, C') provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fO, the total phase shift is 0, and the positive feedback causes the circuit to oscillate. R=R', C=C', and R2=R2A//(R2B+Rdiode), the oscillation frequency is:

where R is equal to RWA:

At resonance, set the following balance bridges:

In practice, R2/R1 should be set a little more than 2 to ensure that this oscillation can start. On the other hand, the alternate conduction of diode D1 and diode D2 ensures that R2/R1 is small and therefore, the oscillation is stabilized.

Once the frequency is set, the oscillation amplitude can be adjusted by R2B because:

VO, ID and VD are interdependent variables. Appropriately select R2B to achieve a balance and make VO converge. R2B can be added in series with discrete resistors to increase the amplitude, but the total resistance cannot be too large to prevent the output from saturating.

RDAC circuit simulation model

Internal parasitic capacitance and external capacitive loading control the AC characteristics of the RDAC. The −3 dB bandwidth of the AD5280 (20 kΩ resistor) is configured as a potentiometric divider, measuring 310 kHz at half scale. Figure 24 provides the Bode plot characteristics for the three available resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. The parasitic simulation model is shown in Figure 65. A list of macromodel nets for 20 kΩ RDACs is provided.

List of macromodel nets for RDAC

Dimensions

1. Line 1 contains the model number, line 2 contains the ADI logo followed by the end-to-end resistance value, and line 3 contains the date code YYWW.

2. Z = RoHS compliant parts.