feature

±1.5 A, 50 V continuous output rating; low rDS (on) DMOS output driver; programmable slow, fast and mixed current decay modes; serial interface control chip function; low power synchronous rectification; internal UVLO and Thermal shutdown circuitry; cross-current protection; sleep and idle modes.

Designed for pulse width modulation (PWM) current control in two DC motors, the A3974SED is capable of outputting current to ±1.5A and operating voltage to 50 V. An internal fixed off-time is available through the serial interface and can operate in slow, fast and mixed current decay modes.

Provides independent enable input terminals for externally controlling the speed and torque application of each DC motor with a PWM control signal.

The synchronous rectification circuit allows the load current to flow through the DMOS output driver during low rDS(on) current decay. This feature will eliminate external clamping diodes in most applications, saving cost and external component count while minimizing power dissipation. Internal circuit protection includes thermal shutdown VDD hysteresis, under-voltage monitoring with charge pump and cross-current protection. Special powerups do not require sequencing.

The A3974SED is provided by a 44 lead plastic PLCC with four copper bat fins for maximum heat dissipation. This power label is at ground potential and does not require electrical isolation.

Functional block diagram

Function description

serial interface. The A3974SED is controlled via a 3-wire (clock, data, strobe) serial port. Programmable features allow maximum flexibility in configuring PWM based on motor drive requirements. Serial data is written as two 20-bit words: 1-bit select word and 19-bit data. Data is timed from D19 .

D0–D1 blank time. According to the table below, the current sense comparator is shielded when any output driver is on. fosc is the input frequency of the oscillator.

D2–D6 fixed off time. This five-bit word sets the fixed off-time for the internal PWM control circuit. Closing time by:

where N=0. . . . 31

For example, with an oscillator frequency of 4MHz, the fixed off time will be adjusted from 1.75µs to 63.75µs in 2µs increments.

D7–D10 fast decay time. This nibble sets the fast decay portion of the fixed off-time of the internal PWM control circuit. This only has an effect if the mixed decay mode is selected (via bit D17). For tfd>toff, the device will effectively operate in fast decay mode. The fast decay part is defined as:

where N=0. . . . 15

For example, with an oscillator frequency of 4MHz, the fast decay time will be adjusted from 1.75µs to 31.75µs in 2µs increments.

The different modes of operation are described in the Synchronous Rectification section of the functional description.

D13 External PWM decay mode. This bit determines the current decay mode when chopping is enabled using external PWM current control.

D14 enables logic. This bit, together with ENABLE, determines whether the output driver is in the chopped or on state.

D15 Phase Logic. This bit determines whether the device is operating in the forward or reverse state.

D16 Gm range option. This bit determines whether VREF is divided by 5 or 10.

D17 Bridge 2 mode. This bit determines the slow or mixed decay of the internal current control operation.

D19 test mode. This bit is reserved for testing and should not be changed by the user. Default (low) to operate the device in normal mode.

D0-D17. Definition is the same as word 0, word 1 is selected. Data is written to Full Bridge 2.

D19 idle mode. The device can be put into a low-power "idle" mode by writing a "0" to D19. The output will be disabled, the charge pump will be turned off, and the device will draw lower load supply current. The undervoltage monitoring circuit will remain active. D19 should be set high for 1 ms before attempting to enable any output drivers.

VREG. This internally generated supply voltage is used to operate the receiver side DMOS output. VREG is internally monitored, and in the event of a fault, the output of the device is disabled. The VREG terminal should be grounded separately from the 0.22µF capacitor.

Fill pump. A charge pump is used to generate a supply voltage greater than VBB to drive the source DMOS gate. A 0.22µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22µF ceramic capacitor should be connected between the VCPs as a reservoir for running high-end DMOS devices. The CP voltage is monitored internally and in the event of a fault the output of the device is disabled.

closure. If a fault occurs due to excessive junction temperature or low voltage on CP or VREG, the output of the device will be disabled until the fault condition is removed. On power-up, or in the case of low VDD, the UVLO circuit disables the driver and resets the data in the serial port to all zeros.

current regulations. The load current is regulated by an internal fixed off-time PWM control circuit. When the output of the DMOS H-bridge turns on, the current in the motor windings increases until it reaches the trip value determined by the external sense resistor (RS), the applied analog reference voltage (VREF), and serial data bit D16:

When D16=0…………ITRIP=VREF/10RS

When D16=1…………ITRIP=VREF/5RS

At the trigger point, the sense comparator resets the source enable latch, turning off the source driver (except in low-side-only mode, with the sink driver off). The load inductance then cycles the current for a fixed off time period programmed by the serial port. The current path during recirculation is determined by the slow/mixed decay mode (D17) and the configuration of the synchronous rectification control bits (D11 and D12).

sleep mode. Input sleep is designed to put the device into a minimum current consumption mode. When asserted low, the serial port will reset to all zeros and all circuits will be disabled.

PWM timer function. The PWM timer can be programmed through the serial port (bits D2–D10) to provide a fixed off-time PWM signal to the control circuit. In mixed current decay mode, the first part of the off time operates in fast decay until the fast decay time count (serial bits D7–D10) is reached, and then slowly decays for the remainder of the off time period (bits D2–D6). If the fast decay time is set longer than the off time, the device is effectively operating in fast decay mode. Bit D17 selects mixed decay or slow decay.

Synchronous rectification. When a PWM off cycle is triggered by the ENABLE chop command or the internal fixed off time period, the load current is recirculated according to the decay mode selected by the control logic. After a short crossover delay, the A3974 synchronous rectification feature will turn on the appropriate MOSFET (or pair of MOSFETs in the mixed decay portion of the off-time) during current decay and effectively short the body diode using a low rDS(on) driver. This will greatly reduce power dissipation and can eliminate the need for external Schottky diodes.

Synchronous rectification can be configured in active mode, passive mode, low side only, or disabled via the serial port (bits D11 and D12). Active mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. Passive mode allows current reversal, but if the load current reverses up to the current limit set by VREF/10RS (when D16=0) or VREF/5RS (when D16=1), the synchronous rectifier circuit will be turned off.

Low-side-only mode will turn on the low-side MOSFET during shutdown to short the current path through the MOSFET body diode. In this setup, the high-end mosfet will not be synchronously rectified, so four external diodes from the output to the power supply are recommended. This mode is suitable for high power applications wishing to save the expense of two external diodes per bridge. In this mode, the slot-side MOSFETs are switched off during the PWM off-time. In all other cases, the source-side mosfet is switched off in response to the PWM shutdown command.

application information

current sensing. To minimize inaccurate ITRIP current level sensing due to IR drops on the ground trace, the sense resistor should have an independent ground return to the device's ground terminal. For low value sense resistors, the IR drop in the resistor's PCB sense trace may be significant and should be considered. Sockets should be avoided as the contact resistance of the sockets can cause variations in RS.

The maximum value of RS is RS=0.5/itrpmax.

brake. The device is driven in slow decay mode via serial port bit D13, synchronous correction is enabled via bits D11 and D12, and the braking function is implemented by applying the enable chop command in conjunction with D14 and the enable input terminal. Because current can be driven bidirectionally through the DMOS switch, this configuration effectively shorts out the BEMF generated by the motor as long as the enable chopper mode is asserted. It is important to note that the internal PWM current control circuit does not limit the current when braking because the current does not flow through the sense resistor. The maximum braking current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded at high speeds and high inertia loads.

Thermal Protection. Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.

layout. Printed wiring boards should use heavy duty ground planes. For best electrical and thermal performance, the driver should be soldered directly to the board. The ground side of the RS should have a separate path to the equipment ground terminal. This path should be physically as short as possible and should not connect any other components. The load power terminal VBB should be separated from an electrolytic capacitor (recommended greater than 47µF) placed as close as possible to the device.

Serial port write timed operation. On the rising edge of the clock signal, data is recorded into the shift register. Normally, the strobe will remain high and only decrease when a write cycle is initiated. See the diagram and specification table below for timing requirements.

Dimension Unit: Inches (Control Dimensions)

Note: 1. Lead spacing tolerance is non-cumulative.

2. Within the limits shown, the exact body and lead configuration is selected by the supplier.

3. Available in standard rod/tube for 28 devices, or add "TR" to part numbers for tape and reel.

Dimensions are in mm (for reference only)

Note: 1. Lead spacing tolerance is non-cumulative.

2. Within the limits shown, the exact body and lead configuration is selected by the supplier.

3. Available in standard rod/tube for 28 devices, or add "TR" to part numbers for tape and reel.

The products described herein are manufactured under one or more US patents or US patents pending.

Allegro MicroSystems, Inc. reserves the right to deviate from detailed specifications at any time to improve the performance, reliability or manufacturability of its products. Before placing an order, the user is reminded to confirm that the information relied upon is up to date.

Allegro products may not be used as critical components of life support equipment or systems without express written approval.