feature

High performance, 24-bit sigma-delta ADC; 115 dB dynamic range at 78 kHz output data rate; 112 dB dynamic range at 156 kHz output data rate; 156 kHz maximum fully filtered output word rate; pin selectable oversampling rate (128 × and 256 × low-power modes); flexible SPI; fully differential modulator input; on-chip differential amplifier for signal buffering; full-band low-pass finite impulse response (FIR) filter overrange alarm pin; digital gain correction register Power-down mode; synchronization of multiple devices via daisy-chaining of sync pins.

application

Data acquisition system; vibration analysis instrument.

General Instructions

The AD7765 is a high performance 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). It combines the performance of wide input bandwidth, high speed and 112db dynamic range at an output data rate of 156khz. The converter has excellent DC characteristics and is ideal for high-speed data acquisition of AC signals that require DC data.

Using the AD7765 simplifies the front-end antialiasing filtering requirements and greatly simplifies the design process. The AD7765 offers pin-selectable decimation rates of 128× and 256×. Additional features include an integrated buffer to drive the reference, and a fully differential amplifier to buffer and level shift the modulator input.

When the input signal is outside the acceptable range, the overrange alarm pin will display. The addition of internal gain and internal overrange registers makes the AD7765 a compact, highly integrated data acquisition device that requires minimal peripheral components.

The AD7765 also offers a low-power mode that significantly reduces power consumption without reducing the output data rate or available input bandwidth.

The differential input is sampled by an analog modulator at speeds up to 40 MSPS. The modulator output is processed by a series of low pass filters. The external clock frequency applied to the AD7765 determines the sample rate, filter corner frequency, and output word rate.

The AD7765 device has a full-band onboard FIR filter. The full stopband attenuation of the filter is achieved at the Nyquist frequency. This feature provides increased protection against signals above the Nyquist frequency from being aliased back into the input signal bandwidth.

The reference voltage supplied to the AD7765 determines the input range. With a 4V reference, the analog input range is ±3.2768 V differential, biased around a common mode of 2.048 V. This common-mode biasing can be achieved using an on-chip differential amplifier, further reducing external signal conditioning requirements.

The AD7765 is available in a 28-lead TSSOP package and is specified over the industrial temperature range of -40°C to +85°C.

Absolute Maximum Ratings

TA = 25°C unless otherwise noted.

1. The absolute maximum voltage of VIN negative, VIN positive, VIN negative and VIN positive is 6.0 V or AVDD3+0.3V, whichever is lower.

2. The absolute maximum voltage on the digital input is 3.0 V or DVD+0.3 V, whichever is lower.

3. The absolute maximum voltage on the VREF+ input is 6.0 V or AVDD4+0.3 V, whichever is lower. 4 Transient currents up to 100 mA will not cause thyristors to latch up.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; equipment at these or any other conditions beyond those listed in the Operation section is not implied in this specification. Exposure to absolute long-term maximum rated conditions may affect device reliability.

Typical performance characteristics

AVDD1=DVDD=2.5 V, AVDD2=AVDD3=AVDD4=5 V, VREF+=4.096 V, MCLK amplitude=5 V, TA=25°C. Measured linear curve with 16-bit precision; input signal reduced to avoid modulator overload and digital clipping; fast Fourier transform (FFT) generated from 8192 samples.

the term

signal to noise ratio

The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and DC. The signal-to-noise ratio is expressed in decibels (dB).

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental. For the AD7765, it is defined as:

where: V1 is the rms amplitude of the fundamental wave. V2, V3, V4, V5 and V6 are the second sixth harmonic.

Aharmonic Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components, excluding harmonics.

Dynamic Range

The ratio of the full-scale rms value to the rms noise measured with the input shorted. The value of dynamic range is expressed in dB.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3, etc. Intermodulation distortion terms refer to terms where neither m nor n equals 0. For example, second-order terms include (fa+fb) and (fa-fb), while third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7765 is tested using the CCIF standard, which uses two input frequencies near the top of the input bandwidth. In this case, the second-order term is usually at a distance from the original sine wave in frequency, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second- and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, which is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental sum in dB.

Integral Nonlinearity (INL)

Maximum deviation of a straight line through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured value and the ideal 1 LSB between any two adjacent codes in the ADC changes.

zero error

The difference between the ideal midscale input voltage (when the two inputs are shorted together) and the actual voltage that produces the midscale output code.

Zero error drift

The change in the actual zero error value due to a 1°C change in temperature. Expressed as a percentage of full scale at room temperature.

gain error

The first transition (from 100…000 to 100…001) should occur at nominally negative full scale above 1/2 LSB of the analog voltage. The last conversion (from 011...110 to 011...111) should occur at an analog voltage 1 1/2 LSB below nominal full scale. The gain error is the deviation of the difference between the actual energy level of the last transition and the actual energy level of the first transition and the difference between the ideal energy level.

Gain Error Drift

Change in actual gain error value due to a 1°C change in temperature. Expressed as a percentage of full scale at room temperature.

theory of operation

The AD7765 has an on-chip fully differential amplifier to feed the sigma-delta modulator pins, an on-chip reference buffer, and an FIR filter block to perform the digital filtering required for the sigma-delta modulator output. Using this sigma-delta conversion technique and additional digital filtering, the analog input is converted into an equivalent digital word.

Sigma-Delta Modulation and Digital Filtering

The input waveform applied to the modulator is sampled and the equivalent digital word is output to the digital filter at a rate equal to ICLK. By employing oversampling, the quantization noise spreads over a wide bandwidth from 0 to f. This means that the noise energy contained in the signal band of interest is reduced (see Figure 23). To further reduce quantization noise, high-order modulators are used to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see Figure 24).

The digital filtering following the modulator removes the large out-of-band quantization noise (see Figure 25) while also reducing the data rate at the filter input from f to f/128 at the filter output, depending on the decimation rate used or smaller.

The AD7765 employs three FIR filters in series. By using different combinations of decimation rates, data can be obtained from the AD7765 at three data rates.

The first filter receives data from the modulator at ICLK MHz and decimates 4× at ICLK MHz to output the data at (ICLK/4) MHz. The second filter allows to choose the decimation rate: 16× or 32×.

The third filter has a fixed decimation rate of 2×. Table 6 shows some characteristics of digital filtering, where ICLK=MCLK/2. The group delay of a filter is defined as the delay in the center of the impulse response, equal to the amount of computation plus the filter delay. The delay before valid data is available (with the FILTER-SETTLE status bit set) is approximately twice the FILTER delay plus the computation delay. This is listed in Table 6 for the MCLK period.

AD7765 Antialiasing Protection

The decimation of the AD7765 and its counterparts in the AD776x family (ie AD7760, AD7762, AD7763, and AD7764) provides top-level antialiasing protection.

The decimation filter of the AD7765 has more than 115dB of attenuation across the stopband, which ranges from the Nyquist frequency (that is, ODR/2) to ICLK-ODR/2 (where ODR is the output data rate). Starting the stop band at the Nyquist frequency prevents any signal components above Nyquist (and up to ICLK−ODR/2) from aliasing into the desired signal bandwidth.

Figure 26 shows the frequency response of the decimation filter when operating the AD7765 in decimation 128× mode with a 40 MHz MCLK. Note that the first stopband frequency occurs at Nyquist. The frequency response of the filter and the selection of the decimation rate and the application of the MCLK frequency. In low-power mode, the modulator sample rate is MCLK/4.

Taking the AD7765 as an example, in normal power and 128× mode, the first possible alias is the ICLK frequency minus the passband of the digital filter (see Figure 27).

AD7765 Input Structure

The AD7765 requires a 4.096 V input at reference pin VREF+, which is provided by a high precision reference such as the ADR444. Since the input to the device's sigma-delta modulator is fully differential, the effective differential reference range is 8.192 V.

Due to the inherent properties of sigma-delta modulators, only a certain portion of the complete reference signal can be used. In the case of the AD7765, an 80% fully differential reference can be applied to the differential inputs of the modulator.

This means that a maximum of ±3.2768 V pp can be applied to each AD7765 modulator input (pin 5 and pin 6) and the AD7765 input is reduced by -0.5 dB from full scale (0.5 dBFS). The AD7765 modulator input must have a common-mode input of 2.048 V.

Figure 28 shows the relative scale between the differential voltage applied to the modulator pins and the corresponding 24-bit double complement digital output.

On-chip differential amplifier

The AD7765 contains an on-board differential amplifier recommended for driving the modulator input pins. Pin 1, Pin 2, Pin 3, and Pin 4 on the AD7765 are the differential input and output pins of the amplifier. External components RIN, RFB, CFB, CS and RM are placed between Pin 1 to Pin 6 to create the recommended configuration. To achieve the specified performance, the difference amplifier should be configured as a first-order antialiasing filter using the component values listed in Table 7, as shown in Figure 29. The inputs of the differential amplifier are then routed through this network of external components before being applied to the modulator inputs V- and VIN+ (pins 5 and 6). Taking the best value in the table as an example, produces 25db of attenuation at the first alias point at 19.84mhz.

1. Values shown are acceptable tolerances for each component when relative to the specifications used to achieve the stated equipment.

The components that can be used in each of the differential amplifier configurations listed are shown in Table 7. When using a differential amplifier to obtain the input voltage for the desired modulator input range it is recommended to implement the gain function by varying RIN, leaving RFB as the optimum value listed.

The common-mode input range of each differential amplifier input (pin VINA+ and pin VINA-) is -0.5 V dc to 2.2 V dc. The amplifier has a constant output common-mode voltage of 2.048 V, which is VREF/2, the common-mode voltage required by the modulator input pins (VIN+ and VIN-).

Figure 30 shows signal conditioning using the differential amplifier configuration detailed in Table 7 with an input signal of ±2.5 V. The amplifiers in this example are biased around ground, scaled to ±3.168v pp (–0.5dbfs) on each 2.048v common-mode modulator input.

To get the maximum performance from the AD7765, it is recommended to drive the ADC with differential signals. Figure 31 shows how a bipolar, single-ended signal biased at ground can be used to drive the AD7765 using an external op amp, such as the AD8021.

Modulator Input Structure

The AD7765 uses a double sampling front end, as shown in Figure 32. For simplicity, only the equivalent input circuit of V+ is shown. The equivalent circuit of V- is the same.

The SS1 and SS3 sampling switches are driven by ICLK, while the SS2 and SS4 sampling switches are driven by ICLK. When ICLK is high, the analog input voltage is connected to CS1. On the falling edge of ICLK, the SS1 and SS3 switches open and the analog input is sampled on CS1. Similarly, when ICLK is low, the analog input voltage is connected to CS2. On the rising edge of ICLK, the SS2 and SS4 switches open and the analog input is sampled on CS2.

The CPA, CPB1 and CPB2 capacitors represent parasitic capacitances including the junction capacitances associated with the MOS switches.

Direct drive modulator input

The AD7765 can be configured to disable the on-board differential amplifier, and the discrete amplifier can be used to directly drive the modulator. This allows the user to reduce power consumption.

To power down the on-board differential amplifier, the user issues a write to set the AMP shutdown bit in the control register to logic high (see Figure 33).

The AD7765 modulator inputs must have a common-mode voltage of 2.048 V and follow the amplitudes described in the AD7765 Input Structure section.

Figure 34 shows an example of a typical circuit driving the AD7765 for applications that require excellent AC and DC performance. The AD8606 or AD8656 can be used to directly drive the AD7765 modulator input.

Best practice is to short the differential amplifier input to ground with typical input resistance and leave the typical feedback resistance.

AD7765 interface

read data

The AD7765 uses an SPI-compatible serial interface. The timing diagram in Figure 2 shows how the AD7765 transmits its conversion result.

The data read from the AD7765 is clocked using the serial clock output (SCO). The SCO frequency is half of the AD7765 MCLK input frequency.

The conversion result output on the serial data output (SDO) line consists of the frame synchronization output (FSO), which is logic low for 32 SCO cycles. Each bit of the new conversion result is recorded on the SDO line on rising SCO edges and is valid on falling SCO edges. The 32-bit result consists of 24 data bits, 5 status bits, and 3 zeros. The five status bits are listed in Table 9 and described in the following table.

• The FILTER-SETTLE bit indicates whether the data output from the AD7765 is valid. After resetting the device (using the reset pin) or clearing the digital filter (using the sync pin), the filter settling logic goes low to indicate that the filter's full settling time has not elapsed and the data is not yet valid. The FILTERSETTLE bit will also go to zero when the component's input has asserted an out-of-range alarm.

• The OVR (overrange) bit is described in the Overrange Alerts section.

• When the AD7765 is operating in low power mode, the LPWR bit is set to logic high. See the Power Modes section for more details.

• The DEC_RATE 1 and DEC_RATE 0 bits indicate the decimation rate used. Table 10 is the truth table for the decimation rate bits.

Read status and other registers

The AD7765 has a gain correction register, an overrange register, and a read-only status register. To read the contents of these registers, the user must first write to the device's control register and set the bit corresponding to the register to be read. The next read operation outputs the contents of the selected register (on the SDO pin), not the conversion result.

To ensure that the next read cycle contains the contents of the write register, a write to this register must complete at least 8 × t before the falling edge of FSO (indicating the start of the next read cycle). See Figure 4 for more details.

The AD7765 Registers section provides more information on the relevant bits in the control registers.

Write to AD7765

A write operation to the AD7765 is shown in Figure 3. Serial write operations are synchronized with the SCO signal. The state of the frame sync input FSI is on the falling edge of the SCO signal. If the FSI line is low, the first data bit on the Serial Data Input (SDI) line is latched on the next SCO falling edge.

The active edge of the FSI signal is set to occur when the SCO signal is high or low to allow the setup and hold times of the falling edge of the SCO to be met. The width of the FSI signal can be set from 1 to 32 SCO cycle widths. The second or subsequent falling edge that occurs before 32 SCO cycles have elapsed is ignored.

Figure 3 details the format of the serial data written to the AD7765 through the SDI pin. Write operations require 32 bits. The first 16 bits are used to select the register address from which data is to be read. The second 16 bits contain the data for the selected register.

The AD7765 is allowed to be written to at any time, even while the conversion result is being read. Note that when writing to the device, valid data is not output until after the filter's set time has elapsed. At this point, the FILTER-SETTLE status bit is asserted to indicate that the filter is set and valid data is available at the output.

AD7765 Features

Synchronize

The sync input of the AD7765 provides a sync function that allows the user to begin collecting samples of the analog front end input from a known point in time.

The synchronization feature allows operation of multiple AD7765 devices from the same master clock using a common sync and reset signal so that each ADC updates its output registers simultaneously. Note that all devices being synced must be running at the same decimation rate in the same power mode.

For systems with multiple AD7765s, connect the common MCLK, sync, and reset signals to each AD7765.

The AD7765 sync pin is polled by the falling edge of MCLK. The AD7765 device enters the sync state when the sync input signal is detected logic low on the falling edge of MCLK. At this point, the digital filter sequencer is reset to 0. The filter remains in reset (sync mode) until the first MCLK falling edge senses a sync logic high.

Where possible, ensure that all transitions that are synchronized occur synchronously with the rising edge of MCLK (that is, as far away as possible from the falling or decision edge of MCLK). Otherwise, follow the timing specified in Figure 35, which does not include the synchronous rising edge occurring in the 10ns window around the falling edge of MCLK.

Hold synchronous logic low for at least four MCLK cycles.

When the falling edge of MCLK detects that sync has returned to logic high, the AD7765 filter begins to sample the input simultaneously. The falling edge of FSO is also synchronized, allowing conversion data to be output simultaneously.

After synchronization, the digital filter needs time to stabilize before valid data can be read from the AD7765. The user knows that there is valid data on the SDO line by checking the FILTER-SETTLE status bits (see D7 in Table 9) that are output with each conversion result. The time from the rising edge of SYNC to the assertion of the FILTER-SETTLE bit depends on the FILTER configuration used. See the "Theory of Operation" section and the values listed in Table 6 for details on calculating the time before the FILTERSETTLE assertion.

Note that the FILTER-SETTLE bit is designed as a reaction flag to alert the user when the converted data output is valid.

Out of range alert

The AD7765 provides overrange functionality on both the pins and the status bit output. When the voltage applied to the AD7765 modulator input pin exceeds the limit set in the overrange register, the overrange alarm indicates that the applied voltage is approaching the overrange level of the modulator. To set this limit, the user must program the registers. The default overrange limit is set to 80% of the VREF+ voltage (see AD7765 Registers section).

The overrange pin outputs a logic high to alert the user that the modulator has sampled an input voltage whose magnitude is greater than the overrange limit set in the overrange register.

The overrange pin is set to logic high when the modulator samples an input above the overrange limit. The overrange pin returns to zero when the input returns below the limit. The overrange pin is updated after the first FIR filter stage. Its output varies at ICLK/4 frequency.

During a data conversion, the OVR status bit is output as Bit D6 on SDO and can be checked in the AD7765 status register. This bit is not as dynamic as the overrange pin output. It is updated each time the conversion result is output; that is, the bits vary with the output data rate. The OVR bit is set to logic high if, during sampling for a particular conversion result output, the modulator samples a voltage input that exceeds the overrange limit.

The output points from FIR Filter 1 in Figure 36 are not plotted to scale relative to the output data rate points. The FIR Filter 1 output is updated 16× or 32× faster than the output data rate depending on the decimation rate in the operation.

power mode

low power mode

During power-up, the AD7765 operates in normal power mode by default. No register writes are required. The AD7765 also offers a low power mode. To operate the device in low power mode, the user sets the LPWR bit in the control register to logic high (see Figure 37). Operating the AD7765 in low power modes does not affect the output data rate or available bandwidth.

reset/PWRDWN mode

The AD7765 has a reset/PWRDWN pin. Holding the input to this pin logic low puts the AD7765 in power down mode. All internal circuits are reset. After the device is initially powered up, a reset pulse is applied to the AD7765. The AD7765 reset pin is polled by the rising edge of MCLK. The AD7765 device enters the reset state when the reset input signal is detected as a logic low by rising MCLK. The AD7765 comes with a reset deassertion on the first MCLK rising edge that senses reset as a logic high.

It is a best practice to ensure that all transitions of reset occur in synchronization with the falling edge of MCLK; otherwise, follow the timing requirements shown in Figure 38.

Reset should be held logic low for at least 1 MCLK cycle for a reset to occur.

If synchronizing multiple AD7765 devices using a sync pulse, daisy-chaining multiple AD7765 devices must be done in addition to the normal sync and MCLK signals.

decimation rate PIN

The decimation rate of the AD7765 is selected using the DEC_rate pin. Table 11 shows the required voltage input settings for the three decimation rates.

Daisy chain

Daisy chaining allows many devices to use the same digital interface line. This feature is especially useful for reducing component count and wiring connections, such as in isolated multi-converter applications or for systems with limited interface capacity. Data readback is similar to clocking a shift register. When using a daisy chain, all devices in the chain must operate in a common power mode and a common decimation rate.

The block diagram in Figure 39 shows how to connect the devices for a daisy-chain function. Figure 39 shows four AD7765 devices daisy-chained together with the application's common MCLK signal.

Read data in daisy-chain mode

Referring to Figure 39, note that the SDO line of the AD7765 (A) provides the output data of the AD7765 converter chain. Also, note that for the last device in the chain, the AD7765 (D), the SDI pin is grounded. All devices in the chain must use a common MCLK and sync signal. To enable the daisy-chain conversion process, apply a common sync pulse to all devices (see the sync section).

After the sync pulse is applied to all devices, the filter-SETTLE time must elapse before the filter-SETTLE bit is asserted to indicate valid conversion data at the output of the device chain. As shown in Figure 40, the first conversion result is output from the device labeled AD7765(A). This 32-bit conversion is then followed by conversions from the devices AD7765(B), AD7765(C), and AD7765(D), all output MSB first. The signals output from the daisy chain are the conversion result stream from the SDO pin of the AD7765(A) and the FSO signal stream from the first device in the chain, the AD7765(A).

The falling edge of FSO signals the MSB of the output of the first conversion in the chain. FSO remains logic low for the 32 SCO clock cycles required to output the AD7765(A) result, then goes logic high during the output of the conversion result from the AD7765(B), AD7765(C), and AD7765(D) devices flat.

The maximum number of devices that can be daisy-chained depends on the selected decimation rate. Simply divide the chosen decimation rate by 32 (the number of bits each conversion must be clocked) to calculate the maximum number of devices that can be daisy-chained. Table 12 provides the maximum number of chained devices per decimation rate.

Write data in daisy-chain mode

Writing to AD7765 devices in daisy-chain mode is similar to writing to a single device. Serial write operations are synchronized with the SCO signal. Check the status signal of the frame sync input FSI on the falling edge of SCO. If the FSI line is low, the first data bit of serial data on the SDI line is latched on the next falling edge of SCO.

Writing to the AD7765 in daisy-chain mode has the same timing structure as writing to a single device (see Figure 3). The difference between writing to a single device and writing to multiple daisy-chained devices is the implementation of the FSI signals. Whether the number of devices in a daisy chain determines the period for which the FSI signal must remain logic low. To write to n devices in a daisy chain, the period between the falling edge of FSI and the rising edge of FSI must be between 32×n-1 and 32×n-SCO periods. For example, if three AD7765 devices are written in daisy-chain mode, FSI is logic low between 32×(3−1) to 32×3 SCO pulses. This means that the rising edge of the FSI must appear between the 64 and 96 SCO periods.

The AD7765 device can be written to at any time. The falling edge of FSI covers all attempts to read data from the SDO pin. In the case of a daisy chain, the FSI signal remains logic low for more than 32 SCO cycles to indicate to the AD7765 device that there are more devices in the chain. This means that the AD7765 directs the data input on the SDI pin to its SDO pin. This ensures that the data is passed to the next device in the chain.

Timing AD7765

The AD7765 requires an external low-jitter clock source. This signal is applied to the MCLK pin. The internal clock signal (ICLK) is derived from the MCLK input signal. ICLK controls the internal operation of the AD7765. The maximum ICLK frequency is 20 MHz. To generate ICLK, ICLK = MCLK/2.

For an output data rate equal to that used in an audio system, an ICLK frequency of 12.288mhz can be used. As shown in Table 6, output data rates of 96 kHz and 48 kHz can be achieved using this ICLK frequency.

MCLK Jitter Requirements

MCLK jitter requirements depend on many factors, as follows:

In the formula: OSR=oversampling rate=fICLK/ODR. fIN = maximum input frequency. SNR (dB) = target SNR.

Example 1: This example can be obtained from Table 6, where: ODR = 156.25 kHz. fICLK = 20 MHz. fIN (max) = 78.625 kHz. Signal-to-noise ratio = 104 dB.

This is the maximum clock jitter allowed at full scale, 78.625 kHz input tone, with a given ICLK and output data rate.

Example 2: The second example can also be obtained from Table 6, where: ODR = 48 kHz. fICLK = 12.288 MHz. fIN(max)=19.2 kHz. SNR = 109 dB.

The input amplitude also has an effect on these jitter numbers. For example, if the input level is 3db below full scale, the allowable jitter is increased by a factor of √2, increasing the first example to 144.65ps rms. This happens when the maximum slew rate is reduced by a magnitude.

Figure 43 and Figure 44 illustrate this, showing the maximum slew rate for sine waves of the same frequency but different amplitudes.

Decoupling and Layout Information

Power decoupling

Decoupling of the power supplies applied to the AD7765 is important to achieve maximum performance. Each power pin must be disconnected from the correct ground pin with a 100 nF, 0603 case size capacitor.

Take special care to separate pin 7 (AVDD2) directly from the nearest ground pin (pin 8). The digital ground pin AGND2 (pin 20) is directly connected to ground. Also, connect REFGND (pin 26) directly to ground.

DVDD (pin 17) and AVDD3 (pin 28) power supplies should be disconnected from the ground plane at a point away from the device. It is recommended to disconnect the power connected to the following power pins from the star ground connected to pin 23 (AGND1) through a 0603 size 100 nF capacitor.

• VREF+ (Pin 27)

• AVDD4 (pin 25)

• AVDD1 (pin 24)

• AVDD2 (pin 21)

A layout decoupling scheme for these supplies to the right of the AD7765 is shown in Figure 45. Note the star point ground created at pin 23.

Reference voltage filtering

A low noise reference source, such as the ADR444 or ADR434 (4.096 V), is suitable for use with the AD7765. The reference voltage supplied to the AD7765 should be decoupled and filtered as shown in Figure 46.

The recommended solution for the voltage reference supply is a 200Ω series resistor to a 100µF tantalum capacitor, followed by a 10 nF decoupling capacitor very close to the VREF+ pin.

Differential Amplifier Components

Table 7 details the correct components to use around the on-chip differential amplifier. Matching the components on both sides of the differential amplifier is important to minimize signal distortion applied to the amplifier. These parts require a tolerance of 0.1% or higher. The symmetrical routing of the rails on both sides of the differential amplifier also contributes to this performance. Figure 47 shows a typical layout of components around a difference amplifier. Note that the traces for the two differential paths are as symmetrical as possible, and the feedback resistors and capacitors are placed on the bottom of the PCB for easiest routing.

Layout Considerations

While using the right components is critical for optimal performance, the correct layout is equally important. The AD7765 product page on the AD7765 contains the Gerber files for the AD7765 evaluation board. These files should be downloaded and used as a reference when designing any system using the AD7765.

The use of ground aircraft should also be carefully considered. To ensure that the loop current through the decoupling capacitor goes to the correct ground pin, the ground side of the capacitor should be as close as possible to the ground pin associated with that power supply as recommended in the Power Supply Decoupling section.

Using AD7765

The following is the recommended sequence for starting and using the AD7765:

1. Power on the device.

2. Apply the MCLK signal.

3. Use a low reset for at least one MCLK cycle, preferably synchronous to a falling MCLK edge. If you want to sync multiple parts, apply a common reset to all devices.

4. After releasing reset, wait at least two MCLK cycles.

5. If multiple sections are being synchronized, a sync pulse must be applied to these sections, preferably in synchronization with the rising edge of MCLK. In the case where the devices are not in sync, no sync pulse is required; a logic high signal should simply be applied to the sync pins.

When a sync pulse is applied,

• Sending a sync pulse to the device must not occur at the same time as writing a sync pulse to the device.

• Make sure the sync pulse is low for at least four MCLK cycles.

Data can then be read from the device using the default gain and overrange thresholds. However, the converted data read is invalid until the set time of the filter has elapsed. Once this happens, the FILTER-SETTLE status bit is set, indicating that the data is valid. The gain and overrange threshold values can be written or read from the corresponding registers at this stage.

Bias Resistor Selection

The AD7765 requires a resistor connected between the RBIA and AGNDx pins. Resistor values should be chosen to provide 25 microamps of current through the resistor to ground. For a 4.096 V reference, the correct resistor value is 160 kΩ.

AD7765 registers

The AD7765 has many user programmable registers. The control registers are used to set the functions of the on-chip buffer and differential amplifier, and provide the option to turn off the AD7765. There are also digital gain and overrange threshold registers. Writing to these registers consists of writing the register address followed by a 16-bit data word. This section provides register addresses, individual bit details and default values.

control register

1. Bits 14 to 11 and bit 9 are self-clearing bits.

2. Only one bit can be set in any write operation because it determines the content of the next read operation.

status register

Gain Register Address 0x0004

Not bitmapped, default 0xA000

The gain registers are scaled so that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). When the input is 80% of VREF+, this results in a full-scale digital output, associated with ±80% of the maximum analog input range of VREF+pp.

Overrange register address 0x0005

Not bitmapped, default 0xCCCC

The overrange register value is compared to the output of the first decimation filter to obtain an overload indication with minimal propagation delay. This is before any gain scaling or offset adjustment. The default value is 0xCCCC, which is equivalent to 80% of VREF+ (maximum allowable analog input voltage). Assuming VREF+=4.096v, the bit is set when the input voltage exceeds about 6.55v pp differential. If the analog input voltage exceeds 100% of VREF+ for more than four consecutive samples at the modulator rate, the overrange bit is set immediately.

Dimensions