feature

±1.5 A, 50 V continuous output rating; low rDS (on) DMOS output driver; optimized microstepping via 6-bit linear DAC; programmable mixed, fast and slow current decay modes; 4MHz internal for digital timing Oscillator; Serial Interface Control Chip Function; Low Power Synchronous Rectification; Internal UVLO and Thermal Shutdown Circuitry; Crossover Current Protection; Accurate 2V Reference; Input Compatible with 3.3 V or 5 V Control Signals;

The A3972SB is designed for pulse width modulation (PWM) current control of bipolar microstepping motors, capable of continuous output current to ±1.5 A and operating voltage to 50 V. An internal fixed off-time PWM current-controlled timing circuit can be programmed via the serial interface for slow, fast operation, and mixed current decay modes.

The desired load current level is set via the serial port along with two 6-bit linear DACs and a voltage reference. Six-position control allows maximum flexibility in torque control for various step methods, from micro-stepping to full-step actuation. The load current is set in 1.56% increments of the maximum value.

The synchronous rectification circuit allows the load current to flow through the low rDS(on) of the DMOS output driver during current decay. This feature will eliminate the need for external clamping diodes in most applications, saving cost and external component count while minimizing power dissipation.

Internal circuit protection includes hysteretic thermal shutdown, TVS diode, and cross-current protection. No special power-up sequence is required.

The A3972SB is 24-lead plastic impregnated with copper batwing power tabs (suffix "B"). The power label is at ground potential and does not require electrical isolation.

Functional block diagram

Function description

serial interface. The A3972SB is controlled via a 3-wire (clock, data, strobe) serial port. Programmable features allow maximum flexibility in configuring PWM based on motor drive requirements. Serial data is written as two 19-bit words: 1-bit select word and 18-bit data. Serial data is clocked from D18 .

D1–D6 Bridge 1 Linear DAC. The six-bit word sets the current level required by Bridge 1. Setting all six bits to zero will disable Bridge 1, shutting down all drivers (see the current regulations section of the feature description).

D7–D12 Bridge 2 Linear DACs. The six-bit word sets the current level required by Bridge 2. Setting all six bits to zero will disable Bridge 2, shutting down all drivers (see the current regulations section of the feature description).

D13 Bridge Phase 1. This bit controls the output current direction of Load 1.

D14 Bridge Phase 2. This bit controls the output current direction of Load 2.

D15 Bridge 1 mode.

D16 bridge 2 mode.

D17 reference selection. This bit determines the reference input for the 6-bit linear DAC.

D18 Gm range option. This bit determines the scale factor (4 or 8) used.

D1–D2 blank time. These two bits set the blanking time for the current sense comparator. When the source driver is turned on, current spikes occur due to the reverse recovery current of the clamp diode and/or switching transients related to distributed capacitance in the load. To prevent this current spike from falsely resetting the source enable latch, the sense comparator is masked. The blank timer runs after the off time counter to provide a programmable blank function. When the phase is changed, the blank timer is reset.

D3–D7 fixed off time. These 5 bits set the fixed off time of the internal PWM control circuit. Fixed off hours are defined as follows:

where N=0….31

For example, with a main oscillator frequency of 4MHz, the fast decay time will be adjusted from 1.75µs to 63.75µs in 2µs increments.

D8–D11 Fast decay time. These four bits set the fast decay portion of the fixed off-time of the internal PWM control circuit. The definition of the fast decay part is as follows:

where N=0….15

For example, with an oscillator frequency of 4MHz, the fast decay time can be adjusted from 1.75µs to 31.75µs in 2µs increments. For tfd>toff, the device will effectively operate in fast decay mode.

D12–D13 oscillator control. 4mhz internal oscillator is used for timing functions and charge pump clock. If more precise control is required, an external oscillator can be input to the OSC terminal. To accommodate a wider range of system clocks, an internal divider is provided to generate the required MO frequency according to the following table:

D14-D15 synchronous rectification.

The different operating modes are described in the Synchronous Rectification section of the functional description.

D16, D17. These bits are reserved for testing and should be programmed to zero during normal operation.

D18 idle mode. The device can be put into a low power "idle" mode by writing a "0" to D18. The output will be disabled, the charge pump will be turned off, and the device will draw lower load supply current. The undervoltage monitoring circuit will remain active. D18 should be set high for 1 ms before attempting to enable any output drivers.

VREG. This internally generated supply voltage is used to run the receiver side DMOS output. VREG is internally monitored and in the event of a fault condition, the device outputs are disabled. A 0.22µF capacitor should be used to separate the VREG pin from ground.

current regulations. The reference voltage can be set via the analog input to the reference terminal, or via the internal 2V precision reference. The choice of reference voltage and sense resistor sets the maximum trip current.

The microstepping current level is set according to the following formula:

where the DAC input code is equal to 1 to 63 in a range of 4 or 8, selected by the word 0, D18. Programming the DAC input code to zero disables the bridge and produces a minimum load current.

PWM timer function. The PWM timer can be programmed through the serial port to provide a fixed off-time PWM signal to the control block. In mixed decay mode, the first part of the off time works in fast decay until the fast decay time count is reached, then decays slowly for the rest of the fixed off time period. If the fast decay time is set longer than the off time, the device is effectively operating in fast decay mode.

oscillator. The PWM timer is based on the oscillator input, typically 4mhz. The A3972SB can be configured to select the 4MHz internal oscillator, or, if more precision is required, an external clock can be connected to the OSC terminal. If an external clock is used, three internal divider options can be selected through the serial port to provide flexibility in selecting fOSC based on the available system clock. If the internal oscillator option is used, absolute accuracy depends on the process variation of resistance and capacitance. A precision resistor can be connected from the OSC terminal to VDD to further improve tolerance. The frequency is:

If the internal oscillator is used without an external resistor, the OSC terminal should be grounded.

sleep mode. Input sleep is designed to put the device into a minimum current consumption mode. When pulled low, the serial port will reset to all zeros and all circuits will be disabled.

closure. If a fault occurs due to excessive junction temperature or low VCP or VREG voltage, the output of the device will be disabled until the fault condition is removed. On power-up, or in the case of low VDD, the UVLO circuit disables the driver and resets the data in the serial port to zero.

Synchronous rectification. When a PWM off cycle is triggered by a bridge disable command or an internal fixed off time period, the load current is recirculated according to the decay mode selected by the control logic. The A3972SB synchronous rectification function will turn on the corresponding MOSFET during current decay and effectively short the body diode using a low rDS(on) driver. This will significantly reduce power dissipation and eliminate the need for external Schottky diodes for most applications.

Two serial port control bits can configure four different modes of operation:

1. Active mode. When a zero current level is detected, the load current is prevented from reversing by turning off the synchronous rectification.

2. Passive mode. Reverse current is allowed, but if the load current rises in the opposite direction to the current limit, the synchronous rectification circuit is turned off.

3. Disabled. No MOSFET switching occurs during load recirculation. This setup can only be used with the four external clamping diodes per bridge.

4. Only the lower side. The low-side MOSFET will turn on during turn-off, shorting the current path through the MOSFET body diode. In this setup, the high-end mosfet will not be synchronously rectified, so four external diodes from the output to the power supply are recommended. This mode is suitable for high power applications wishing to save the expense of two external diodes per bridge. In this mode, the slot-side MOSFETs are switched off during the PWM off-time. In all other cases, the source mosfet is switched off in response to the PWM shutdown command.

current sensing. To minimize inaccurate IPEAK current level sensing due to IR drop in the ground trace, the sense resistor should have a separate ground return to the device ground terminal. For low value sense resistors, the IR drop in the PCB trace of the sense resistor may be significant and should be considered. Sockets should be avoided as the contact resistance of the sockets can cause variations in RS.

Thermal Protection. Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from failure due to excessive junction temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.

Serial port write timed operation. Data is clocked in the shift register on the rising edge of the clock signal. Normally, the strobe will remain high and only decrease when a write cycle is initiated. Data is written MSB first, followed by the word select bit. See the serial port diagram for timing requirements.

layout. Printed wiring boards should use heavy duty ground planes. For best electrical and thermal performance, the driver should be soldered directly to the board. The ground side of RS should have a separate path to the driver ground pin. This path should be as short as possible and should not connect any other components. The load supply pin, VBB, should be separated from an electrolytic capacitor (greater than 47µF recommended) placed as close to the driver as possible.

Dimensions in inches (control dimer)

Note: 1. Mesh lead frame. Conductors 6, 7, 18 and 19 are internally integral.

2. Lead spacing tolerances are non-cumulative.

3. Within the limits shown, the exact body and lead configuration is selected by the supplier.

4. Supplied in standard rods/tubes of 15 units.

Dimensions are in mm (for reference only)

Note: 1. Mesh lead frame. Conductors 6, 7, 18 and 19 are internally integral.

2. Lead spacing tolerances are non-cumulative.

3. Within the limits shown, the exact body and lead configuration is selected by the supplier.

4. Supplied in standard rods/tubes of 15 units.

The products described herein are manufactured under one or more US patents or US patents pending.

Allegro MicroSystems, Inc. reserves the right to deviate from detailed specifications at any time to improve the performance, reliability or manufacturability of its products. Before placing an order, the user is reminded to confirm that the information relied upon is up to date.