feature

Fast 12-bit ADC with 1.6s conversion time; 8 single-ended analog input channels Overvoltage protection on each channel Selection of input ranges: 5 V, 10 V for AD7891-1 ; 0 to +2.5 V, 0 to + 5 V, 2.5 V for AD7891-2; parallel and serial interfaces; on-chip track/hold amplifier; on-chip reference; single supply, low power operation ( 100 mW max); power down mode (75 W typical).

application

Data acquisition system; motor control; mobile communication base station; instrument.

General Instructions

The AD7891 is an 8-channel 12-bit data acquisition system with a choice of parallel or serial interface structure. This section includes the input multiplexer, on-chip track/hold amplifier, high-speed 12-bit ADC, 2.5v reference, and high-speed interface. The part is powered by a 5 V supply and is available in two versions of the AD7891-1 (±5 V and ±10 V) and AD7891-2 (0 V to +2.5 V, 0 V to +5 V and ±2.5 V) accepts various analog input ranges.

The AD7891 offers a choice of parallel or serial interface structure determined by the mode pins. The part features standard control inputs and fast data access times for both serial and parallel interfaces, ensuring easy interfacing with modern microprocessors, microcontrollers and digital signal processors.

In addition to traditional DC accuracy metrics such as linearity, full scale, and offset error, this section specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

The power consumption in normal mode is a typical 82mw; in standby mode, the power consumption is reduced to a typical 75mw. This part is available for 44 terminal MQFP and 44 lead PLCC.

Product Highlights

1. AD7891 is a complete monolithic 12-bit data acquisition system, which integrates 8-channel multiplexer, 12-bit ADC, 2.5V reference voltage and track/hold amplifier on a single microcontroller.

2. The AD7891-2 has a conversion time of 1.6 ms and an acquisition time of 0.4 ms. This allows for a sampling rate of 500 kSPS when sampling one channel and 62.5 kSPS when channel hopping. These sample rates can be achieved by software or hardware conversion initiation. The AD7891-1 has an acquisition time of 0.6 ms when initiated using a hardware conversion and 0.7 ms when initiated using a software conversion. These acquisition times allow hardware and software conversions to be initiated at sample rates of 454.5 kSPS and 435 kSPS, respectively.

3. Each channel on AD7891 has overvoltage protection. This means that overvoltages on unselected channels will not affect transitions on selected channels. The AD7891-1 can withstand overvoltages of ±17 V.

the term

signal to noise ratio

This is the ratio of signal to (noise + distortion) measured at the ADC output. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fS/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio (noise + distortion) of an ideal N-bit converter with a sine wave input is given by the signal-to-noise ratio (noise + distortion) = (6.02N + 1.76) dB, so for a 12-bit converter this is 74dB.

Total Harmonic Distortion (THD)

THD is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7891, it is defined as:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it is the noise peak.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3, etc. The intermodulation term refers to the intermodulation term for which both m and n are not equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), while third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7891 is tested using the CCIF standard using two input frequencies near the top of the input bandwidth. In this case, the second and third order terms have different meanings. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second and third order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dBs.

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. Measured by applying a full-scale 20 kHz (AD7891-1) or 100 kHz (AD7891-2) sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The numbers given are the worst of all 8 channels.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measurement between any two adjacent codes in the ADC and the ideal 1 LSB change.

Positive Full-Scale Error (AD7891-1, 10 V and 5 V; AD7891-2, 2.5 V)

This is the deviation of the last code transition (01.110 to 01.111) after adjusting for bipolar zero error, from the ideal 4¥REF IN – 3/2 LSB (AD7891-1±10 V range), 2¥REF IN–3/2 LSB (AD7891-1 ±5 V range) or REF IN–3/2 LSB (AD7891-2, ±2.5 V range).

Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the last code transition (11.110 to 11.111) after adjusting for unipolar offset error, from the ideal 2$REF IN–3/2 LSB (0 V to 5 V range) or REF IN–3 /2 LSB (0 V to 2.5 V range).

Bipolar Zero Error (AD7891-1, 10 V and 5 V; AD7891-2, 2.5 V)

This is the deviation of the mesoscale transformation (all 0s to all 1s) from ideal AGND – 1/2 LSB.

Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the first code transition (00.000 to 00.001) from ideal AGND + 1/2 LSB.

Negative Full-Scale Error (AD7891-1, 10 V and 5 V; AD7891-2, 2.5 V)

This is the deviation of the first code transition (10.000 to 10.001) after adjusting for bipolar zero error, from the ideal -4¥REF IN+1/2 LSB (AD7891-1±10 V range), -2 $REF IN+1/2 LSB (AD7891-1 ±5 V range) or -REF IN+1/2 LSB (AD7891-2, ±2.5 V range).

Track/Hold Acquisition Time

Track/hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 LSB) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a change in the selected input channel, or when there is a step input change in the input voltage applied to the selected VIN input of the AD7891. This means that the user must wait for the duration of the track/hold acquisition time after a conversion has ended or after a channel change/step input change to VIN before starting another conversion to ensure the part is operating to specification.

Converter Details

The AD7891 is an 8-channel, high-speed, 12-bit data acquisition system. It provides users with signal scaling, multiplexing, track/hold, reference, ADC, and logic functions for high-speed parallel and serial interfaces. Signal conditioning on the AD7891-1 allows the part to accept an analog input range of ±5 V or ±10 V when operating from a single supply. The input circuitry on the AD7891-2 allows the part to again handle input signal ranges of 0 V to +2.5 V, 0 V to +5 V, and ±2.5 V when operating from a single 5 V supply. The part requires a reference voltage of 2.5 V, which can be supplied from the part's own internal reference voltage or from an external reference voltage source.

Conversions are initiated on the AD7891 by pulsing the CONVST input or by writing a logic 1 to the SWCONV bit of the control register. When using the hardware CONVST input, the on-chip track/hold goes from track to hold mode, and the conversion sequence begins on the rising edge of the CONVST signal. When a software conversion start is initiated, an internal pulse is generated, delaying the track/hold acquisition point and conversion start sequence until the pulse times out. This internal pulse (low to high) is initiated whenever a 1 in the SWCONV bit is written to the AD7891 control register. Then start to discharge, track/hold cannot go into hold, and conversion cannot start until the pulse signal goes low. The internal pulse duration is equal to the track/hold acquisition time. This allows the user to obtain valid results after changing the channel and initiating the conversion in the same write operation.

The conversion clock for this part is internally generated, and the AD7891's conversion time is 1.6 ms from the rising edge of the hardware CONVST signal. The track/hold capture time of the AD7891-1 is 600 ns, while the track/hold capture time of the AD7891-2 is 400 ns. For best performance from the part, data read operations should not occur during a conversion or during the 100 ns before the next conversion. This enables the AD7891-1 to operate at throughput rates up to 454.5 kSPS, while the AD7891-2 can operate in parallel mode at throughput rates up to 500 kSPS and achieves the data sheet specification. In serial mode, the maximum achievable throughput of the AD7891-1 and AD7891-2 is 357 kSPS (assuming a 20 MHz serial clock).

All unused analog inputs should be connected to a voltage within the nominal analog input range to avoid noise pickup. For minimum power dissipation, unused analog inputs should be connected to AGND.

interface information

The AD7891 offers two interface options, a 12-bit parallel interface and a high-speed serial interface. The desired interface mode is selected via the mode pin. These two interface modes will be discussed in the following sections.

Parallel interface mode

The parallel interface mode is selected by tying the mode input to a logic high level. Figure 2 shows a timing diagram of the sequence of operations of the AD7891 in parallel mode for hardware conversion initiation. The multiplexer address is written to the AD7891 on the rising edge of the WR input. On-chip track/hold enters hold mode on the rising edge of CONVST; conversion also begins at this point. When the conversion is complete, the end of the conversion line (EOC) is pulsed low to indicate that new data is available in the AD7891's output register. This EOC line can be used to drive edge-triggered interrupts to the microprocessor. CS and RD go low to access the 12-bit conversion result. In systems where this part interfaces with a gate array or ASIC, this EOC pulse can be applied to the CS and RD inputs to latch data from the AD7891 into the gate array or ASIC. This means that the gate array or ASIC does not require any transition state recognition logic, and it also eliminates the logic required in the gate array or ASIC to generate the read signal for the AD7891.

serial interface mode

The serial interface mode is selected by connecting the mode input to a logic low level. In this case, the five data/control inputs in parallel mode assume the serial interface function.

The serial interface on the AD7891 is a 5-wire interface with read and write functions. Data is read from the output register through the data output line, and data is written into the control register through the data input line. The part operates in slave or external clock mode and requires an externally applied serial clock to the SCLK input to access data in the data register or write data to the control register. There are separate framing signals for read (RFS) and write (TFS) operations. The serial interface on the AD7891 is designed to allow the part to be connected to systems that provide a serial clock synchronized with serial data, such as the 80C51, 87C51, 68HC11, and 68HC05, and most digital signal processors.

When using the AD7891 in serial mode, the data lines DB11 to DB10 should be connected to logic low and the CS, WR, and RD inputs should be connected to logic high. Pins DB4 to DB0 can be tied to logic high or logic low, but cannot be left floating as this condition could cause the AD7891 to draw significant current.

read operation

Figure 3 shows the timing diagram for reading data from the AD7891 in serial mode. RFS is low enough to access data from the AD7891. The serial clock input does not have to be continuous. Serial data can be accessed in bytes. However, during data transfer operations, RFS must be kept low. The 16-bit data is transmitted in serial mode, the data format bit is first, the 3 address bits in the control register are last, and the 12-bit conversion result starts from the MSB. Serial data is clocked from the device on the rising edge of SCLK and is valid on the falling edge of SCLK. At the end of a read operation, the data output line is represented by three rising edges on the SCLK or RFS input, whichever occurs first.

write operation

Figure 4 shows a write to the AD7891's control register. The TFS input goes low to indicate the portion of the serial write that will occur. The AD7891 control register requires only 6 bits of data. They are loaded on the first six clock cycles of the serial clock, ignoring data on all subsequent clock cycles. Serial data to be written to the AD7891 must be valid on the falling edge of SCLK.

Simplified serial interface

To minimize the number of interconnect lines to the AD7891 in serial mode, the user can connect the RFS and TFS lines of the AD7891 together while reading and writing from the part. In this case, a new control register data line that selects the input channel and provides a conversion start command should be provided on the data input line, while this section provides the result of the just completed conversion on the data output line.

Circuit Description Reference

The AD7891 includes a reference pin labeled REF OUT/REF, which provides access to the part's own 2.5V internal reference, or connects to an external 2.5V reference to provide the part's reference voltage source. This part is specified for a 2.5 V reference voltage. Errors in the reference source cause gain errors in the AD7891's transfer function and add to the full-scale errors specified on the part. They also cause offset errors injected into the attenuator stage.

The AD7891 includes an on-chip 2.5 volt reference. To use this reference as a reference source for the AD7891, simply connect a 0.1 mF disk ceramic capacitor from the REF OUT/REF IN pins to REF GND. REFGND should be connected to AGND or the analog ground plane. The voltage appearing on the REF OUT/REF IN pins is buffered internally before being applied to the ADC. If the reference needs to be used outside the AD7891, it should be buffered because the part has a FET switch in series with the reference, resulting in a nominal 2 kW source impedance for this output. At 25∞C, the internal reference has a tolerance of ±10 mV, a typical temperature coefficient of 25 ppm/∞C, and a maximum temperature error of ±20 mV.

If the application requires a reference with tighter tolerances, or if the AD7891 needs to be used with a system reference, an external reference can be connected to the REF OUT/REF IN pins. The external reference overdrives the internal reference, providing a reference source for the ADC. The reference input is buffered before being applied to the ADC, and the maximum input current is ±100mA. References suitable for use with the AD7891 include the AD580, AD680, AD780, and REF43 precision 2.5V references.

Analog input section

There are two types of AD7891: AD7891-1, each input can be configured for ±10 V or ±5 V input range; AD7891-2, each input can be configured for 0 V to +2.5 V, 0 V to +5 V and ±2.5 V input range.

AD7891-1

Figure 5 shows the analog input section of the AD7891-1. Each input can be configured for ±5 V or ±10 V operation. For 5V operation, the VINXA and VINXB inputs are connected together and the input voltage is applied to both. For ±10 V operation, the VINXB input is tied to AGND and the input voltage is applied to the VINXA input. VINXA and VINXB inputs are symmetrical and fully interchangeable. Therefore, to facilitate PCB layout in the ±10 V range, the input voltage can be applied to the VINXB input when the VINXA input is tied to AGND.

The input resistance for the ±5 V range is typically 20 kW. For a ±10 V input range, the input resistance is typically 34.3 kW. The resistive input stage is followed by a multiplexer, which is followed by the high input impedance stage of the track/hold amplifier.

The designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). The LSB size is given by Equation 1, LSB=FS/4096. Therefore, for the ±5 V range, 1 LSB=10 V/4096=2.44 mV. For the ±10 V range, 1 LSB=20 V/4096=4.88 mV. The output encoding is determined by the format bits in the control register. The ideal input/output code conversion is shown in Table 1.

AD7891-2

Figure 6 shows the analog input section of the AD7891-2. Each input can be configured for an input range of 0 V to +5 V, 0 V to +2.5 V, or ±2.5 V. For the 0 V to 5 V input range, the VINXB input is tied to AGND and the input voltage is applied to the VINXA input. For an input range of 0 V to 2.5 V, the VINXA and VINXB inputs are connected together and the input voltage is applied to both. For the ±2.5 V input range, the VINXB input is tied to 2.5 V and the input voltage is applied to the VINXA input. The 2.5 V supply must have low output impedance. If using the internal references on the AD7891, the

VINXB. VINXA and VINXB inputs are symmetrical and fully interchangeable. Therefore, to facilitate PCB layout in the 0 V to +5 V or ±2.5 V range, the input voltage can be applied to the VINXB input while the VINXA input is tied to AGND or 2.5 V.

The input resistance for the 0 V to +5 V and ±2.5 V ranges is typically 3.6 kW. When the input is configured for 0 V to 2.5 V operation, the input is fed into the high impedance stage of the track/hold amplifier through a multiplexer and two parallel 1.8 kW resistors.

The designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). The LSB size is given by Equation 1, LSB=FS/4096. Therefore, for the 0 V to 5 V range, 1 LSB=5 V/4096=1.22 mV; for the 0 V to 2.5 V range, 1 LSB=2.5 V/4096=0.61 mV; for the ±2.5 V range, 1 LSB=5 V/4096=1.22mV. The output encoding is determined by the format bits in the control register. Table 1 shows the ideal input/output code conversion over the ±2.5 V range. Table II shows the ideal input/output transcoding for the 0 V to 5 V range and the 0 V to 2.5 V range.

notes

1. The output code format is determined by the format bits in the control register.

2. FSR is the full-scale range, +20 V within ±10 V, +10 V for ±5 V, +5 V for ±2.5 V, REF IN=+2.5 V.

3. LSB=FSR/4096=+4.88 mV (±10 V range), +2.44 mV (±5 V range) and +1.22 mV (±2.5 V range), reference voltage=+2.5 V.

4. ±0 V range, ±5 V range, or ±2.5 V range.

notes

1. The output code format is determined by the format bits in the control register.

2. FSR is full scale range, 0 to 5 V range is 5 V, 0 to 2.5 V range is 2.5 V, REF IN=2.5 V.

3. LSB=FS/4096=1.22 mV (0 to 5 V range) or 610 mV (0 to 2.5 V range), reference voltage=2.5 V.

4. 0 V to 5 V range or 0 V to 2.5 V range.

Transfer Function of AD7891-1 and AD7891-2

The transfer function of the AD7891-1 and AD7891-2 can be expressed as:

D is the output data from the AD7891 at 0 to 4095 for direct binary encoding and from -2048 to +2047 for two's complement. The value of M depends on the input voltage range. The value of N depends on the input voltage range and output data format. These values are in Table III. REF IN is the reference voltage applied to the AD7891.

Track/Hold Amplifier

The track/hold amplifier on the AD7891 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. Even at the ADC's maximum throughput of 454khz (AD7891-1) or 500khz (AD7891-2), the track/hold input bandwidth is greater than the ADC's Nyquist rate. In other words, the track/hold amplifier can handle input frequencies in excess of 227 kHz (AD7891-1) or 250 kHz (AD7891-2).

The track/hold amplifier takes an input signal of 600 ns (AD7891-1) or 400 ns (AD7891-2). The operation of tracking/holding is basically transparent to the user. The track/hold amplifier goes from its track mode to its hold mode on the rising edge of CONVST. The aperture time for track/hold (i.e. the delay between the external CONVST signal and the track/hold actually entering the hold) is typically 15ns. At the end of the conversion, the part returns to its tracking mode. At this point the track/hold starts to acquire the next signal.

Alternate action

The AD7891 can enter a power-saving or standby mode by using the alternate pins or the SWSTBY bit of the control register. Normal operation of the AD7891 occurs when the alternate input is at logic 1 and the SWSTBY bit is at logic 0. When the standby pin goes low or a 1 is written to the SWSTBY bit, the part enters standby mode of operation, reducing its power consumption to a typical 75mW.

When the spare item input is at logic 1, the SWSTBY bit is logic 0. The wake-up time of the AD7891 is typically determined by the amount of time required to charge the 0.1 mF capacitor between the REF OUT/REF IN pin and REF GND. If the internal reference is used as the reference source, this capacitor is charged through the nominal 2kW resistor. Assuming 10 time constants to charge the capacitor to 12-bit accuracy, this means a wake-up time of 2 ms.

If an external reference is used, this must be taken into account when calculating how long the capacitor will take to charge. If the external reference voltage remains at 2.5 V while the AD7891 is in standby mode, the capacitor will already be charged when the part comes out of standby mode. Therefore, the wake-up time is now the time required for the AD7891's internal circuitry to achieve 12-bit accuracy. This usually takes 5 ms. If the external reference is also placed in standby, the wake-up time of the reference, plus the time required to charge the reference capacitor from the external reference, determines how much time must elapse before the conversion can resume.

Microprocessor Interface AD7891 to 8X51 Serial Interface

The serial interface between the AD7891 and the 8X51 microcontroller is shown in Figure 7. The TXD of the 8X51 drives the SCLK of the AD7891, while the RXD sends data to and

Receive data from parts. The serial clock speed of the 8X51 is slow compared to the maximum serial clock speed of the AD7891, so this interface cannot achieve the maximum throughput of the AD7891.

The 8X51 provides the LSB of its SBUF register as the first bit in the serial data stream. The AD7891 needs to be written to the 6-bit MSB first. Therefore, the data in the SBUF register must be properly arranged to take it into account. P3.3 is taken low when data is being transferred to the part. The 8X51 transmits its data in 8-bit bytes with only 8 falling clock edges during the transmission cycle. Writing data to the AD7891's control register requires an 8-bit transfer. After the data transfer is complete, the P3.3 line will go high to complete the transfer.

When reading data from AD7891, P3.4 of 8X51 is taken low. The 8X51 performs two 8-bit serial reads and sets P3.4 high to complete the transfer. Again, the 8X51 needs the LSB first, while the AD7891 sends the MSB first, so this must be accounted for in the 8X51 software.

There is no specification in a given interface when the transition ends. If the conversion is software-initiated, the 8X51 can wait a predetermined amount of time before reading valid data. Alternatively, the falling edge of the EOC signal can be used to initiate an interrupt service routine that reads the result of a conversion from one part to another.

AD7891 to 68HC11 Serial Interface

Figure 8 shows the serial interface between the AD7891 and the 68HC11 microcontroller. The SCK of the 68HC11 drives the SCLK of the AD7891, the MOSI output drives the data input of the AD7891, and the MISO input receives data from the data of the AD7891. Ports PC6 and PC7 of the 68HC11 drive the TFS and RFS lines of the AD7891, respectively.

For proper operation of this interface, the 68HC11 should be configured so that its CPOL bit is 1 and the CPHA bit is 0. PC7 is taken low when data is to be transferred to the AD7891. When data is to be received from the AD7891, PC6 is taken low. The 68HC11 first transmits and receives serial data in 8-bit bytes (MSB). The AD7891 also transmits and receives data MSB first. Eight falling clock edges occur during a read or write cycle of the 68HC11. With PC7 low, an 8-bit write operation is required to write to the control register. When data is written, PC7 is taken high. When reading from the AD7891, PC6 is held low after the first 8 bits have been read. Then, the second byte of data is sent serially from the AD7891. After this transfer is complete, the PC6 line will be high.

As shown in the 8X51 circuit in Figure 7, the way the 68HC11 is told that the conversion is complete is not shown in the figure. The EOC line can be used to notify the 68HC11 that a conversion is complete by using it as an interrupt signal. The interrupt service routine reads the conversion result. If initiated with a software conversion, the 68HC11 can wait 2.0 ms (AD7891-2) or 2.2 ms (AD7891-1) before reading the AD7891.

AD7891 to ADSP-21xx Serial Interface

The interface between the AD7891 and the ADSP-21xx is shown in Figure 9. In the interface shown, data can be transferred to the AD7891 using SPORT0 or SPORT1. When reading from the part, the motion must set a serial word length of 16 bits. Serial word lengths of 6 bits or more can be used when writing to the AD7891. Additional settings for the serial interface on the ADSP-21xx internal SCLK use alternate framing modes and active low framing signals. Typically, the EOC line from the AD7891 will be connected to the IRQ2 line of a DSP-21xx to interrupt the DSP at the end of a conversion (not shown in the figure).

AD7891 to DSP5600x Serial Interface

Figure 10 shows the AD7891 and DSP5600x family of DSPs. When reading data from the AD7891, the DSP5600x should be set up for 16-bit data transfer, MSB first, normal mode synchronous operation, internally generated word frame synchronization, and gated clock. When writing to the AD7891, either 8-bit or 16-bit data transfers can be used. The frame sync signal from the DSP5600x must be inverted before being applied to the RFS and TFS inputs of the AD7891, as shown in Figure 10.

To monitor the conversion time of the AD7891, schemes such as those previously outlined in Interfacing with the EOC can be used. This can be achieved by connecting the EOC line directly to the IRQA input of the DSP5600x.

AD7891 to TMS320xxx Serial Interface

The AD7891 can be connected to the serial port of TMS320xxx DSPs as shown in Figure 11. The external timing generation circuit is the interface necessary to generate the serial clock and synchronization.

Parallel interface

The parallel port on the AD7891 allows the device to be connected to a microprocessor or DSP processor as a memory-mapped or I/O-mapped device. The CS and RD inputs are common to all memory peripheral interfaces. Typical interfaces for different processors are shown in Figures 12 to 15. In all interfaces shown, an external timer controls the CONVST input of the AD7891 and the EOC output interrupts the host DSP.

AD7891 to ADSP-21xx

Figure 12 shows the AD7891 connected as a memory-mapped device to an ADSP-21xx family of DSPs. Depending on the clock speed of the DSP, interfacing the AD7891 to the ADSP-21xx may require a wait state. This wait state is programmable through the ADSP-21xx's data memory wait state control registers (see the ADSP-2100 Series User Manual for details). The following instructions read data from the AD7891.

MR = DM (ADC)

where ADC is the address of the AD7891.

AD7891 to TMS32020, TMS320C25 and TMS320C5x

The parallel interface between AD7891 and TMS32020, dsp of TMS320C25 and TMS320C5x series is shown in Figure 13. The memory map address chosen for the AD7891 should fall within the I/O memory space of the DSP.

Parallel interface

The parallel interface on the AD7891 is fast enough to interface with the TMS32020 without additional wait states. If high-speed glue logic (such as a 74AS device) is used to drive the WR and RD lines when interfacing with the TMS320C25, wait states are not required. However, with slower logic, data access may slow down to the point where a wait state needs to be inserted when reading and writing the part. In this case, the wait state can be generated using a single OR gate combining the CS and MSC signals to drive the ready line of the TMS320C25, as shown in Figure 13. Additional wait states are required when using the TMS320C5x at the fastest clock speeds. Wait states are programmable through the IOWSR and CWSR registers (see the TMS320C5x User's Guide for details).

Data is read from the ADC using the following instruction: at D, ADC, where D is the memory location where the data is stored and ADC is the I/O address of the AD7891.

AD7891 to TMS320C3x

Figure 14 shows the parallel interface between the AD7891 and the TMS320C3x family of dsp. The AD7891 interfaces to the expansion bus of the TMS320C3x. This interface requires a single wait state. This can be programmed using the WTCNT bits of the Expansion Bus Control Register (see the TMS320C3x User Guide for details). Data from the AD7891 can be read using the following instructions: Local Design Institute ¥ , ARn receive, where ARn is an auxiliary register containing the lower 16 bits of the AD7891 address in the TMS320C3x memory space, and Rx is the register that loads the ADC data.

AD7891 to DSP5600x

Figure 15 shows the parallel interface between the AD7891 and the DSP5600x family of DSPs. The AD7891 should be mapped to the first 64 locations of Y data memory. If additional wait states are required for this interface, they can be programmed using the Port A bus control registers (see the DSP5600x User Manual for details). Data can be read from the AD7891 using the following instruction: move: ADC, X0, where ADC is the address in the DSP5600x address space to which the AD7891 is mapped.

Power Bypass and Ground

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure the specified performance. The printed circuit board on which the AD7891 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of easily separated ground planes. The minimum etch technique is usually best for the ground plane because it provides the best shielding. Digital and analog ground can only be connected in one place. If the AD7891 is the only device that requires an AGND to DGND connection, the ground plane should be connected at the AGND and DGND pins of the AD7891. If the AD7891 is in a system where multiple devices require an AGND to DGND connection, it should still be connected at only one point, a star ground point as close as possible to the AD7891.

Digital lines under the device should be avoided as these coupled noises can affect the die. The analog ground should be allowed to run under the AD7891 to avoid noise coupling. The power lines to the AD7891 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never run near analog inputs. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best technology, but not always possible with double sided. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

The AD7891 should have adequate power supply bypassing as close to the package as possible, ideally right against the device. One of the VDD pins (pin 10 for the PLCC package and pin 4 for the MQFP package) mainly drives the analog circuitry on the chip. This pin should be separated from the analog ground plane and connected in parallel with a 10µf tantalum bead capacitor and a 0.1µf capacitor in parallel. The other VDD pin (pin 19 on the PLCC package and pin 13 on the MQFP package) is mainly driven

digital circuits on a chip. This pin should be separated from the digital ground plane using a 0.1 mF capacitor. 0.1 mF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transients caused by internal logic switching current. Figure 16 shows the recommended decoupling scheme.

AD7891 performance linearity

The linearity of the AD7891 is primarily determined by the on-chip 12-bit DAC. This is a segmented DAC that is laser trimmed to 12-bit integral linear and differential linear. The typical INL of the AD7891 is ±0.25 LSB and the typical DNL is ±0.5 LSB.

noise

In ADCs, noise manifests itself as code uncertainty in dc applications and as a noise floor in ac applications (such as in FFTs). In sampling a dc (like the AD7891), from dc to half the sampling frequency, all information about the analog input appears in baseband. The input bandwidth of the track/hold amplifier exceeds the Nyquist bandwidth, so in applications where such signals are present, an antialiasing filter should be used to remove unwanted signals above fS/2 from the input signal.

Figure 17 shows a histogram of 16384 conversions of a dc input signal using the AD7891-1. The analog input is set at the center of the transcoding as follows. An initial DC input level was selected and multiple conversions were made. Record the resulting histogram and adjust the applied level so that only two codes with equal occurrences are generated. This indicates that the transition point between the two codes has been found. The voltage level at which this occurs is recorded. The other edge of one of the two codes is found in a similar way. Then, the dc level at the center of the code can be calculated as the average of the two transition levels. The AD7891-1 input is configured for a ±5 V input range, and after conversion, data is read from the part in parallel mode. Similar results were found over the ±10 V range of the AD7891-1 and all input ranges of the AD7891-2. The same performance is achieved in serial mode, again with the data read from the AD7891-1 after conversion. All but 3 codes appear in one output bin, which indicates good noise performance of the ADC.

Dynamic performance

The AD7891 includes an on-chip track/hold amplifier that allows the section to sample input signals up to 250 kHz on any of its input channels. Many applications of the AD7891 require it to be sequenced through eight channels of low frequency input signals. However, for some applications, the dynamic performance of the converter on signals up to 250 kHz input frequency is of concern. For these wider bandwidth signals, it is recommended to use hardware conversion to start sampling.

These applications require information about the spectral content of the input signal. Signal-to-noise ratio (noise + distortion), total harmonic distortion, peak harmonics or noise, and intermodulation distortion are specified. Figure 18 shows an FFT plot of a typical 10 kHz, ±10 V input, digitized after the AD7891-1 was operating at 500 kHz, with the input connected for ±10 V operation. The signal-to-noise ratio is 72.2db, and the total harmonic distortion is -87db. Figure 19 shows an FFT plot of a typical 100 kHz, 0 V to 5 V input with the input connected for 0 V to 5 V operation after the AD7891-2 is operating at 500 kHz. The signal-to-noise ratio is 71.17db, and the total harmonic distortion is -82.3db. It should be noted that taking part readings during conversion does have a significant impact on dynamic performance. Therefore, for sampling applications, it is recommended not to read during conversion.

significant digits

The formula for signal-to-noise ratio (noise + distortion) (see the Terminology section) is related to the resolution or number of bits of the converter. The rewritten formula gives a performance measure in effective number of bits (ENOB).

where SNR is the signal-to-noise ratio.

A device's effective number of bits can be calculated from its measured signal-to-noise ratio. Figure 20 shows a typical plot of effective bits versus frequency for the AD7891-1 and AD7891-2 from dc to 200 kHz. The sampling frequency is 500khz. The AD7891-1 inputs are configured for ±10 V operation. The AD7891-2 inputs are configured for 0 to 5 V operation. The AD7891-1 graph is only 100 kHz because there is not a good enough quality ±10 V sine wave at higher frequencies.

Figure 20 shows the AD7891-1 converting a 100 kHz input sine wave to an effective number of bits of 11, which equates to a (noise + distortion) level signal of 68.02 dBs. The AD7891-2 converts a 200 kHz input sine wave to an effective number of bits of 11.07, which equates to a signal-to-(noise + distortion) level of 68.4 dBs.

Dimensions

44 Lead Plastic Leaded Chip Carrier (P-44A)

Dimensions are in inches and (mm)