feature

Micropower - 100 A; single supply - 2.7 V to 5.5 V operation; compact 1.75 mm high SO-8 package and 1.1 mm high TSSOP-8 package; AD7390 - 12-bit resolution; AD7391 - 10-bit resolution; and Schmitt-compatible SPI and QSPI serial interfaces; trigger input.

application

Automotive 0.5 V to 4.5 V output span voltage; portable communications; digitally controlled calibration.

General Instructions

The AD7390/AD7391 family of 10-bit and 12-bit voltage output digital-to-analog converters are designed to operate from a single 3V supply. Fabricated using the CBCMOS process, these monolithic DACs offer users low cost and ease of use in a single supply 3V system. Operation is guaranteed over a supply voltage range of 2.7 volts to 5.5 volts, and power consumption is less than 100 microamps making this device ideal for battery-powered applications.

The full-scale voltage output is externally referenced to the input voltage. Rail to rail to DACOUT allows the full-scale voltage to be set to positive supply VDD or any value in between.

The double-buffered serial data interface provides high speed, 3-wire, SPI and microcontroller compatible input (SDI), clock (CLK) and load strobe (LD) pins using data. Alternatively, the CLR input is available at power up or upon user request.

Both parts are available with the same pins to allow users to choose the number of circuit card redesigns that work for their resolution.

The AD7390/AD7391 are specified over the extended industry (40°C to 85°C) temperature range. The AD7391AR is specified over the 40°C to 125°C automotive temperature range. The AD7390/AD7391s are available in plastic impregnated and low profile 1.75mm high SO-8 surface mount packages. The AD7391ARU is suitable for ultra-thin applications in a 1.1 mm TSSOP-8 package.

AD7390/AD7391 – Typical Performance Characteristics

operate

The AD7390 and AD7391 are a set of pin-compatible 12-bit/10-bit digital-to-analog converters. Operating over a supply voltage range of 2.7V to 5.5V, these single-supply operated devices draw less than 100 microamps of current, making them ideal for battery-powered applications. They contain a voltage switch, 12-bit/10-bit, laser-trimmed digital-to-analog converter, rail-to-rail output op amps, serial input registers, and a DAC register. The external reference input has a constant input resistance, independent of the DAC's digital code setting. Additionally, the reference input can be tied to the same supply voltage as VDD, resulting in a maximum output voltage span of 0 to VDD. The SPI-compatible serial data interface consists of serial data input (SDI), clock (CLK), and load (LD) pins. The CLR pin can be used to reset the DAC registers to zero scale. This feature can be used to restore a power-on reset or system failure to a known state.

D/A Converter Section

The voltage switching R-2R DAC generates an output voltage from an external reference connected to the VREF pin according to the following equation:

where D is the decimal data word loaded into the DAC register and N is the number of bits of DAC resolution. Using the 10-bit AD7391 with a 2.5 V reference in this case, Equation 1 simplifies to:

Using Equation 2, when D=512, the nominal mid-scale voltage of VOUT is 1.25 V; the full-scale voltage is 2.497 V. The LSB step size is = 2.5 1/1024 = 0.0024 V.

For the 12-bit AD7390 operating from a 5.0V reference, Equation 1 becomes:

Using Equation 3, the AD7390 provides a nominal mid-scale voltage of 2.5 V and a full-scale output of 4.998 V at D=2048. The LSB step size is = 5.0 1/4096 = 0.0012 V.

Amplifier section

The output of the internal DAC is buffered by a low-power precision amplifier. The typical settling time for an op amp is 60 microseconds to 0.1% of full scale. The settling time of the negative slew signal and the positive slew signal is slightly different. In addition, the negative transition settling time within the last 6 lsbs of zero volts has an extended settling time. The amplifier's rail-to-rail output stage is designed to provide precise performance when operating near either supply. Figure 5 shows the equivalent output schematic of a rail-to-rail amplifier with an N-channel pull-down FET that pulls the output load directly to GND. The output source current is provided by a P-channel pull-up device that can source current to ground.

The rail-to-rail output stage provides ±1mA of output current. The N-channel output pull-down MOSFET shown in Figure 5 has an on-resistance of 35Ω, which sets the leakage current capability close to ground. In addition to resistive load drive capability, the amplifier is designed to drive capacitive loads up to 100 pF.

reference input

The reference input has constant input resistance independent of the digital code, which reduces glitches on external reference voltage sources. The high 2 MΩ input impedance minimizes power dissipation within the AD7390/AD7391 D/A converters. The VREF input accepts an input voltage from ground to the positive supply voltage VDD. One of the easiest applications to save an external reference voltage source is to connect the VREF terminal to the positive VDD supply. This connection results in a rail-to-rail voltage output span that maximizes the programming range. The reference inputs will accept AC signals as long as they remain within the supply voltage range, 0

power supply

The extremely low power consumption of the AD7390/AD7391 is a direct result of the circuit design optimized for the use of the CBCMOS process. Good analog accuracy is obtained by exploiting the low power consumption of CMOS and the low noise and tight matching of complementary bipolar transistors. One advantage of the rail-to-rail output amplifier used in the AD7390/AD7391 is the wide range of available supply voltages. The part is fully specified and tested for operation over a voltage range of 2.7 V to 5.5 V.

Power Bypass and Ground

Precision analog products, such as the AD7390/AD7391, require a well-filtered power supply. Since the AD7390/AD7391 are powered from a 3V to 5V supply, it seems convenient to tap into the digital logic power supply. Unfortunately, logic power supplies are usually a switch-mode design, which produces noise in the 20 kHz to 1 MHz range. Additionally, fast logic gates can generate faults with 100 mV amplitude due to wiring resistance and inductance. The resulting power supply noise means that special care must be taken to ensure that the inherent accuracy of the DAC is maintained. Good engineering judgment should be exercised when dealing with power grounding and bypassing the AD7390.

The AD7390 should be powered directly from the system power supply. As shown in Figure 6, this arrangement uses an LC filter and separate power and ground connections to isolate the analog section from the logic switching transients.

However, with or without separate power supply tracking, extensive power supply bypassing will reduce power line induced errors. A local power supply bypass consisting of a 10µF tantalum electrolyzer in parallel with a 0.1µF ceramic capacitor is recommended for all applications (Figure 7).

input logic level

All digital inputs are protected with a Zener-type ESD protection structure (Figure 8), which allows logic input voltages to exceed the VDD supply voltage. This feature is useful if the user is driving one or more digital inputs at 5V CMOS logic input voltage levels while operating the AD7390/AD7391 on a 3V supply. If using this interface mode, make sure that the VOL of the 5V CMOS meets the VIL input requirements for the AD7390/AD7391 operating at 3V. See TPC 6 for a graph of digital logic input thresholds versus operating VDD supply voltage.

To minimize power consumption at input logic levels close to the VIH and VIL logic input voltage specifications, a Schmitt trigger design is employed to minimize input buffer current consumption compared to conventional CMOS input stages. TPC 5 shows a graph of incremental input voltage versus supply current, showing negligible current consumption when the logic levels are quiescent. Normal cross currents still occur during logic transitions. A second advantage of Schmitt triggers is that when using standard CMOS logic interfaces or opto-isolators, false triggers due to slow-moving logic transitions are prevented. Logic inputs SDI, CLK, LD, CLR all contain Schmitt trigger circuits.

digital interface

The AD7390/AD7391 have double-buffered serial data inputs. The serial input register is separate from the DAC register, which allows new data values to be preloaded into the serial register without disturbing the current DAC value. A functional block diagram of the digital section is shown in Figure 4, while Table I contains the truth table for the control logic inputs.

Three pins control serial data input. Data at the serial data input (SDI) is recorded into the shift register on the rising edge of CLK. Data is entered in MSB first format. It takes 12 clock pulses to load the 12-bit AD7390 DAC value. If extra bits are recorded into the shift register, such as when the microcontroller sends two 8-bit bytes, the msb will be ignored (Figure 9). The CLK pin is only enabled when the load (LD) is high. The low-resolution 10-bit AD7391 contains a 10-bit shift register. The AD7391 also loads the MSB of the 10-bit data first. Likewise, if additional bits are recorded into the shift register, only the last 10 recorded bits are used.

The load pin (LD) controls the flow of data from the shift register to the DAC register. After a new value is recorded to the serial input register, it will be transferred to the DAC register by negative transition of the load pin (LD).

Reset (CLR) pin

Forcing the CLR pin low will set the DAC register to all zeros and the DAC output voltage will be zero volts. A reset function can be used to set the DAC output to zero at power-up or after a power interruption. Test systems and motor controllers are two of many applications that benefit from powering up to a known state. External reset pulses can be generated by the microprocessor's power-on reset signal, the microprocessor's output, or by external resistors and capacitors. The CLR has a Schmitt trigger input which produces a clean reset function when pulsed using an external resistor/capacitor. The CLR input overrides other logic inputs, especially LD. However, LD should be set high before CLR goes high. If CLR is held low, the contents of the shift register will be transferred to the DAC register once CLR returns high. See Control Logic Truth Table 1.

Unipolar output operation

This is the basic operating mode of the AD7390. As shown in Figure 10, the AD7390 is designed to drive loads as low as 5 kΩ in parallel with 100 pF. The code table for this operation is shown in Table 4.

Depending on application performance requirements, the circuit can be configured with an external reference plus power, or powered by a single dedicated regulator or reference.

Bipolar output operation

Although the AD7391 is designed for single-supply operation, the output can easily be configured for bipolar operation. A typical circuit is shown in Figure 11. The circuit is powered from a clean 5 volt regulated power supply, which also provides the reference voltage for the circuit. Since the output range of the AD7391 swings from ground to very close to 5V, it is necessary to choose an external amplifier whose common-mode input voltage range extends to its positive supply rail. The micropower OP196 is designed for this purpose, with a maximum power consumption of only 50 microamps. Connecting 470 kΩ resistors of the same value produces a differential amplifier operating mode with a voltage gain of 2, resulting in a circuit output span of 10 volts (ie, 25 volts to 15 volts). Since the DAC is programmed with zero code 000H to mid-scale 200H to full-scale 3FFH, the circuit output voltage VO is set to 25 volts, 0 volts and 15 volts V (minus 1 LSB). The output voltage VO is coded in offset binary according to Equation 4.

where D is the decimal code loaded in the AD7391 DAC register. Note that the LSB steps are 10/1024 = 10 mV. The circuit has been optimized for micropower consumption and includes a 470 kΩ gain setting resistor that should have a low temperature coefficient to maintain accuracy and matching (preferably the same material such as a metal film). If better stability is required, the power supply can be replaced with an accurate reference voltage, such as the low dropout REF195, which can easily power the circuit's 162µA current and still provide additional power to the load connected to VO. The Micropower REF195 is guaranteed to deliver 10mA of output drive current, but consumes only 50µA internally. If higher resolution is required, the AD7390 can be used with an additional two bits of data inserted into the software encoding, which will result in 2.5 mV LSB steps. Table V shows an example of the nominal output voltage VO provided by a bipolar operating circuit application.

Microcomputer interface

The AD7390 serial data input provides a simple interface to a variety of microcontrollers (μCs). Many µcs have built-in serial data capabilities that can be used to communicate with the DAC. Where a serial port is not provided, or is being used for some other purpose (such as an RS-232 communication interface), the AD7390/AD7391 can be easily addressed in software.

12 data bits are required to load the value into the AD7390. If more than 12 bits are sent before the load LD input goes high, the extra (ie, most significant) bits are ignored. This feature is valuable because most µCs only send data in 8-bit increments. So the µC sends 16 bits to the DAC instead of 12. However, the AD7390 will only respond to the last 12 bits going into the SDI input, so the serial data interface is not affected.

10 data bits are required to load the value into the AD7391. If more than 10 bits are transferred before load LD returns high, the extra bits are ignored.

Dimensions

Dimensions are in inches and (mm).