feature

±1.5 A, 50 V continuous output rating; low rDS (on) output; programmable mixed, fast and slow current decay modes; serial interface controls chip functions; low power synchronous rectification; internal UVLO and thermal shutdown circuitry; Cross current protection.

Designed for DC Pulse Width Modulation (PWM) current control, the A3948 SB and A3948SLB are capable of continuous output current of ±1.5 A with an operating voltage of 50 V. An internal fixed off-time pulse width modulated current control timing circuit is available via the serial interface and can operate in slow, fast and mixed current decay modes. A similar device with an output rating of ±2A is available as the A3958SB/SLB.

Provides phase and enable input terminals for pulse-width modulated control signals for speed and direction applications with external control of DC motors. The enable input can be programmed through the serial port to pulse-width modulate the bridge with fast or slow current decay. An internal synchronous rectification control circuit is provided to reduce power consumption during PWM operation.

Internal circuit protection includes thermal shutdown hysteresis and cross-current protection. Special powerups do not require sequencing.

The A3948SB/SLB is available in two power supply packages, a 24-pin plastic dipped copper stick (package suffix "B") and a 24-lead plastic SOIC with a copper stick (package suffix "LB"). In both cases, the power tag is on the ground without galvanic isolation.

Always order by full part number:

Functional block diagram

A3948SB (Dipping)

Note that A3948SLB (SOIC) and A3948SB (DIP) do not share common terminal tasks.

Function description

serial interface. The A3948 is controlled via a 3-wire (clock, data, strobe) serial port. Programmable features allow maximum flexibility in configuring PWM based on motor drive requirements. Serial data is clocked from D19.

D0–D1 blank time. According to the table below, the current sense comparator is shielded when any output driver is on. fosc is the input frequency of the oscillator.

D2–D6 fixed off time. A five-bit word sets the fixed off-time for the internal PWM current control. The closing time is defined by:

where N=0…31

For example, with an oscillator frequency of 4MHz, the off-time can be adjusted from 1.75µs to 63.75µs in 2µs increments.

D7–D10 fast decay time. A four-bit word sets the fast decay portion of the fixed off-time for the internal PWM control circuit. This only has an effect if the mixed decay mode is selected (via bit D17 and the mode input terminal). For tfd>toff, the device will operate effectively in fast decay mode. The fast decay part is defined as:

where N=0…15

For example, with an oscillator frequency of 4MHz, the fast decay time will be adjustable from 1.75µs to 31.75µs in 2µs increments.

D11 synchronous rectification mode. Active mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. Passive mode allows current reversal, but will turn off the synchronous rectification circuit if the load current reverses up to the current limit set by VREF/RS.

D12 Synchronous rectification enabled.

D13 External PWM decay mode. Bit D13 determines the current decay mode when chopping is enabled using external PWM current control.

D14 enables logic. Bit D14, with ENABLE, determines whether the output driver is in the chopped (off) (ENABLE=D14) or on (ENABLE≠D14) state.

D15 Phase Logic. Bit D15 is combined with PHASE to determine whether the device is working in the forward (PHASE≠D15) or reverse (PHASE=D15) state.

D16 Gm range option. Bit D16, together with RANGE, determines whether VREF is divided by 5 (RANGE≠D16) or by 10 (RANGE=D16).

D17 Internal PWM mode. Bit D17 combined with mode, selects slow (mode ≠ D17) or mixed (mode = D17) current decay.

D18 test mode. Bit D18 low (default) operates the device in normal mode. D18 is for testing purposes only. Users should not change this bit.

D19 sleep mode. Bit D19 selects sleep mode to minimize power consumption when not in use. This disables most of the internal circuitry including the regulator and charge pump. On power-up, the serial port is initialized to all 0s. Bit D19 should be programmed high for 1 ms before attempting to enable any output drivers.

Serial port write timed operation. Data is clocked into the shift register signal on the rising edge of the clock. Normally, the strobe will remain high and only initiate the lower limit of the write cycle. Refer to the chart below and these minimum timing specification requirements.

A. Data setting time...15ns

B. Data retention time...10 nanoseconds

C. Set the flash to the rising edge of the clock...50ns

D. Clock High Pulse Width...50 ns

E. Clock low pulse width...50ns

F. Set the rising edge of the clock to strobe... 50 ns

G. Strobe pulse width...50ns

VREG. This internally generated voltage is used to operate the receiver side DMOS output. The VREG terminal should be grounded separately from the 0.22µF capacitor. VREG is internally monitored and in the event of a fault condition, the device outputs are disabled.

Fill pump. The charge pump is used to generate a gate supply voltage greater than VBB to drive the source DMOS gate. A 0.22µF ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. 0.22µF ceramic capacitors should be connected between CP and VBB as reservoirs to operate high-end DMOS devices. The CP voltage is internally monitored and in the event of a fault, the source output of the device is disabled.

closure. If a fault occurs (junction temperature is too high, or voltage on CP or VREG is too low), the output of the device will be disabled until the fault condition is removed. On power-up, or in the case of low VDD, the UVLO circuit disables the driver and resets the data in the serial port to all zeros. The watchdog circuit also resets the data in the absence of the OSC signal.

PWM timer function. The PWM timer is programmable through the serial port (bits D2–D10) to provide an off-time PWM signal to the control circuit. In mixed current decay mode, the first part of the off time operates in fast decay until the fast decay time count (serial bits D7–D10) is reached, and then slowly decays for the remainder of the off time period (bits D2–D6). If the fast decay time is set longer than the off time, the device is effectively operating in fast decay mode. In conjunction with mode, bit D17 selects mixed decay or slow decay.

PWM blank timer. When the source driver is turned on, current spikes occur due to the reverse recovery current of the clamp diode and/or switching transients related to distributed capacitance in the load. To prevent this current spike from falsely resetting the source enable latch, the sense comparator is masked. The blank timer runs after the off-time counter (see bits D2–D6) to provide a programmable blank function. The blank timer is reset when ENABLE is switched off or the phase is changed. For external PWM control, a phase change or enable triggers the blanking function.

Synchronous rectification. When a PWM off cycle is triggered by the ENABLE chop command or the internal fixed off time period, the load current is recirculated according to the decay mode selected by the control logic. The A3948 synchronous rectification function will turn on the opposing pair of DMO outputs during current decay and effectively short the body diode using a low rDS(on) driver. This will greatly reduce power dissipation and can eliminate the need for external Schottky diodes.

Synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits D11 and D12).

In slow decay mode, active or passive mode selection has no effect. When sync correction is enabled, slow decay mode is used as an effective braking mode.

current regulations. The load current is regulated by an internal fixed off-time PWM control circuit. When the output of the DMOS H-bridge turns on, the current in the motor windings increases until a trip is reached as determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the range logic level, and serial data bit D16 value:

when range=D16. . . . . . . . . . . ITRIP=VREF/10RS

When the range ≠ D16. . . . . . . . . . . . ITRIP=VREF/5RS

At the trigger point, the detection comparator resets the sourceenable latch, turning off the source driver. The load inductance then cycles the current for a fixed off time period programmed by the serial port. The current path during recirculation is determined by the slow/mixed current decay mode (D17) and the configuration of the synchronous rectification control bits (D11 and D12).

Note that the induced voltage (VS) must not be greater than 0.55 V (Absolute Maximum Ratings). Therefore, if the reference divider is set to 5, VREF must not be greater than 2.75 V; if the reference divider is set to 10, then VREF must not be greater than 5.5 V (absolute maximum ratings).

current sensing. To minimize inaccurate sensing of ITRIP current levels caused by ground tracking infrared dips, the sense resistor should have a separate ground return to the device ground terminal. For low value sense resistors, the IR drop across the traces of the PCB sense resistor can be large and should be considered. Sockets should be avoided as the contact resistance of the sockets can cause variations in RS.

The maximum value of RS is RS≤0.5/ITRIP.

brake. Braking is accomplished by driving the unit in slow decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping via a combination of D14 and the enable input terminal. Since current can be driven in either direction through the DMOS driver, this configuration effectively shorts out the BEMF generated by the motor as long as chopper mode is enabled as long as it is asserted. It is important to note that the internal PWM current control circuit does not limit the current when braking because the current does not flow through the sense resistor. The maximum braking current can be approximated by VBEMF/RL. Care should be taken to ensure that the equipment's maximum ratings are not exceeded under worst-case braking conditions at high speeds and high inertia loads.

Thermal Protection. Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has a hysteresis of about 15°C.

layout. Printed wiring boards should use heavy duty ground planes. For best electrical and thermal performance*, the driver should be soldered directly to the circuit board. The ground side of the RS should have a separate path to the equipment ground terminal. This path should be physically as short as possible and should not connect any other components. It is recommended to place a 0.1µF capacitor between the sensor and ground, as close as possible to the device; the load power supply terminal VBB should be separated from the electrolytic capacitor (recommended greater than 47µF) placed as close as possible to the device.

*The thermal resistance and absolute maximum allowable package power dissipation specified on page 1 is measured on a typical double-sided printed circuit board with minimum copper ground area. See also Application Note 29501.5, Improving Batwing Power Consumption.

Terminal list

*Only for the A3948SB DIP, there is an indeterminate resistance between substrate ground (pins 6, 7, 18 and 19) and ground at pins 5 and 8. Pins 5 and 8 and 6, 7, 18 or 19 must be connected together externally.

Model A3948SB Dimensions: Inches (Control Dimensions)

Note: 1. Mesh lead frame. Conductors 6, 7, 18 and 19 are internally integral.

2. Within the limits shown, the exact body and lead configuration is selected by the supplier.

3. Lead spacing tolerances are non-cumulative.

4. The thickness of lead is measured at or below the seat surface.

5. Supplied in standard rods/tubes of 15 units.

A3948SLB Dimensions in inches (for reference only)

Notes: 1. Within the limits shown, the exact body and lead configuration is selected by the supplier.

2. Lead spacing tolerances are non-cumulative.

3. Mesh lead frame. Conductors 6, 7, 18 and 19 are internally integral.

4. Available in standard rods/tubes of 31 units, or add "TR" to the part number for tape and reels. The products described herein are manufactured under one or more US patents or US patents pending.

Allegro MicroSystems, Inc. reserves the right to deviate from detailed specifications at any time to improve the performance, reliability or manufacturability of its products. Before placing an order, the user is reminded to confirm that the information relied upon is up to date.