feature

Low-Power, Smallest Pin-Compatible, Four-nm DAC; AD5625R /AD5645R/AD5 665 R; 12-/14-/16-bit Nano DAC; On-Chip, 2.5V, 5ppm/°C, Reference TSSOP; On-Chip, 2.5 V, 10 ppm/°C LFCSP reference; on-chip, 1.25 V, 10 ppm/°C LFCSP reference; AD5625/AD5665 models; 12-/16-bit nanodac; external reference only; 3 mm x 3 mm, 10-lead LFCSP; 14 leads and 1.665 mm × 2.245 mm, 12-ball WLCSP; 2.7 V to 5.5 V supply; guaranteed monotonicity by design; power-on reset to zero-scale/mid-scale; power down per channel; hardware LDAC and CLR functions; Compatible serial interface supports standard ( 100 kHz), fast ( 400 kHz) and high-speed (3.4 MHz) modes.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

Members of the AD5625R/AD5645R/AD5665R and AD5625/AD5665nanoDAC® families are low power, quad, 12-/14/16-bit buffered voltage output DACs with/without on-chip references. All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and feature an I2C compatible serial interface.

The AD5625R/AD5645R/AD5665R have an on-chip reference. The LFCSP version of the AD5625R/AD5645R/AD5665R has a 1.25 V or 2.5 V, 10 ppm/°C reference, offering a full-scale output 2.5 V or 5 V range; the TSSOP version of the AD5625R/AD5645R/AD5665R has a 2.5 V reference, 5 ppm/ °C, giving a full-scale output range of 5 V. The WLCSP has a 1.25 V reference voltage. The on-chip reference is turned off at power-up, allowing the use of an external reference. Internal reference writes are enabled by software. The AD5625/AD5665 require an external reference to set the voltage of the DAC output range.

The device contains a power-on reset circuit that ensures that the DAC output powers up to 0V (POR=GND) or midscale (POR=VDD) and remains there until a valid write occurs. This on-chip precision output amplifier achieves rail-to-rail output swing.

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 use a 2-wire I2C-compatible serial interface with standard operation (100 kHz), fast (400 kHz), and high-speed (3.4 MHz) modes.

Typical performance characteristics

the term

Relative Accuracy or Integral Nonlinearity (INL)

For a DAC, relative accuracy or integral nonlinearity is a measure of the maximum deviations (LSBs) of a straight line passing through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. Monotonicity is assured by differential nonlinearity specified to a maximum of ±1 LSB. The monotonicity of the DAC is guaranteed by design.

Zero code error

A zero code error is a measure of the output error when the zero scale (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Due to the combination of offset errors in the DAC and output amplifier, the output of the DAC cannot go below 0 V, so the zero code error is always positive in the AD5665R. Zero-code errors are expressed in millivolts (mV).

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range (FSR).

gain error

Gain error is a measure of DAC span error. It is the slope deviation of the DAC transfer characteristic from the ideal expressed as a percentage of full scale range (FSR).

Zero code error drift

Zero-code error drift is a measure of zero-code error as a function of temperature. It is expressed in microvolts per degree Celsius (microvolts per degree Celsius).

Gain temperature coefficient

Gain temperature coefficient is a measure of gain error as a function of temperature. It is expressed in parts per million (ppm) and the full scale range is per degree Celsius (FSR/°C).

offset error

Offset error is a measure of the difference between V (actual) and V (ideal) expressed in mV in the linear region of the transfer function. The offset error is measured on the AD5665R and the DAC register is loaded with code 512. It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR)

DC-PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in decibels (decibels). VREF remains at 2v and VDD varies by ±10%.

Output voltage settling time

Output voltage settling time is the time required for the DAC output to settle to a specified level for a 1/4 to 3/4 full-scale input change, measured from the rising edge of a stop condition.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault area in nV-s, measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000) (see Figure 45).

digital feedthrough

Digital feedthrough is a measurement of pulses injected from the DAC's digital input into the DAC's analog output, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from 0 to 1 and vice versa.

reference feedthrough

Reference feedthrough is the ratio of the signal amplitude at the DAC output to the reference input when the DAC output is not being updated. It is expressed in decibels (decibels).

Output Noise Spectral Density

The output noise spectral density is a measure of internally generated random noise, characterized by the spectral density (mV/Hz root of frequency (nV/√Hz)). It is measured by loading the DAC to midscale and measuring the noise at the output. Units are millivolts/Hz frequency square root (nV/√Hz). The noise spectral density plot is shown in Figure 51.

DC crosstalk

DC crosstalk is the DC change in the output level of one DAC as the output of another DAC changes. It is measured by the full-scale output change of one DAC (or soft power off and on) while monitoring the other DAC held at mid-scale. Expressed in microvolts (μV).

DC crosstalk due to a change in load current is a measure of the effect of a change in load current on one DAC on another DAC that remains at midscale. It is expressed in microvolts per milliampere (µV/mA).

digital crosstalk

This is a glitch pulse that is midscale transferred to the output of one DAC in response to a full-scale code change in the input register of the other DAC (all 0s to all 1s and vice versa). It is measured in standalone mode and is expressed in nanovolts per second (nV-s).

Analog crosstalk

Analog crosstalk is a glitch pulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading an input register and making a full-scale code change (from 0 to 1 and vice versa), then executing a software LDAC and monitoring the output of the DAC whose digital code has not changed. The fault area is expressed in nanovolts per second (nV-s).

DAC-to-DAC crosstalk

DAC-to-DAC crosstalk is a glitch pulse transferred to the output of one DAC due to another DAC's digital code change and subsequent analog output change. It is measured by loading the attack channel with LDAC low and making a full range of code changes (from 0 to 1 and vice versa), while monitoring the output of the attack channel at mesoscale. The energy of the fault is expressed in nanovolts per second (nV-s).

Double the bandwidth

The multiplying bandwidth is a measure of the limited bandwidth of the amplifier within the DAC. A sine wave on the reference appears in the output (loading the full-scale code to the DAC). The octave bandwidth is the frequency at which the output amplitude drops 3db below the input.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and a decaying sine wave using a DAC. The sine wave is used as a reference for the DAC, and THD is a measure of the harmonics of the DAC's output. It is measured in decibels (decibels).

theory of operation

Digital-to-Analog Converter (DAC)

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 DACs are fabricated on a CMOS process. The AD5625/AD5665 have no internal references and the DAC architecture is shown in Figure 55. The AD5625R/AD5645R/AD5665R have internal references that can be configured for use with internal or external references (see Figure 55 and Figure 56).

Because the input encoding of the DAC is straight binary, the ideal output voltage when using an external reference is given by:

The ideal output voltage when using the internal reference is given by:

where: D is loaded into the DAC register as follows:

AD5625R/AD5625 (12-bit) is 0 to 4095.

AD5645R is 0 to 16383 (14 bits).

0 to 65535 (16 bits) for AD5665R/AD5665.

N is the DAC resolution.

resistor string

The resistor string is shown in Figure 57. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

output amplifier

The output buffer amplifier can generate rail-to-rail voltage at its output, the output range is 0v to V, can drive a 2kΩ load, and is connected in parallel with 1000pf to GND. The source and sink capabilities of the output amplifier are shown in Figure 39 and Figure 40. The slew rate is 1.8v/μs, and the whole settling time is 7μs.

internal reference

The AD5625R/AD5645R/AD5665R have an on-chip reference. Versions without the R suffix require external references. The on-chip reference is turned off at power-up and enabled by writing to the control register. See the Internal Reference Settings section for details.

Versions packaged in a 10-lead LFCSP feature a 1.25 V reference or a 2.5 V reference, with a full-scale output of 2.5 V or 5 V depending on the model selected (see ordering guide). The internal reference voltage of the WLCSP is 1.25 V. These devices can operate from voltage sources ranging from 2.7 V to 5.5 V. The version packaged in the 14-lead TSSOP has a 2.5 V reference and provides a 5 V full-scale output. The device operates from a voltage source from 2.7 V to 5.5 V, but at a voltage source below 5 V, the output voltage is clamped to V. See the guide for a complete list of ordering models. The internal reference associated with each device is available on the V pin (only available on the R suffix version).

A buffer is required if the reference output is used to drive an external load. When using the internal reference, it is recommended to place a 100 nF capacitor between the reference output and GND to maintain reference stability.

xref

The VREFIN pin on the AD5625R/AD5645R/AD5665R allows the use of an external reference if required by the application. The default condition for the on-chip reference is to turn off at power-up. All devices can be operated from a 2.7V to 5.5V power supply.

serial interface

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 feature a 2-wire IC-compatible serial interface. The AD5625R is under the control of a master device, and the AD5645R/AD5665R and AD5625/AD5665 can be connected to the IC bus as slave devices. A timing diagram for a typical write sequence is shown in Figure 3.

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 support standard (100 kHz), fast (400 kHz), and high-speed (3.4 MHz) data transfer modes. High-speed operation is only available on selected models. See the ordering guide for a complete list of models. 10-bit addressing and general call addressing are not supported.

Each AD5625R/AD5645R/AD5665R and AD5625/AD5665 has a 7-bit slave address. The 10-pin and 12-ball versions of the device have a slave address with 5 msbs of 00011 and two lsbs set by the state of the ADDR address pin, which determines the state of the A0 and A1 address bits. The 14-lead version of the device has a slave address whose 3msb is 001, and the four lsbs are set by the ADDR1 and ADDR2 address pins, which determine the state of the A0 and A1 and A2 and A3 address bits, respectively.

As shown in Table 9, the ability to hardwire changes to the ADDR pins allows users to combine up to three such devices on a single bus.

The ability to hardwire changes to the ADDR1 and ADDR2 pins allows users to combine up to nine of these devices on a single bus, as shown in Table 10.

The 2-wire serial bus protocol operates as follows:

1. When a high-to-low transition occurs on the SDA line when SCL is high, the host initiates data transfer by establishing a start condition. The following bytes are the address bytes, consisting of a 7-bit slave address. The slave address corresponding to the transmit address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register.

2. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledgment bit). The transition of the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.

3. A stop condition is established when all data bits have been read or written. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition. In read mode, the master responds with a no to the ninth clock pulse (ie the SDA line is held high). The master pulls the SDA line low before the 10 clock pulses and then high during the 10 clock pulses to establish a stop condition. the first

write operation

When writing to the AD5625R/AD5645R/AD5665R and AD5625/AD5665, the user must begin with a start command followed by an address byte (R/W = 0), then the DAC confirms that it is ready to receive data by pulling SDA low. The AD5665 requires two bytes of data for the DAC and a command byte that controls various DAC functions. Therefore, three bytes of data must be written to the DAC, with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 58 and Figure 59. A STOP condition occurs after the AD5625R/AD5645R/AD5665R and AD5625/AD5665 have acknowledged these data bytes.

read operation

When reading data back from the AD5625R/AD5645R/AD5665R and AD5625/AD5665, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC confirms that it is ready to transfer data by pulling SDA low. Two bytes of data are then read from the DAC, both of which are acknowledged by the master, as shown in Figure 60 and Figure 61. A stop condition then occurs. When performing a read operation, the DAC shifts out the last transmitted command.

high speed mode

Some models offer high-speed serial communication with a 3.4mhz clock frequency. See the ordering guide for a complete list of models.

After high-speed mode communication begins, master address all devices connected to the bus, master code 00001XXX, to indicate that high-speed mode transmission will begin. No device connected to the bus is allowed to acknowledge the high-speed master code; therefore, the code is followed by a non-acknowledge. Next, the host must issue a repeated start followed by the device address. The selected device then confirms its address. All devices continue to operate in high-speed mode until a stop condition is issued by the host. When a stop condition is issued, the device returns to standard/fast mode. When the device is in high-speed mode, the device also returns to standard/fast mode when the CLR is activated.

input shift register

The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of the serial clock input SCL. The timing diagram for this operation is shown in Figure 3. Eight msbs make up the command byte. DB23 is reserved and should always be set to 0 when writing to the device. DB22(S) is used to select multibyte operations. The next three bits are the command bits (C2, C1, and C0) that control the mode of operation of the device. See Table 11 for details. The last three bits of the first byte are the address bits (A2, A1, and A0). See Table 12 for details. The remaining bits are 16-/14-/12-bit data words. The data word consists of a 16-/14-/12-bit input code followed by two or four don't care bits for the AD5645R and AD5625R/AD5625, respectively (see Figure 65 to Figure 67).

multibyte operations

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 support multibyte operation. 2-byte operation is useful for applications that require fast DAC updates and do not require changing command bytes. For 2-byte operation mode, the S bit (DB22) in the command register can be set to 1 (see Figure 64). For standard 3-byte and 4-byte operations, the S bit (DB22) in the command byte should be set to 0 (see Figure 63).

broadcast mode

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 support broadcast addressing only in write mode. Broadcast addressing can be used to update or shut down multiple AD5625R/AD5645R/AD5665R and AD5625/AD5665 devices simultaneously. When using a broadcast address, the AD5625R/AD5645R/AD5665R and AD5625/AD5665 respond regardless of the state of the address pins. The AD5625R/AD5645R/AD5665R and AD5625/AD5665 broadcast address is 00010000.

LDAC function

The AD5625R/AD5645R/AD5665R and AD5625/AD5665DAC have a double-buffered interface consisting of two sets of registers: the input register and the DAC register. The input registers are connected directly to the input shift registers, and upon completion of a valid write sequence, the digital code is transferred to the associated input register. The DAC register contains the digital code used by the resistor string.

Access to the DAC registers is controlled by the LDAC pin.

When the LDAC pin is high, the DAC registers are locked and the input registers can change state without affecting the contents of the DAC register. However, when LDAC is lowered, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user needs to update all DAC outputs simultaneously. The user can individually write to one of the input registers, then, when writing to the other DAC input register, by lowering LDAC, all outputs are updated simultaneously. These devices all contain an additional feature that the DAC registers are not updated unless the input registers have been updated since the last time LDAC was low. Normally, when LDAC is low, the DAC register is filled with the contents of the input register. In the case of the AD5625R/AD5645R/AD5665R and AD5625/AD5665, the DAC registers are updated only if the input registers have changed since the last time the DAC registers were updated, eliminating unwanted digital crosstalk. Using the hardware LDAC pins, the outputs of all DACs can be updated simultaneously.

Synchronous LDAC

The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed.

Asynchronous LDAC

The output does not update the register at the same time as the input is written. When LDAC goes low, the DAC register is updated with the contents of the input register. The LDAC register provides the user with full flexibility and control over the hardware LDAC pins (and software LDACs on 10-lead devices that do not have hardware LDAC pins, see Table 13). This register allows the user to select when the hardware LDAC executes the pin. Setting the LDAC bit register for a DAC channel to 0 means that updates for this channel are done by the LDAC pin. If this bit is set to 1, the channel is updated synchronously; that is, new data can be read in regardless of the state of the LDAC pin. The device effectively pulls the LDAC pin low. See Table 14 for the LDAC register operating modes. This flexibility is useful in applications when the user wants to update select channels at the same time while other channels are being updated synchronously. Write to the DAC using Command 110 to load the 4-bit LDAC register[DB3:DB0]. The default value for each channel is 0; that is, the LDAC pin is functioning properly. Setting the bit to 1 means that the DAC register is updated regardless of the state of the LDAC pin. The contents of the input shift register are shown in Figure 68 during the LDAC register set command.

Power down mode

Command 100 is reserved for power up/down functions. The power up/down mode is programmed by setting Bit DB5 and Bit DB4. This defines the output state of the DAC amplifier, as shown in Table 15. Bits DB3 to DB0 determine to which DAC or DAC the power-up/power-down command is applied. Setting one of these bits to 1 applies the power-up/power-down state defined by DB5 and DB4 to the corresponding DAC. If the bit is 0, the state of the DAC is unchanged. Figure 70 shows the contents of the input shift register for the power up/down command.

When Bit DB5 and Bit DB4 are set to 0, the device operates normally, and the normal power consumption is 1mA at 5V. However, for the three power-down modes, the supply current drops to 480mA at 5V. Not only does the supply current drop, but the output stage is also internally switched from the amplifier's output to a resistor network of known value. This allows the output impedance of the device to be known when the device is in power down mode. The output can be internally connected to GND through a 1kΩ or 100kΩ resistor, or it can be left open (tri-stated), as shown in Figure 67.

Note that the 14-lead TSSOP models provide a power-down feature when the device is operating from 3.6 V to 5.5 V. The 10-lead LFCSP model provides a power-down function when the device operates from 2.7 V to 5.5 V.

When the power-down mode is activated, the bias generator, output amplifier, resistor string and other associated linear circuits are turned off. However, when powered down, the contents of the DAC registers are not affected. For V=5V or V=3V, the time to exit power-down is typically 4μs.

Power-on reset and software reset

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 contain a power-on reset circuit that controls the output voltage during power-up. The 10-wire version of the device has a power supply up to 0 volts. The 14-wire version has a power-on reset (POR) pin that allows selection of the output voltage. The AD5625R/AD5645R/AD5665R and AD5625/AD5665 output power up to 0 V by connecting the port pin to GND; the AD5625R/AD5645R/AD5665R and AD5625/AD5665 output power up to mid-scale by connecting the port pin to V. The output will remain powered on at this level until a valid write sequence is issued to the DAC. This is useful in applications where it is important to know the state of the DAC's output during power-up. During power-on reset, any events on the LDAC or CLR are ignored. There is also a software reset function. Command 101 is a software reset command. The software reset command contains two reset modes, which are software programmable by setting bit DB0 in the input shift register.

Table 16 shows how the state of the bits corresponds to the software reset mode of operation of the device. Figure 71 shows the contents of the input shift register during the software reset mode of operation.

Internal reference setup (R version)

By default, the on-chip reference is turned off at power-up. Possibly turned on by sending a reference set command (111) and setting DB0 in the input shift register. Table 17 shows how the state of the bits corresponds to the operating mode.

application information

Using the reference as a power supply for the AD5625R/AD5645R/AD5665R and AD5625/AD5665

Since the supply current required by the AD5625R/AD5645R/AD5665R and AD5625/AD5665 is extremely low, another option is to use a voltage reference to supply the required voltage to the device (see Figure 73). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5V or 3V, such as 15V. The voltage reference outputs the regulated supply voltage for the AD5625R/AD5645R/AD5665R and AD5625/AD5665. If a low dropout REF195 is used, it must supply 450 µA to the AD5625R/AD5645R/AD5665R and AD5625/AD5665 with no load on the output of the DAC. When the DAC output is loaded, the REF195 must also supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is:

The load regulation of the REF195 is typically 2ppm/mA, resulting in a 4ppm (20µV) error of the 2ma current. This corresponds to a 0.263 LSB error.

Bipolar Surgery Using the AD5625R/AD5645R/AD5665R and AD5625/AD5665

The AD5625R/AD5645R/AD5665R and AD5625/AD5665 are designed for single-supply operation, but a bipolar output range can also be achieved using the circuit shown in Figure 74. The output voltage range of this circuit is ±5 V. Using the AD820 or OP295 as the output amplifier enables rail-to-rail operation at the output of the amplifier.

The output voltage of any input code can be calculated as follows:

where D represents the input code in decimal (0 to 65535). If VDD=5V, R1=R2=10kΩ,

This is an output voltage range of ±5 V, 0x0000 corresponds to -5 V output and 0xFFFF corresponds to +5 V output.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5625R/AD5645R/AD5665R and AD5625/AD5665 should have separate analog and digital sections, each with its own board area. If the AD5625R/AD5645R/AD5665R and AD5625/AD5665 are in a system where other devices require an AGND to DGND connection, they should only be connected at one point. This ground point should be as close as possible to the AD5625R/AD5645R/AD5665R and AD5625/AD5665.

The power supplies to the AD5625R/AD5645R/AD5665R and AD5625/AD5665 should be bypassed with 10µF and 0.1µF capacitors. Capacitors should be placed as close to the device as possible, ideally a 0.1µF capacitor should be placed close to the device. The 10µF capacitors are of the tantalum bead type. It is important that 0.1µF capacitors have low effective series resistance (ESR) and low effective series inductance (ESI), for example, common ceramic type capacitors. This 0.1µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents generated by internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other fast switching digital signals should be shielded from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When the traces cross on opposite sides of the board, make sure they run at right angles to each other to reduce the effect of feedthrough through the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions