1 big feature

1. AEC-Q100 qualified for automotive applications with the following results: – Device temperature class 1: –40°C to +125 °C ambient operating temperature – Device HBM ESD class: – Class 3B for pins 6 and 7 – for all other pins Class 3A – Device CDM ESD Classification Class C6 Meets or exceeds ISO 11898-2 and ISO 11898-5 Compliant with GIFT/ICT standards Data rates up to 1 Mbps ESD protection up to ±12 kV (Human Body Model) on bus pins I/ O Voltage Level Adjustment – HVDA551: Applicable I/O Voltage Range (VIO) from 3 V to 5.33 V 8226 ; Split Voltage Source – HVDA553: Common Mode Bus Stable Operating Modes: – Normal Mode – Low Power Standby Mode, RXD Wake-up Request High Electromagnetic Compatibility (EMC) Support for CAN Flexible Data Rate (FD) Protection – Under-Voltage Protection on VIO and VCC – Bus Fail Protection – 27 V to 40 V Request Main Fault Stuck (HVDA551) – Digital Input and 5-V Compatible Microprocessor (HVDA553) – Thermal Shutdown Protection – Power-Up and Power-Up No Fault Bus I/O – High Bus Input Impedance when No Power (No Bus Load)

2. Application Automotive SAE J2284 High Speed Tank

application

SAE J1939 standard data bus interface

GMW3122 two-wire CAN physical layer

ISO 11783 standard data bus interface

NMEA 2000 standard data bus interface

3. Description

The HVDA55x-Q1 devices are designed to be qualified for automotive applications and meet or exceed the specifications of ISO 11898 Speed Controller Area Network Physical Layer Standard (Transceivers).

Switching Characteristics

Over operating free air temperature range (unless otherwise stated)

(1) All typical values are at 25°C, supply voltage VCC=5V, VIO=3.3V.

(2) Once the TXD dominant time exceeds t(DOM), the TXD dominant timeout (t(DOM)) will disable the transceiver's driver to release the bus to recessive, preventing a local fault from locking the bus dominant . The driver can only transmit dominant again after TXD returns high (recessive). While this protects the bus from local faults and locks out the bus master, it limits the minimum data rate possible. In the worst case, the CAN protocol allows up to 11 consecutive master bits (on the TXD), five of which are followed by an error frame. This together with the t(DOM) minimum limits the minimum bitrate. The minimum bit rate is calculated as: minimum bit rate = 11/t(DOM) = 11 bits/300 microseconds = 37kbps

Typical features

VIO=5V, STB=0V, Rl=60Ω, CL=open, RCM=open, TJ=25°C (unless otherwise stated)

A. The input pulse is provided by a generator with the following characteristics: PRR≤125 kHz, 50% duty cycle, tr≤6 nanoseconds, tf≤6 nanoseconds, ZO=50 ohms.

B. CL, including the capacitance of the meter and fixture, is within ±20%.

C. For HVDA553 device version, VIO=VCC.

A. The input pulse is provided by a generator with the following characteristics: PRR≤125 kHz, 50% duty cycle, tr≤6 nanoseconds, tf≤6 nanoseconds, ZO=50 ohms.

B. CL, including the capacitance of the meter and fixture, is within ±20%.

C. For HVDA553 device version VIO=VCC.

Overview

The device meets or exceeds the ISO 11898 high-speed controller area network (CAN) specification for physical layer standards (transceivers). The device provides CAN transceiver functionality: differential transmit bus capability and differential receive capability at data rates up to 1 megabit per second (Mbps). This device includes a number of protection features that provide robustness to the device and the CAN network.

Feature description

Digital Inputs and Outputs The HVDA551 device has an I/O supply voltage input pin (VIO) that is used to scale the digital logic input horizontally relative to the VIO output level to match the I/O supply voltage between 3V and 5.33V Volt. The HVDA553 device has a VCC power supply (5v). The digital logic input and output levels of these devices are compatible with VCC and I/O power supply protocol controllers between 4.68 V and 4.68 V 5.33 V using the HVDA553 with split termination in normal mode, split pin voltage The output provides 0.5×VCC. This circuit can be used to stabilize the common-mode voltage network of the bus by connecting the bus to the center tap of the CAN tap (see Figure 15 and Figure 23). This pin provides a regulated recessive voltage drive to compensate for leakage current from unpowered transceivers or other bias imbalances that can cause the common-mode voltage of the network to be away from 0.5 × VCC. Using this feature in a CAN network can improve transmission by eliminating fluctuating bus common-mode voltage levels at the beginning of a message.

TXD Master State Timeout In normal mode, and only in mode with the controller area network driver active, the TXD master time-out circuit prevents the transceiver from dominating network communications for longer than the time-out period t when a hardware or software failure occurs on the TXD. (DOM). The main time-out circuit is triggered by a falling edge on TXD. If no rising edge is seen before the circuit's timeout constant (t(DOM)) expires, the CAN bus driver is disabled, freeing the bus for communication between other network nodes. When a recessive signal is visible on the TXD pin, clearing the dominant state times out. The CAN bus pins are biased to the recessive level during the TXD dominant state timeout.

Undervoltage lockout or no power supply unit

Brown-out detection is available on both supply pins, placing the device in forced standby mode to protect the bus in the event of a brown-out event on the VCC or VIO supply pins. If VIO is under voltage, the RXD pin is forced into a high impedance state and the device will not pass any wake-up signal from the bus to the RXD pin. Since the device is in forced standby mode, the common-mode bias of the CAN bus pins is ground, protecting the CAN network; see Figure 16 and Figure 17. The device is designed to be an ideal passive load to the CAN bus if it is unpowered. The bus pins (CANH, CANL) have extremely low leakage current when the device is unpowered, so they don't load the bus but do a no-load. This is very important especially when some nodes in the network are not powered and the network is still running.

floating pin

The device integrates pull-up and pull-down on key pins if the pin is floating. The TXD and STB pins on the HVDA551 are pulled to VIO. This will force the recessive input level on TXD a situation where the TXD pin is floating if the STB pin is floating. For the HVDA553, both the TXD and STB pins are pulled to VCC, which has the same effect. CAN bus short-circuit current limiting The device has multiple protection functions to limit short-circuit current when the CAN bus is short-circuited. These include drive current limit (dominant and recessive) and TXD dominant state timeout to prevent sustained drive dominance. During CAN communication, the bus switches states between dominant and recessive; therefore, the short-circuit current can be viewed as the current or DC average current during each bus state. Considering the system current and power choke rating in the terminating resistor and common mode, the average short circuit current must be used. The device has a TXD master state timeout, which permanently prevents the dominant high short-circuit current. The CAN protocol also has mandatory state changes and recessive bits such as bit stuffing, control fields and interframe spaces. These are guaranteed even if the data field contains the dominant part.

The average short-circuit current can be calculated by formula 2: IOS(AVG)=%Transmission×[(%REC bit×IOS(SS)REC)+(%DOM bit×IOS(SS)DOM)]+[%Receive×IOS(SS) REC]

IOS (average) is the average short circuit current

Transmit is the percentage of CAN messages sent by the node

Receive is the percentage of CAN messages received by the node

REC_Bits is the percentage of recessive bits in the transmitted CAN message

DOM_bits is the percentage of dominant bits in the transmitted CAN message

IOS(SS)REC is the recessive steady-state short-circuit current

IOS(SS) is the dominant steady-state short-circuit current (2)

Device functional mode

These devices have two main modes of operation: normal mode and standby mode. Table 3 lists these mode details. Operation mode selection is made through the set-top box input pins.

Bus Status by Mode

During power-up operation, the CAN bus has three active states, depending on the mode of the device. Normally in mode, the bus may be dominant (logic low), where the bus lines are driven differentially, or the bus may be recessive (logic high), where the bus is biased into the VCC/2 receiver through a high-ohmic internal input resistor. The third state is a low-power standby mode, where the bus is biased to GND through the receiver's high-ohmic internal input resistor RIN.

normal mode

This is the normal working mode of the device. Normal mode is selected by setting STB low. The can driver receiver is fully functional and CAN communication is bidirectional. The driver is converting digital inputs on TXD to differential outputs on CANH and CANL. The receiver is converting the differential signal from CANH for digital output on RXD. In the recessive state, the CAN bus pins (CANH and CANL) are biased towards 0.5 × VCC. In the master state, the bus pins are driven differentially. A logic high is equivalent to a recessive bus on the bus, and a logic low is equivalent to a primary (differential) signal on the bus.

Standby mode with RXD wake-up request

This is the low power mode of the device. Standby mode is selected by setting the set-top box height. The can driver and main receiver are off, and bidirectional CAN communication is not possible. The low power receiver and bus monitor, both provided via VIO, are both via the CAN bus. The VCC (5-V) power supply may be turned off for further power savings at the system level. Wake-up Request is output to RXD (driven low) for any master bus transfer that exceeds the filter time tbu. This local protocol controller (MCU) must monitor RXD transitions and then reactivate the device to normal mode based on a wake-up request. The local protocol controller must reactivate the 5-V (VCC) power supply to resume normal mode if it has been shut down for low power standby operation. The CAN bus pins are weakly pulled to GND, see Figure 16 and Figure 17.

RXD Bus Stuck Master Fault Wakeup Request Lockout (HVDA551) If the bus fails, the bus is still dominant while the HVDA551 is in standby mode Through the STB pin, the device locks the RXD wakeup request until the fault clears to prevent false wakeups in the system Signal.

application information

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the data link layer portion of the CAN protocol. The following typical application configurations are for 5-V and 3.3-V microprocessor applications. For illustration purposes, bus terminations are shown.

typical application

Some typical applications of the HVDA55x family are shown below

Design requirements

The ISO 11898-2 standard specifies a maximum bus length of 40 m and a maximum stub length of 0.3 m. However, with careful design, users can have longer cables, longer memory lengths and more bus nodes. A large number of nodes require transceivers with high input impedance, such as transceivers. Many CAN organizations and standards have extended the use of CAN for applications beyond the original ISO 11898-2. They trade off data rate, cable length, and bus parasitic loading at the system level. Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.

Detailed design procedure

The ISO 11898 standard specifies the interconnection as 120Ω twisted pair (shielded or unshielded) characteristic impedance (ZO). Both ends of the cable must be terminated with a resistor equal to the characteristic impedance of the line to prevent signal reflections. The distance from the unterminated drop line (stub) connecting the nodes to the bus must be kept as short as possible to minimize signal reflections. The termination may be on the cable or in the node, but if the node can be removed from the bus, the termination must be carefully placed so that the termination is always present on the network. The termination can be a 120Ω resistor at the end of the bus, either on the cable or on the termination node. If the common mode voltage of the bus needs to be filtered and stabilized, then tap terminals can be used (see Figure 22). Split termination works by eliminating fluctuations in the bus common-mode voltage at the beginning and end of a message transmission.