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2022-09-23 10:10:12
Agilent HCPL-8100/0810 High Current Line Driver
illustrate
The HCPL-8100 and HCPL-0810 are low cost high current line drivers. With a 5V single power supply, they provide up to 1 application current. This is ideal for high current applications as a power line modem. The HCPL-8100 and HCPL-0810 have internal protection to prevent shutdown due to over-temperature thermal conditions. Undervoltage or overload conditions detected through internal detection circuitry
feature
1 applied drive current
3.5 MHz Gain Bandwidth Product – 60 dB Maximum Harmonic Distortion
Load detection function
Undervoltage detection
Over temperature shutdown
5 V single supply
Temperature range: –40°C to +85°C
Suitable for FCC Part 15 and EN50065-1 Compliant Designs
application
Automatic Meter Reading (AMR)
power line modem
Universal Line Driver
signal conditioning
digital to analog converter
buffer
And the output is indicated by the status pin. In addition to the transmit enable (Tx en) input, the line driver output stage can be disabled to reduce power consumption when not in operation. The HCPL-8100 and HCPL-0810 are specified for operation over the extended temperature range -40°C to +85°C. HCPL-8100 is available in DIP-8 packaging and HCPL-0810 is available in SO-8 packaging.
Electrical Specifications
All typical values are at TA=25°C and VCC=5V for sinusoidal input and reference resistor Rref=24 kΩ unless otherwise noted; all min/max specifications are under recommended operating conditions.
notes:
1. VCC falling threshold with 0.2V (typ) hysteresis.
2. Hysteresis 20°C (typ) junction temperature rise threshold.
3. For more information on the load detection feature, see the Application Information section.
4. The relationship between the supply current and the Tx output current is shown in Figure 3.
Performance graph
All typical graphs are for TA=25°C, VCC=5 V, sine wave input and Rref=24 kΩ unless otherwise noted.
Test circuit diagram
Unless otherwise stated, all test circuits are at TA=25°C, VCC=5 V, sinusoidal waveform input, and signal frequency f=132kHz.
application information
The HCPL-8100 and HCPL-0810 are designed to work with a variety of transceivers and are available with a variety of modulation methods including interrogation, FSK and BPSK. Figure 17 shows the frequency shift keying (FSK) modulation scheme in use for a power line modem.
line driver
The line driver is capable of driving power line loads with output signal impedances up to 4 VPP. The bias of the internal line driver is connected from pin 4 to ground through an external control resistor Rref. The optimum offset point value for modulation frequencies up to 150 kHz is 24 kΩ. In order to operate some modulation schemes at higher frequencies, it may be necessary to reduce the resistor value to be enabled to comply with international regulations. The output of the line driver is connected to the power line using a simple LC coupling circuit as shown in Figure 18. Refer to Table 1 for typical component values. Capacitor C2 and inductor L1 attenuate the 50/60 Hz power line transmission frequency. Suitable values for L1 range from 200 μH to 1 mH. To reduce the series coupling impedance at the modulation frequency, L2 is included to compensate for the reactive impedance of C2. The inductor should be low resistive to meet peak current requirements. To meet many regulatory requirements, capacitor C2 must be of type X2. Because these types of capacitors typically have a very wide tolerance range of 20%, it is recommended to use the lowest possible Q-factor L2/C2 combination. Using a high-Q coupling circuit will result in a low power line impedance to the overall coupling impedance, causing potential communication difficulties. Occasionally with other circuit configurations, high-Q coupling arrangements are recommended, such as below C2 over 100 nanofarads. In this case it is usually used to filter out the band harmonic source from the line driver. This is not required for HCPL-8100 or HCPL-0810.
Although the series coupling impedance is minimized to reduce insertion loss, it must be large enough to limit the maximum current to the desired level under worst-case expected power line loading conditions. The peak output current is effectively driven by the full series coupling resistance, which is determined by the series resistance in L2, the series resistance fuse and any other resistance connected in the coupling network. To reduce power consumption during transmission inactive mode the line driver stage is off to a low power high impedance state pulling the Tx en input (pin 2) to a logic low state. External transient voltage protection protects the HCPL-8100 and HCPL-0810 from transient surges caused by high voltage power and requires the addition of an external 6.8V bidirectional transient voltage protector (component D117 shown in the component diagram) when disconnecting/connecting the modem . Additional protection from power line voltage surges can be achieved by adding appropriate metal oxide varistor (MOV) power line termination fuses. Internal Protection and Sensing The HCPL-8100 and HCPL-0810 include several sensing as well as protection features to ensure protection over a wide range of environmental conditions. The first feature is VCC undervoltage detection.
If VCC drops when the voltage is less than 4V the output status pin has toggled to a logic high. The next feature is over-temperature shutdown. This special feature protects the line driver stage from excessive thermal stress. Should the IC junction temperature range be higher than 150°C, the horizontal line driver circuit will shut down and the status output (pin 1) will be pulled to a logic high state at the same time. The last feature is the load detection function. This power line impedance is quite unpredictable just at different connections but is also time-varying. The HCPL-8100 and HCPL-0810 contain current sensing capabilities available to provide feedback on instantaneous power line load conditions. If the peak current reaches a greater level than 0.5 APP, the output status pin is pulled logically to the highest state peak current for the entire period over -0.25A as shown in Figure 12. Using the pulse period and the known coupling impedance, the actual power line load can be calculated. Table 2 shows the logic outputs of the status pins.