feature

2-channel 256 -position potentiometer; end-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ in compact 10-lead MSOP (3 mm x 4.9 mm) packages; fast settling time: typically tS = 5 microseconds at power up ; full read/write of wiper registers; power on preset to midscale; additional packet address decode pins: AD0 and AD1 only) (AD5248O); computer software replaces microcontroller single power supply in factory programmed applications: 2.7 V to 5.5 V; low temperature coefficient: 35ppm/°C; low power consumption: IDD=6µA max; wide operating temperature: -40°C to +125°C evaluation board available.

application

System calibration; electronic level setup; mechanical cutter replacement in new designs; permanent factory printed circuit board (PCB) setup; sensor adjustments for pressure, temperature, position, chemical and optical sensors; RF amplifier biasing; gain control and Offset adjustment.

General Instructions

The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm package solution for dual 256 position adjustment applications. The AD5243 performs the same electronic trim function as a 3-terminal mechanical potentiometer, and the AD5248 performs the same trim function as a 2-terminal variable resistor. Available in four end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ), these low temperature coefficient devices are ideal for high precision and stability variable resistance adjustments. Wiper settings are controlled via an IC-compatible digital interface. The AD5248 has additional packet address decode pins AD0 and AD1, allowing multiple parts to share the same IC, 2-wire bus on a PCB. The resistance between the wiper and the fixed terminal varies linearly with the transmitted digital code into the RDAC latch. (Terms such as digital potentiometer, VR, and RDAC are used interchangeably.)

Operating from a 2.7V to 5.5V supply, it consumes less than 6µA, allowing the AD5243/AD5248 to be used in portable battery powered applications.

For applications that program the AD5243/AD5248 at the factory, Analog Devices, Inc. provides device programming software that runs on Windows® NT/2000/XP operating systems. The software effectively replaces the need for an external IC controller, thereby improving the system's time-to-market. AD5243/AD5248 evaluation kits and software are available. The kit includes cables and manual.

Typical performance characteristics

test circuit

Figures 30 through 36 illustrate the test circuits that define the test conditions used in the product specification sheets (see Tables 1 and 2).

theory of operation

The AD5243/AD5248 are 256-bit digitally controlled variable resistor (VR) devices.

A built-in power-up preset places the wipers at mid-scale when powered up, which simplifies recovery from fault conditions at power-up.

Variable Resistor and Voltage Programming

Rheostat operation

The nominal resistances of the RDAC between Terminal A and Terminal B are 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ, respectively. The nominal resistance (R) of VR has 256 contact points, which are contacted by the wiper terminal and the B terminal. The 8-bit data in the RDAC latch is decoded to select one of 256 possible settings.

Assuming a 10 kΩ part is used, the first wiper connection for data 0x00 starts at the B terminal. Since there is a wiper contact resistance of 160Ω, such a connection creates a minimum resistance of 320Ω (2 x 160Ω) between terminal W and terminal B. The second connection is the first tap point, corresponding to 359Ω for data 0x01 (R=R/256+2×R=39Ω+2×160Ω). The third connection is the next tap point, indicating that data 0x02 is 398Ω (2×39Ω+2×160Ω), and so on. For each additional LSB data value, the wiper moves up the resistor ladder until the last tap point reaches 10281Ω (R+2×R).

The general formula for determining the digitally programmed output resistance between W and B is:

Where: D is the 8-bit RDAC register; RAB is the end-to-end resistance; RW is the internal switch.

To sum up, if RAB is 10 kΩ and the A terminal is open, the following output resistor RWB is set to the RDAC latch code.

Note that there is a finite wiper resistance of 320Ω at zero-scale conditions. In this state, care should be taken to limit the current between W and B to a maximum pulsed current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to the mechanical potentiometer, the RDAC resistor between wiper W and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. The resistance value for setting R starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

When R is 10 kΩ and the B terminal is open, the output resistance R is set according to the RDAC latch code, as shown in Table 8.

Typical equipment-to-equipment matching is process batch dependent and can vary by as much as ±30%. Since the resistive element is processed with thin film technology, R has a very low temperature coefficient of 35ppm/°C as a function of temperature.

Program the Potentiometer Divider

Voltage output operation

The digital potentiometer easily creates a voltage divider at wiper to B and wiper to a, proportional to the input voltage at a to B. Unlike the polarity of VDD to GND (which must be positive), the voltages a to B, W to a, and W to B can be of any polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground results in an output voltage when the wiper is connected to B, starting at 0 V and less than 1 LSB of 5 V. The voltage of each LSB is equal to the voltage applied to Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. The general equation that defines the V output voltage relative to ground for any effective input voltage applied to Terminal A and Terminal B is:

The operation of the digital potentiometer in voltage divider mode allows for more precise operation when the temperature is too high. Unlike the varistor mode, the output voltage is mainly determined by the ratio of the internal resistances RWA and RWB, not the absolute value. Therefore, the temperature drift was reduced to 15ppm/°C.

ESD protection

All digital inputs are protected with a series of input resistors and a parallel Zener ESD structure, as shown in Figure 40 and Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital input pins (AD5248 only).

Terminal voltage operating range

The AD5243/AD5248 VDD and GND supplies define the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals that appear on the A, B, and W terminals in excess of VDD or GND are clamped by internal forward-biased diodes (see Figure 42).

power-on sequence

Since the ESD protection diodes limit voltage compliance at the A, B, and W terminals (see Figure 42), it is important to power VDD/GND before applying voltage to the A, B, and W terminals; otherwise, the diodes are positive to bias VDD inadvertently and potentially affect the rest of the user circuit. The ideal power-up sequence is as follows:

GND, VDD, digital inputs, then VA, VB, and VW. The relative order of VA, VB, VW, and digital inputs does not matter as long as power is supplied after VDD/GND.

Layout and Power Bypass

It is good practice to design a layout with a compact, minimum lead length. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance. Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µF to 0.1µF chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency fluctuations (see Figure 43). Also, note that the digital ground should be remotely connected to a point on the analog ground to minimize ground bounce.

Maintains constant deviation of resistance settings

For users who need non-volatile but cannot justify the additional cost of EEMEM, the AD5243/AD5248 can be viewed as a low-cost alternative by maintaining a constant offset to maintain the wiper setting. The AD5243/AD5248 are designed for low power applications, enabling low power consumption even in battery powered systems. The graph in Figure 44 shows the power dissipation of a 3.4V, 450mAhr Li-Ion cell phone battery connected to the AD5243/AD5248. Over time, measurements show that the device draws about 1.3 microamps of power, which is negligible. Over 30 days, the battery was less than 2% charged, most of which was due to leakage currents inherent in the battery itself.

This shows that continuously biasing a potentiometer can be a practical approach. Most portable devices do not require battery removal for charging. Although the AD5243/AD5248's resistor setting is lost when the battery needs to be replaced, such events are fairly infrequent, so the lower cost and small size offered by the AD5243/AD5248 justify this inconvenience. If total power is lost, the user should be provided with a means to adjust the settings accordingly.

I2C interface

I2C compatible, 2-wire serial bus

The 2-wire IC compatible serial bus protocol operates as follows:

1. The host initiates a data transfer by establishing a start condition, a high-to-low transition on the SDA line when SCL is high (see Figure 45). The following bytes are the slave address bytes, consisting of the slave address and an R/W bit (this bit determines whether the slave device reads or writes data). The AD5243 has a fixed slave address byte, while the AD5248 has two configurable address bits, AD0 and AD1 (see Figure 10).

The slave whose address corresponds to the transmit address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers. If the R/W bit is high, the master device reads from the slave device. On the other hand, if the R/W bit is low, the master writes to the slave.

2. In write mode, the second byte is the instruction byte. The first bit (MSB) of the instruction byte is the RDAC subaddress select bit. A logic low selects channel 1 and a logic high selects channel 2.

The second MSB, SD, is an off bit. When the wiper is shorted to terminal B, a logic high causes terminal A to open. This operation produces almost 0Ω in rheostat mode and 0 V in potentiometer mode. It should be noted that the shutdown operation does not interfere with the contents of the registers. When the AD5243 or AD5248 comes out of shutdown, the previous settings are applied to the RDAC. Additionally, new settings can be programmed during shutdown. When the part returns from the closed state, the corresponding VR settings are applied to the RDAC. The remaining bits in the instruction byte are don't care bits (see Figure 10).

After acknowledging the command byte, the last byte in the write mode is the data byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 45 and Figure 46).

3. In read mode, the data byte follows the acknowledgment of the slave address byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (slightly different from write mode, where there are 8 data bits followed by an acknowledge bit). Likewise, transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 47 and Figure 48).

Note that the channel of interest is the channel previously selected in write mode. If the user needs to read the RDAC value of two channels, the first channel needs to be programmed to write mode and then changed to read mode to read the first channel value. After that, the user must return the device to write mode with the second channel selected, and read the second channel value in read mode. The user does not need to issue frame 3 data bytes in write mode for subsequent readback operations. The user should refer to Figure 47 and Figure 48 for the programming format.

4. After reading or writing all data bits, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during 10 clock pulses to establish a stop condition (see Figure 45 and Figure 46). In read mode, the master responds with a no to the ninth clock pulse (ie the SDA line is held high). The master then drives the SDA line low before 10 clock pulses, which will go high to establish a stop condition (see Figure 47 and Figure 48). The Repeat Write feature provides the user the flexibility to update the RDAC output multiple times after addressing and instructing the part only once. For example, after the RDAC acknowledges its slave address and instruction byte in write mode, the RDAC output is updated on each successive byte. However, if a different instruction is required, the write/read mode must be restarted with the new slave address, instruction and data bytes. Likewise, the repeated read function of the RDAC is also allowed.

read mode

I2C Controller Programming

write bit pattern

read bit pattern

Multiple devices on one bus (AD5248 only)

Figure 49 shows four AD5248 devices on the same serial bus. Each has a different slave address because of the different states of their AD0 and AD1 pins. This allows each device on the bus to write or read independently. The master output bus driver is an open-drain pull-down in a fully integrated circuit compatible interface.

Dimensions