feature

●Complete analog interface; T1, E1 and MDSL operation

●Clock scalable speed

●Single-chip solution

●+5V only (5V or 3.3V digital)

● 250 mW power consumption; 48-pin SSOP

●Operating temperature is -40°C to +85°C

illustrate

Burr Brown's analog front end greatly reduces the size and cost of an HDSL or MDSL system by providing all the active analog circuitry required to interface with a Metalink MtH1210B HDSL digital signal processor or an external compromise mix and 1:2.3 HDSL line transformer. All internal filter responses as well as a clocked pulse generator output scale allow the AFE1105 to operate at bit rates ranging from 196kbps to 1.168Mbps.

Functionally, this unit is divided into a transmit and receive part. Sends partially generated, filtered, and buffered output 2B1Q data. The receive section filters and digitizes the received symbol data to call the MtH1210B. The HDSL analog interface is a monolithic device fabricated on 0.6μCMOS. It operates at a +5V supply. It is packaged in a 48-pin SSOP package.

Typical performance curve

Pulse transformer output

Unless otherwise specified, typically at 25°C, AVDD=+5V and DVDD=+3.3V.

theory of operation

The transmission channel consists of a switched capacitor pulse forming network and a differential line driver. The pulse forming network receives symbol data from the XMTDA output of the MtH1210B and generates a 2B1Q output waveform. The output meets the pulse shielding and power spectral density requirements for E1 mode in European Telecommunications Standards Institute document RTR/TM-03036 and Sections 6.2.1 and 6.2.2.1 for T1 mode in Bellcore Technical Advisory TA-NWT-001210. Differential line drivers use a combined output stage that combines Class B operation (for driving large signals efficiently) with Class AB operation (for minimizing crossover distortion).

The receive channel is designed around a fourth-order delta-sigma A/D converter. It includes a differential amplifier designed to reduce first-order analog crosstalk with an external compromise mix. Also includes a programmable gain amplifier with a gain of 0dB to +9dB. A delta-sigma modulator operating at an oversampling rate of 24 produces 14-bit resolution at output rates up to 584kHz. The basic functions of the AFE1105 are shown in Figure 1 below.

The receive channel works by adding two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). The connection of these two inputs is described in the paragraph titled "Echo Cancellation in AFE" in order to subtract the mixed signal from the line signal. The equivalent gain of each input in a differential amplifier is 1. The resulting signal is then passed to a programmable gain amplifier that can be set from 0dB to 9dB of gain. The ADC converts the signal into 14-bit digital words rxD13-rxD0.

rxLOOP input

rxLOOP is the loopback control signal. When enabled, the rxLINEP and rxLINEN inputs are disconnected from the AFE. The rxHYBP and rxHYBN inputs remain connected. Loopback is enabled by applying a positive signal (logic 1) to rxLOOP.

Echo Cancellation in AFE

The rxHYB input is designed to be subtracted from the rxLINE input for first order echo cancellation. To achieve this, note that the rxLINE inputs are connected to signals of the same polarity on the transformer (positive to positive and negative to negative), while the rxHYB inputs are connected to opposite polarities via a compromise mix (negative to positive and positive to negative), as shown in Figure 2 shown.

Receive data encoding

The data from the receive channel A/D converter is encoded as two's complement.

Receive channel programmable

gain amplifier

The gain of the amplifier at the input of the receive channel is set by two gain control pins, rxGAIN1 and rxGAIN0. The resulting gain between 0dB and +9dB is shown below.

rxHYBAND rxLINE input antialiasing filter

The –3dB frequency of the input antialiasing filter for the differential inputs of rxLINE and rxHYB should be approximately 1MHz. Recommended filter values for the two input resistors are 750 Ω and 100 pF for the capacitor. The two 750Ω resistors and 100pF capacitor together produce a –3dB frequency just above 1MHz. The 750Ω input resistance will minimize the voltage divider losses and the input impedance is the AFE1105.

This circuit is suitable for both T1 and E1 rates. For slower rates, an anti-aliasing filter will provide the best performance, with a -3dB frequency approximately equal to the bit rate. For example, an a–3dB frequency of 500kHz applies to a single pair bit rate of 500kbps.

rxHYB and rxLINE input bias voltage

The transmitter output on the txLINE pin is centered at 2.5V at midscale. However, in the circuit shown in Figure 2 above, the rxLINE input signal is centered at 1.5V.

Inside the AFE1105, the rxHYB and rxLINE signals are subtracted as described above in the paragraph on echo cancellation. This means that the rxHYB input needs to be centered at 1.5V, just like the rxLINE signal is centered at 1.5V. REFN (Pin 36) is a 1.5V voltage source. The external compromise hybrid must be designed so that the signal at the rxHYB input is concentrated at 1.5V.

receive timing

The rxSYNC signal controls part of the A/D converter decimation filter and the A/D converter's data output timing. It is generated by the user at the symbol rate and must be synchronized to txCLK. The rising edge of rxSYNC can occur at the falling edge of txCLK, or it can be shifted by the user in increments of 1/48 of the symbol period to one of 47 discrete delay times after the falling edge of txCLK.

The bandwidth of the A/D converter decimation filter is equal to half the symbol rate. The data output rate of the A/D converter is twice the symbol rate. The specification of the AFE1105 assumes the use of one A/D converter output per symbol period and ignores the other interpolated output. The receive timing diagram above suggests using the rxSYNC pulse to read the first data output in a symbol period. Either data output can be used. Both data outputs can be used for more flexible post-processing.

normative discussion

echo not canceled

The key to measuring transceiver performance is non-cancelling echoes. Measurements are made as shown in Figure 4. The AFE is connected to an output circuit including a typical 1:2 line transformer. The lines are simulated by 135Ω resistors. The symbol sequence is generated by the tester and applied to the input of the AFE and adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the undeleted echo signal. Once the filter taps have converged, the RMS values of the undeleted echoes are calculated. Since there is no far-end signal source or additional line noise, the uncancelled echoes only contain noise and linearity errors generated in the transmitter and receiver.

The datasheet value for Uncanceled Echo is the ratio of the RMS Uncanceled Echo (referring to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω or 1.74Vrms). This echo value was measured under various conditions: loopback enabled (line input open); loopback disabled in all receiver gain ranges; and line shorted (S1 closed in Figure 4).

layout

The analog front end of an HDSL system has many conflicting requirements. It must receive and transmit digital outputs at fairly high speeds, phase lock to a high-speed digital clock, and convert line inputs to high-precision (14-bit) digital outputs. Therefore, the AFE1105 actually has three parts: a digital part, a phase-locked loop and an analog part.

The supply voltage range of the digital part of the AFE1105 is 3.3V to 5V. This supply should be separated from digital ground and a 0.1µF ceramic capacitor placed close to DGND (pin 12) and DVDD (pin 13). Ideally, both the digital power plane and the digital ground plane should be connected above and below the digital pins (pins 3 to 26) of the AFE1105. However, DVDDs can be provided by wide printed circuit board (PCB) traces. A digital ground plane is strongly recommended under all digital pins.

The PLL is powered by PVDD (pin 2) and its ground is referenced to PGND (pin 1). Note that PVDD must be in the range of 4.75V to 5.25V. This part of the AFE1105 should be separated from the two 10µF tantalum capacitors as well as the 0.1µF ceramic capacitor. Ceramic capacitors should be placed as close as possible to the AFE1105. The placement of the tantalum capacitors is not that critical, but should be close together. In each case, the capacitor should be connected between PVDD and PGND.

In most systems, it is natural to obtain PVDD from the AVDD supply. A 5Ω to 10Ω resistor should be used to connect PVDD to the analog power supply. This resistor is combined with a 10µF capacitor to form a low pass filter - preventing glitches on AVDD from affecting PVDD. Ideally, PVDD would originate from the analog power supply (through a resistor) near the PCB power connector. Likewise, PGND should be connected to a large PCB trace or small ground plane that returns to the power connector under the PVDD power path. The PGND "ground plane" should also extend below PLLIN and PLLOUT (pins 47 and 48).

The rest of the AFE1105 should be considered analog. All AGND pins should be connected directly to a common analog ground plane, and all AVDD pins should be connected to an analog 5V power plane. Both planes should have a low impedance power path.

Ideally, all ground planes and traces and all power planes and traces should return to the power connector before connecting them together (if necessary). Each ground and power wire should be routed against each other, should not overlap any part of the other wire pair, and should be at least 0.25 inches (6mm) apart. One exception is that the digital and analog ground planes should be connected under the AFE1105 via a small trace.