HI5628 is an 8-bit dual 125MSPS D/A converter implemented in advanced CMOS process. Operating from a single +5V to +3V supply, the converter provides 20.48mA full-scale output current and includes an input data register. Low fault energy, high frequency domain performance is achieved through the use of segmented architecture. The single DAC version is the 10-bit version present in the HI5660, HI5760 and HI5728. This DAC is a member of the CommLink 8482 ; a communicative home device.

feature

throughput. 125 ms/s

low power. 330mW at 5V, 170mW at 3V

Integral linearity error. LSB ±0.25

Differential linearity. LSB ±0.25

Channel isolation (typical). 80 dB

SFDR to Nyquist at 10MHz output. 60 dB

Internal 1.2V Bandgap Reference Voltage

Single supply from +5V to +3V

CMOS compatible input

Excellent spurious free dynamic range

application

direct digital frequency synthesis

Wireless communication

signal reconstruction

Arbitrary Waveform Generator

Test Equipment

high resolution imaging system

Absolute Maximum Ratings Thermal Information

Digital supply voltage DVDD to DCOM. +5.5V

Analog supply voltage AVDD to ACOM. +5.5V

Ground, ACOM to DCOM. -0.3V to +0.3V

Digital input voltage (D7-D0, CLK, sleep). DVD+0.3V

Internal reference output current. 0 microamps

Reference input voltage range. Average voltage +0.3V

Analog output current (IOUT). 24 mA

operating conditions

temperature range. -40 degrees Celsius to 85 degrees Celsius

Thermal Resistance (Typical, Note 1) θJA (oC/W)

LQFP package. 75

maximum junction temperature. 150 degrees Celsius

Maximum storage temperature range. -65 degrees Celsius to 150 degrees Celsius

Maximum lead temperature (10s for soldering). 300 degrees Celsius

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation of the device under the above or any other conditions stated in the operating section of this specification is not implied.

Note:

1. θJA is measured in free air with components mounted on an evaluation PC board.

Electrical Specifications AVDD=+5V, DVDD=+5V, VREF=internal 1.2V, IOUTFS=20mA, TA=25oC, for all typical values. Data given is per channel except "Power Characteristics"

Electrical Specifications AVDD=+5V, DVDD=+5V, VREF=internal 1.2V, IOUTFS=20mA, TA=25oC, for all typical values. Data given is per channel except "Power Characteristics" (continued)

Electrical Specifications AVDD=+5V, DVDD=+5V, VREF=internal 1.2V, IOUTFS=20mA, TA=25oC, for all typical values. Data given is per channel except "Power Characteristics" (continued)

notes:

2. Gain error is measured as the error in the ratio of the full-scale output current to the current through RSET (typically 625µA). Ideally the ratio should be 32.

3. Parameters guaranteed by design or characterization, not production tested.

4. Spectral measurements with differential transformer coupled output and no filtering.

5. The clock of both channels is 50MSPS, and the output frequency is 1MHz.

6. The clock of both channels is 100MSPS, and the output frequency is 40MHz.

7. See Normative Definitions.

8. For operation below 3V, it is recommended to reduce the output current to 12mA or lower to maintain optimum performance. DVD and AVDD do not have to be equal.

9. For operation above 125MHz, a power supply of 3.3V or higher is recommended. The part operates from a supply voltage below 3.3V at clocks above 125MSPS, but with reduced performance. (Only for 165MHz version).

10. The clock of both channels is 60MSPS, and the output frequency is 10MHz.

canonical definition

The integrated linearity error, INL, is the worst measured deviation from the best-fit straight line data at the instance point along the transmission curve. Differential Linearity Error, DNL, is the step output deviation from code to code. The ideal step size should be 1 LSB. DNL specifications less than or equal to 1 LSB guarantee monotonicity. The output settling time is the time it takes for the output to stabilize within the specified measurement error range from the start of the output transition. This measurement is done by switching from code 0 to 64, or quarter scale. The termination impedance is 25Ω because the output is 50Ω and the oscilloscope's parallel resistance is 50Ω for the input. This also helps address the specified error band without overdriving the scope. Single point fault zone, whether switching transients occur at the output during code transitions. It is measured as the area under the overshoot portion of the curve expressed as a volt-time specification. The full-scale gain error is the ideal ratio of 32 between the error output current and the full-scale adjustment current (via RSET). The full-scale gain drift is measured by setting the data input through a known resistor as the temperature goes from TMIN to Lynx. It is defined as the maximum deviation from this value measured at room temperature as either TMIN or TMAX. Units are ppm (full scale range) of FSR per degree Celsius.

Spurious Free Dynamic Range, SFDR, is the difference in amplitude from the fundamental harmonic to the maximum harmonic or within a specified window. The output voltage conforms to the range, which is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage will not violate the compliance range. Offset error, by setting the data input to pass a known resistance. Offset error is defined as 0 mA of maximum offset output current. By setting the data input to all through known resistance changes with temperature. It is defined as the maximum deviation from this value measured at room temperature as either TMIN or TMAX. Units are ppm (full scale range) of FSR per degree Celsius. Power supply rejection, using a single power supply to measure the supply. Its nominal +5V variation is ±10%, and note the DAC full-scale output. The reference input is multiplied by the bandwidth, defined as the 3dB bandwidth of the voltage reference input. It is measured using a sine waveform as an external reference with the digital input set to 1 and the frequency being increased until the amplitude of the output waveform is 0.707 its original value. Internal reference voltage drift, defined as the maximum deviation from the room temperature measurement to the value measured at TMIN or TMAX. Unit is ppm/degree C

Detailed description

HI5628 is a dual 8-bit current output CMOS digital to analog converter. It has a maximum update rate of 165MSPS and can be powered from a single or dual supply in the recommended +3V to +5V range. It consumes less data exchange when using +5V power supply and 100MSPS. The architecture is based on a segmented current source configuration that reduces faults by reducing the amount of current switching at any time. The five largest current sources represent equivalent currents by the 31 main current sources. The three LSBs are sourced by binary weighted currents. Consider the input pattern to the converter, which ranges from 0 to 255. The three LSB current sources will start counting. When they reach their full high state (decimal value 7) they both turn off and the first major current source turns on if the next code needs to be calculated. Continuing to count up, the 3 lsbs will count up another 7 codes, then the next main current source will turn on and all three lsbs will turn off. The process of turning on a single equivalent high current source turns off the three LSBs each time the converter arrives and turning off the additional 7 codes greatly reduces the failover point for either one. In previous architectures with binary weighted current sources or binary weighted current source resistor ladders, the converter may have the amount of current that turns on and off at some worst-case transition points such as mid-scale and quarter-scale big change. By drastically reducing the current switching at certain "primary" transitions, there will be a significant reduction in converters, improving settling times and transient issues. Digital input and terminal HI5628 digital input is guaranteed to reach CMOS level. However, by lowering the digital threshold due to the input, the supply voltage is about half the supply voltage of the 3V buffer. This internal register is updated on the rising edge of the clock. To reduce reflections as much as possible, terminate the implementation appropriately. If the line inputs driving the clock and digital are 50Ω lines, the 50Ω termination resistors should be as close as possible to the converter inputs, connected to the digital ground plane (if a separate ground is used). Ground Plane If separate digital and analog grounds are used, the digital functions of the device and their corresponding components shall be on the digital ground plane and terminated at the digital ground. The same goes for analog components and analog ground planes. This converter will work fine on a single ground plane, as the evaluation committee was formed on this

Noise reduction

To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter's power supply pins, AVDD and DVD. Also, should the layout be designed to use separate digital and analog grounds, these capacitors should be terminated to digital ground DVD and analog ground for AVDD. Additional filtering is recommended using on-board power supplies. The voltage reference unit's internal voltage reference has a value of +1.2V and has a drift factor of ±60ppm/oC over the temperature range of the converter at full load. It is recommended that a 0.1µF capacitor should be placed as close as possible to the REFIO pin, connected to analog ground. The return pin (15) selects the reference. If pin 15 is tied low (ground). If an external reference is required, then pin 15 should be connected to high (analog supply voltage) and the external reference driven to REFIO, pin 23. The scaled output current of all converters is a function of voltage using the reference and the value of RSET. IOUT should operate at less than 2mA through, 2mA to 20mA range is possible, with performance degradation. If using the internal reference, VFSADJ will be equal to about 1.16V (pin 22). If an xref is used, VFSADJ will be equal to the xref. Calculate IOUT (full scale) as: IOUT (full scale) = (VFSADJ/RSET) x 32. If an internal voltage reference (1.16V) and a 1.86kΩ RSET resistor are used, the input encoding of the output current will look like this:

output

IOUTA and IOUTB (or QOUTA and QOUTB) are complementary current outputs. The sum of the two currents is always equal to the full-scale output current minus 1LSB. If single-ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that unused outputs be grounded or similarly terminated. The voltage developed at the output must not violate - a 0.3V to 1.25VR load should be chosen so that the output voltage produces a scaled current simultaneously with full output, as described in the "References" section above. If you are driving a known line impedance, you should choose an output load resistor impedance that matches this. The output voltage equation is: VOUT = output X load. These outputs can be used in differential to single-ended arrangements for better harmonic rejection. The SFDR measurements in this datasheet use a 1:1 transformer on the DAC output (see Figure 1). When the center tap is grounded, the output swing 17 at pin 16 is biased at zero volts. Note that the negative voltage output here meets the range limit is-300mV, apply a maximum 600mVP-P amplitude to use this configuration. The loading shown in Figure 1 will be if the full-scale output current of the DAC is set to 20 mA.

Allowing the center tap to float will result in the same transformer output, but the output pin of the DAC will have a positive DC offset. The 50Ω load transformer on the output represents the input impedance of the spectrum analyzer.