The AAT4684 OV...

  • 2022-09-23 10:10:12

The AAT4684 OVPSwitch™ is a member of the Skyworks Application Specific Power MOSFET™ (ASPM™) product family.

General Instructions

AAT4684 OVPSwitch 8482 ; is a member of the Skyworks Application Specific Power MOSFET™ (ASPM™) product family. This is a P-channel MOSFET power switch with precise overvoltage protection control designed to protect low voltage systems from high voltage faults up to +28V. If the input voltage exceeds the programmed overvoltage threshold, the P-channel MOSFET switch turns off to prevent damage to the output load circuit. The AAT4684 has an internally programmed overvoltage trigger point, or as an adjustable version programmed by two external resistors.

The AAT4684 also includes an undervoltage lockout (UVLO) protection circuit that will put the device into sleep mode at low input voltages, consuming only <1µA current.

The AAT4684 is available in a small lead-free 12-pin TSOPJW package and is suitable for operation over the -40°C to +85°C ambient temperature range.

feature

• Overvoltage protection up to +28V

• Fixed or adjustable over voltage protection threshold • 3V under voltage lockout threshold

• Fast OVP response:

▪ 1μs (max) to overvoltage transient

• Low operating quiescent current

▪ Typical 30μA

▪ 1μA max in shutdown (disabled)

• 100m 61527 ; typical (130m max) R, 4.5VDS (on)

• 1.8A maximum continuous current

• Temperature range: -40°C to 85°C

• Available in TSOPJW-12 packaging

application

Mobile phones; digital cameras; GPS; MP3 players; personal data assistants (PDAs); USB hot-plug/live-plug devices.

Typical Application (Adjustable Version)

Typical features

Functional block diagram

Function description

The AAT4684 provides overvoltage protection up to 28V when powering low-voltage systems such as cell phones, MP3s, and pdas, or when charging Li-Ion batteries with improperly regulated power supplies. The AAT4684 is inserted between the mains or charger power supply and the load to be protected. The AAT4684 integrated circuit consists of a low-resistance P-channel MOSFET, under-voltage lockout protection, over-voltage monitoring, a fast shutdown circuit, and a fault output flag.

In normal operation, the P-channel MOSFET acts as a slew rate controlled load switch, connecting and disconnecting power from input to output. Low-resistance MOSFETs are used to reduce the voltage drop between the voltage source and the load, reducing power dissipation. When the voltage at the input exceeds the overvoltage protection trip voltage (either internally set or externally set to the OVP pin via a shunt), the device immediately turns off the internal P-channel FET, disconnecting the load from the abnormal input and preventing damage to any downstream components cause damage. At the same time, a fault flag will be raised to remind the system that there is a problem.

If an overvoltage condition is applied while the device is enabled, the switch will remain closed.

Under Voltage Lockout (UVLO)

The AAT4684 has a fixed 3.0V undervoltage lockout level (UVLO). When the input voltage is less than the UVLO level, the MOSFET is turned off. A 100 mV hysteresis is included to ensure circuit stability.

Over voltage protection

The adjustable version of the AAT4684 has an overvoltage trip threshold of 1.1V to ±1.5% on the OVP pin. The overvoltage trip point (see Table 1) can be adjusted anywhere within the input voltage range through a resistive divider from IN to GND on the OVP pin. Once the overvoltage trip level is triggered, the PMOS switch controller will Turn off the PMOS in less than 1μs.

The AAT4684 fixed version can also be used with a 6.5V input voltage trip point integrated inside the resistor divider. The fixed AAT4684 is not connected to the internal OVP circuit and pin 11 is designed to be left unconnected.

FLT output

The FLT output is an active low open-drain fault (OV) reporting output. A pull-up resistor should be connected from the FLT to the logic I/O voltage of the host system. In the event of an overvoltage fault (with only about 1µs of inherited internal circuit delay), the FLT will be asserted immediately.

The FLT signal is blanked for 10ms before de-evaluation.

Overheating Protection (OTP)

If the ambient temperature of the device exceeds T, turn off the OVP switch and turn the pin low. When the junction temperature falls below T-25°C, the OVP switch will automatically resume.

EN input

EN is an active low enable input. EN is driven low, grounded, or left floating in normal device operation. Bring EN high to turn off the MOSFET. Toggling EN during overvoltage or UVLO conditions will not override the fault condition and the switch will remain open.

Equipment operation

At initial power-up, if V V (1.1V), the PMO is delayed. If UVLO

application information

Over voltage protection

The AAT4684 overvoltage protection circuit provides fast protection against transient voltage spikes and short high voltage spikes from the power line. The AAT4684 quickly disconnects the input power to the load without causing any damage to sensitive components. In portable product applications, if the user removes the battery pack during charging, this operation will generate large transients and high voltage may occur spikes, which can damage other electronics in the product, such as battery chargers. Plugging the AC/DC wall adapter's hot plug into an AC outlet can generate and release voltage spikes from the transformer. Therefore, some sensitive equipment in the product may be damaged. Placing the AAT4684 between the power line and the sensitive device can avoid voltage spikes within 0.7μs, disconnecting the input power supply from other devices.

Figure 2 shows the response time of the overvoltage protection from the test circuit (Figure 1). The input voltage is rapidly increased from 5V to 12V through voltage surges or voltage spikes. The voltage on the OVP pin also rises until the trigger point is triggered. At this point, the FLT pin is pulled low and the output voltage begins to drop. Figure 3 shows a zoomed-in capture of the OVP response time; the output is disconnected from the input within 700ns.

Adjustable Version - Overvoltage Protection Resistor

The overvoltage protection threshold is programmed by two resistors R1 and R2. To limit the current through the external resistor string while maintaining good noise immunity, use a smaller resistor value such as 10KΩ for R2. Using a larger value will further reduce the system current, but will also increase the impedance of the OVP node, making it more sensitive to external noise and interference.

The recommended value of R2 is 110KΩ. Once the overvoltage protection voltage is set, R1 can be calculated by the following formula.

Table 1 summarizes the resistor values for various overvoltage settings. Program the desired OVP setting using 1% tolerance metal thin film resistors.

input capacitor

A 1µF or larger capacitor is generally recommended, as the capacitor should be placed as close as possible to the VIN pin of the device. Ceramic, tantalum, or aluminum electrolytic capacitors can be selected for C. There is no specific capacitor equivalent series resistance (ESR) requirement for C. However, for higher current operation, ceramic capacitors are recommended for C due to their inherent ability to withstand input current surges from low impedance sources, such as batteries in portable equipment, than tantalum capacitors.

Capacitors are usually manufactured with different voltage ratings. 16V, 25V and 50V are available for OVP applications. If the maximum possible surge voltage is known, choose a capacitor rated at least 5 volts higher than the maximum possible surge voltage. Otherwise, 50V rated capacitors are usually suitable for most OVP applications to prevent any surge voltage.

output capacitor

To ensure stability when the current limit is active, a small output capacitor of about 1µF is required at the output. Likewise, for output capacitors, there are no specific capacitor ESR requirements. If required, C can be increased to accommodate any load transient conditions.

fault sign

If the input voltage to the AAT4684 exceeds a pre-programmed value, a fault flag is provided to warn the system of an overvoltage trip point. Since the fault is open-drain, it should be pulled to the input/output rails and less than the maximum operating voltage of 6.5V.

Thermal Factors and High Output Current Applications

The AAT4684 is designed to provide continuous output load current. The limiting characteristic of the maximum safe output load current is the package power dissipation. To obtain high operating currents, careful consideration must be given to device layout and circuit operating conditions. The following discussion assumes the load switch is mounted on a printed circuit board, using the minimum recommended footprint described in the "Printed Circuit Board Layout Recommendations" section of this datasheet. At any given ambient temperature (T), the maximum package power dissipation can be determined by the following equation:

The constants for the AAT4684 are the maximum junction temperature (T=125°C) and package thermal resistance (θ=160°C/W). Worst case conditions are calculated at maximum operating temperature T=85°C. Typical conditions are calculated under normal ambient conditions, where T=25°C. At T=85°C, P=250mW. At T=25°C, P=625mW.

The maximum continuous output current of the AAT4684 is the package power dissipation and the R of the MOSFET at T. Calculate the maximum R of the MOSFET at T by increasing the maximum room temperature.

For the maximum current, please refer to the following formula:

printed circuit board layout

Suggest

For proper thermal management and to take advantage of the low R value of the AAT4684, certain board layout rules should be followed: wider than normal lines should be used for VIN and VOUT, and GND should be connected to the ground plane. To maximize the thermal dissipation and power handling capability of the AAT4684 TSOPJW-12 package, the ground plane area of the ground pins should be as large as possible. For best performance, C and C should be placed close to the packing pins. See Figures 3 and 4.

Evaluation Board Schematic

Evaluation Board Layout

Ordering Information

package information