feature

8-bit High Speed Single/Dual/Quad ADC Single-Channel Mode: FSmax=1000msps Dual-Channel Mode: FSmax= 500 MSPS Quad-Channel Mode: FSmax= 250 MSPS 8226 ; Integrated Crosspoint Switch (Mux Array) 1x to 50x Digital Gain No Lost codes up to 32x 1X gain: 49.8dB SNR. 10X Gain: 48dB SNR Internal Low Jitter Programmable Clock Divider Ultra Low Power 710mW including 1000ms I/O per second Reference circuit, no external components required Coarse and fine gain control Digital fine gain adjustment for each ADC Internal offset correction 1.8V supply voltage Control interface 1.7-3.6V CMOS logic on pins QFN 48 (LP7D) package

typical application

USB powered oscilloscope digital oscilloscope satellite receiver

Pin Compatible Parts

HMCAD1511 is pin compatible with HMCAD1520

The HMCAD1511 is pin compatible and can be configured to operate as a HMCAD1510 with the features and performance described in the HMCAD1510 datasheet

General Instructions

The HMCAD1511 is a versatile, high-performance, low-power analog-to-digital converter (ADC) that uses time interleaving to increase the sampling rate. Integrated crosspoint switches activate user-selected inputs. In single-channel mode, one of the four inputs can be selected as the active input for a single ADC channel. Dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode, any input can be assigned to any ADC channel. An internal, low-jitter and programmable clock divider enables one clock source mode for all operations. The HMCAD1511 is based on a proprietary architecture using an internal reference circuit, serial control interface and serial LVDS/RSDS output data. Data and frame sync clocks are used for data capture at the receiver. Internal 1 to 50 times digital coarse gain, ENOB>7.5 to 16 times gain, allowing digital realization of oscilloscope gain setting. Internal digital fine gain can be set individually for each ADC to calibrate gain error. Various modes and configuration settings can be applied to the ADC through the Serial Control Interface (SPI). Each channel can be powered off individually, and the data format can be selected through this interface. Chip-wide idle mode can be set by a single external pin. The register settings determine the exact function of this pin. The HMCAD1511 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from multiple vendors.

DC specification

AVDD==1.8V, DVDD=1.8V, OVDD=1.8V, FS=125msps, quad mode, 50% clock duty cycle, 1dbfs 70mhz input signal, 1x/0dB digital gain (fine and coarse) unless otherwise illustrate

start initialization

As part of the HMCAD1511 power-up sequence, a reset and power-down cycle must be performed to ensure proper boot initialization. Before starting the initialization, make sure that the power supply voltage is set correctly. A reset can be done in one of two ways:

1. By applying a low-pass pulse (20 ns minimum) on the reset pin (asynchronous).

2. Set the "rst" bit high by using the serial interface. When the seat has been set. The "rst" bit is self-reset to zero. When using this method, do not apply any pulses on the low-pass reset pin. Power cycling can be accomplished in one of two ways:

1. By applying a high speed pulse (at least 20 ns) on the PD pin (asynchronous).

2. Rotate the 'pd' bit in register 0Fhex to the high bit (register value '0200'hex) and then to the low bit (register value '0000'hex). Serial interface HMCAD1511 configuration register can access interface data through the serial interface formed by pins SDATA (serial), SCLK (serial interface clock) and CSN (chip select, low level). The following happens when setting the CSN

Low: Serial data is transferred into the chip On every rising edge of SCLK, the value on SDATA is latched. SDATA is loaded into the register every 24 rising edges of SCLK. An active CSN pulse can load multiples of a 24-bit word of data. If loaded into SDATA during an active CSN pulse, only the first 24 bits are reserved. Extra bits are ignored. Each 24-bit word is divided into two parts: the first 8 bits form the register address and the remaining 16 bits form the register data. Acceptable SCLK frequencies are from 20MHz to several Hz. The duty cycle does not have to be tightly controlled.

Undefined register addresses cannot be written; incorrect behavior may result. When programming registers, unused register bits (empty table cells) must be set to '0'. All registers can be written to when the chip is in power down mode. These registers require a power down cycle when written (see Boot Initialization).

The HMCAD1511 has three main operating modes, which are controlled by register bit channels, as shown in Table 6. Power-down mode, as described in the "Startup Initialization" section, must be activated after or during a change to ensure proper operation. All operating modes utilize interleaving to achieve high sampling speeds. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, and single channel mode interleaves all 8 ADC branches.

clk_divide<1:0> allows the user to apply an input clock frequency higher than the sample rate. The divider divides the input clock frequency by a factor of 1, 2, 4, or 8, as defined by the clk_divide<1:0> registers. By setting the clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all channel number settings. e, g: When the number of channels is increased from 1 to 4, the maximum sampling rate is reduced by a factor of 4. By letting clk_divide<1:0> follow the channel_num<2:0> value and changing it from 1 to 4. The internal clock divider will reduce the sample rate without changing the input clock frequency.

Each ADC is connected to the four input signals via a fully flexible crosspoint switch set by inp_sel_adcx. In single channel mode, any of the four inputs can be selected as the active input for a single ADC channel. In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode, any input can be assigned to any ADC channel. Switching of inputs can be done during normal operation and no additional action is necessary. Switching will happen immediately at the end of each SPI command.

The HMCAD1511 device has multiple power management modes, ranging from a sleep mode with a short boot time to a full boot mode with very low power consumption. There are two sleep modes, both with LVDS clocks (FCLK, LCLK) running to maintain synchronization with the receiver. The first is a light sleep mode (sleep*_ch) with a short startup time, and the second a deep sleep mode (sleep), which has the same startup time as a full power down. set sleep4_ch = '1' will set the channel in the quad channel setup in sleep mode . set sleep2_ch = "1" group of channels in a dual channel setup in sleep mode . Setting sleep1_ch1='1' sets the ADC channel to a single channel setting in sleep mode. This is a light sleep mode with a short startup time. Set sleep='1' to put all channels to sleep but keep FCLK and LCLK running to keep LVDS in sync. The start-up time is the same as the complete power-down time. The power consumption is significantly lower than the set value using the sleep*_ch registers to sleep all channels. Setting pd='1' will power down the chip completely, including the bandgap reference circuit. Starting from this time mode is significantly longer than sleep mode. Synchronization with the LVDS receiver is lost because the LCLK and FCLK outputs are in high-Z mode. Setting pdn_pin_cfg<1:0>="x1" configures the circuit to set the PD pin high. This is equivalent to using sleep*\u ch to set all channels to sleep. There is no way to turn off the channel power using the PD pins separately. Setting pdn_pin_cfg<1:0>='10' configures the circuit to enter (deep) sleep mode when the PD pin is set high (equivalent to setting sleep='1'). When pdn_pin_cfg<1:0>='00' is the default value, the circuit enters the power-down mode when the PD pin is set high.

The lvds_pd_mode register configures whether the lvds data output driver shuts down or stays asleep

and sleep channel mode. The LCLK and FCLK drivers are not affected by this register and are always in sleep and sleep channel modes. If lvds_pd_mode is set to low (default), the lvds output will be put into high Z mode and the driver will be powered down completely. If lvds_pd_mode is set to high, the lvds output is set to the constant 0 and the driver remains on in sleep and sleep channel modes.

theory of operation

The HMCAD1511 is a multi-mode high-speed CMOS ADC consisting of 8 ADC branches configured in channel mode using interleaving to achieve high-speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs. A good gain is adjusted separately for the eight branches. The HMCAD1511 uses LVDS outputs as described in 'Register Description, LVDS Output Configuration and Control'. The required clocks (FCLK, LCLK) to the LVDS interface are generated by the internal PLL. The HMCAD1511 operates from a clock input which can be differential or Single-ended. Sampling each of the four channels to generate a clock using carefully matched clocks from the clock input buffer tree. An internal clock divider is used to control the clock to each ADC during interleaving. This clock tree is controlled by the operating mode. The HMCAD1511 uses an internal Generated reference. The differential reference is 1V. This results in a code for the -1V differential input ADC corresponding to zero, and a +1V to cor differential input response full-scale code (code 255). The ADC uses a pipelined converter structure. Each pipeline stage feeds its output data into digital error correction logic, ensuring excellent differential linearity with no missing codes. The HMCAD1511 consists of two sets of supplies and grounds. The analog power and ground devices are identified as AVDD and AVSS, while the digital devices are Identified as DVD and DVSS. Interleaving effects with sample order interleaving adc will produce interleaving artifacts caused by the gain, offset and timing mismatch between ADC branches. The design of the HMCAD1511 is optimized to minimize these effects. No, however, in order to fully Eliminate mismatches, so additional compensation may be required, especially when using high digital gain settings. This internal digital fine gain control can be used to compensate for gain errors between ADC branches. Due to the optimization of the HMCAD1511, there is no one-to-one between sampling Correspondence order, LVDS output order and branch number. Tables 23, 24 and 25 outline the corresponding branch, LVDS output and sampling order for different high speed modes.

Recommended Use

Analog Input The analog input of the HMCAD1511 ADC is a switched capacitor track and hold amplifier optimized for different operation. Operates at mid-supply common-mode voltage even within the specified range for good performance. The VCM pin provides a voltage suitable as a common-mode voltage reference. The drive capability can be changed by programming the external vcm bc<1:0> registers after the internal buffer that switches the VCM voltage is turned off.

Figure 12 shows a simplified diagram of the operation of the input network. The signal source must have a low enough output impedance to charge the sampling capacitor within one clock cycle. A small external resistor (eg. 22 ohms is recommended) in series with each input as it helps reduce transient currents and damp ringing behavior. The chip side of a small differential shunt capacitor resistor can be used to provide dynamic charging current for improved performance. Resistors and capacitors, so the value must be requested by the application. DC Coupling Figure 13 shows the DC coupling. Note that the common mode input voltage must be controlled according to the specified value. Preferably, the CM-EXT output should be used as a reference for setting the common mode voltage.

The input amplifier may be in a companion chip or a dedicated amplifier. Several suitable single-ended to differential driver amplifiers exist on the market. The system designer should ensure that the selected amplifier is sized enough for the overall system and driving capability to meet the input specifications with HMCAD1511. Detailed configuration and usage instructions must be found in the selected driver's documentation, and the values given in Figure 13 must be adjusted based on recommendations to the driver.

AC coupling can be made into the network using a signal transformer or series capacitors. Figure 14 shows the recommended configuration using trans former. Make sure that the transformer has enough linearity of choice and that the transformer is suitable. The bandwidth should preferably exceed the sampling rate of the ADC many times. It is also important to minimize the phase mismatch between the differential ADC inputs for HD2 performance. This transformer-coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have sufficient performance at high frequencies. Magnetic connections between transformers and PCB traces can affect channel crosstalk and must therefore be taken into account during PCB layout.