For analog CMOS (Complementary Symmetric Metal Oxide Semiconductor), the two main hazards are static electricity and overvoltage (signal voltage exceeding supply voltage). By understanding these two hazards, users can effectively deal with them.

Static electricity

The hazard caused by the electrostatic voltage formed by the accumulation of electrostatic charges (V=q/C=1kV/nC/pF) may break down the thin oxide (or nitride) layer that acts as an insulating layer between the gate and the substrate. This hazard is minimal in a properly functioning circuit because the gate is protected by an on-chip Zener diode, which allows the charge to be lost to safe levels.

However, when plugged into a socket, there may be a large amount of static charge between the CMOS device and the socket. If the first pin plugged into the socket happens not to have a Zener diode protection circuit connected, the charge on the gate can be released through the oxide layer and damage the device.

The following four steps help prevent device damage during system assembly:

Store unused CMOS devices in black conductive foam to prevent charge build-up between pins during shipping;

The operator responsible for device connection should be connected to the system power ground through a plastic ground strap;

Before removing the CMOS device from the protective foam material, the foam material should be grounded with the power supply to discharge the accumulated charge;

After the circuit is inserted into the circuit board, keep the circuit board grounded or shielded when moving the circuit board.

SCR Latch-Up When using analog CMOS circuits, it is safest to ensure that no analog or digital voltages exceeding the supply voltage are applied to the device and that the supply voltage is within the rated range. Nonetheless, it is necessary to implement overvoltage protection. If the mechanism of the problem is understood, protection measures will work well in most cases.

Figure 1 is a circuit diagram and cross-sectional view of a typical CMOS output switch unit. From the connection relationship between different cells and regions, we can draw an equivalent diode circuit diagram (Figure 2). If the analog input voltage at S terminal or D terminal exceeds the power supply voltage.

Figure 1: Circuit diagram and cross-sectional view of a typical CMOS output switch cell

Figure 2: Equivalent Diode Circuit Diagram

The parasitic transistors created by the different diode junctions are then in forward biased mode. These parasitic NPN and PNP transistors form the SCR (Silicon Controlled Rectifier) circuit shown in Figure 3.

Figure 3. Parasitic transistor benefits in CMOS switches

Overvoltage can cause excessive current flow and metallization problems. Usually, the output of the op amp acts as a voltage source at the S terminal or the D terminal, so the current cannot be greater than the limit of the DC output current of the op amp. However, transient induced currents can still damage CMOS devices; therefore, protection is necessary.

Figure 4 illustrates how a parasitic transistor can be prevented from turning on by placing a diode (such as a 1N459 ) in series with the power supply pin. If the S terminal or D terminal voltage is higher than the supply voltage, CR1 and/or CR2 are reverse biased, and the base drive circuit cannot make the transistor conduct. Each CMOS device should be protected by a pair of independent diodes. Although this method is effective, it is not foolproof. If one end of the switch is connected to a negative potential (such as a charging capacitor), and the other end voltage exceeds VDD, then the protection diode is in place.

Figure 4: Circuit Protection Scheme

An avalanche diode at the emitter of Q2 is sufficient to provide base drive to turn Q2 on. For this case, there must be a current-limiting power supply or resistor in series with the capacitor.

If there is a transient overvoltage on either the S terminal or the D terminal, the recommended value for the series resistance at the port powered by the voltage source is 300 to 400 Ω (Figure 4b).