feature

Continuous output current; ADP2119: 2 A; ADP2120: 1.25 A; 145 mΩ and 70 mΩ integrated mosfet input voltage range from 2.3 V to 5.5 V; output voltage 0.6 V to VIN; ±1.5% output accuracy; 1.2mhz fixed switch Frequency; synchronizable between 1 MHz and 2 MHz; selectable PWM or PFM mode operation; current mode architecture; accuracy threshold enable input; power good flag; voltage tracking; integrated soft-start; internal compensation; Startup; UVLO, OVP, OCP, and Thermal Shutdown; 10-lead, 3 mm x 3 mm LFCSP U WD package; 8482 supported by ADIsimPower; Design Tools.

application

load switching points; communications and networking equipment; industrial and instrumentation; consumer electronics; medical applications.

General Instructions

The ADP2119/ADP2120 are low quiescent current, synchronous, step-down DC-DC regulators in a 3 mm × 3 mm LFCSP_WD package. Both devices utilize a current mode, constant frequency pulse width modulation (PWM) control scheme for excellent stability and transient response. Under light load conditions, they can be configured to operate in Pulse Frequency Modulation (PFM) mode, which reduces the switching frequency to save power.

The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V. For the adjustable version, the output voltage can be adjusted from 0.6 V to the input voltage (V), while the fixed output version has preset output voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V. The ADP2119/ADP2120 require minimal external components and provide a high efficiency solution with their integrated power switches, synchronous rectifiers and internal compensation. Each IC draws less than 2 microamps from the input when it is disabled. Other key features include undervoltage lockout (UVLO), integrated soft-start to limit startup, overvoltage protection (OVP), overcurrent protection (OCP) and thermal shutdown (TSD).

Absolute Maximum Ratings

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Long-term exposure to absolute maximum rating conditions may affect device reliability.

Thermal resistance

θ is specified for the worst case, that is, a device soldered in a circuit board for a surface mount package.

Boundary conditions

θ is measured with natural convection on a JEDEC 4-layer board with exposed pads soldered to a printed circuit board (PCB) with thermal vias.

Typical performance characteristics

T=25°C, V=V=5 V, V=1.2 V, L=1.5 μH, C=22 μF, C=2×22 μF unless otherwise stated.

Functional block diagram

theory of operation

The ADP2119/ADP2120 are step-down DC-DC regulators with a fixed frequency, peak current mode architecture that integrates a high-side switch and a low-side synchronous rectifier. The high switching frequency and tiny 10-lead, 3 mm × 3 mm LFCSP_WD package provide a small step-down DC-DC regulator solution. The integrated high-side switch (P-channel MOSFET) and synchronous rectifier (N-channel MOSFET) achieve high efficiency at medium to full load, while the use of PFM mode improves light-load efficiency.

The ADP2119/ADP2120 support input voltages from 2.3 V to 5.5 V and regulate the output voltage to 0.6 V. The ADP2119/ADP2120 also offer preset output voltage options of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.

Control plan

The ADP2119/ADP2120 employ a fixed frequency, peak current mode pulse width modulation (PWM) control architecture that operates in pulse width modulation (PWM) mode at medium to full load, but switches to power factor modulation (PFM) mode at light loads (if enabled) to maintain high efficiency. When operating in fixed frequency PWM mode, the duty cycle of the integrated switch is adjusted to regulate the output voltage. When operating in PFM mode at light loads, the switching frequency is adjusted to regulate the output voltage.

When the load current is greater than the pulse skip threshold current, the ADP2119/ADP2120 operate in pulse width modulation mode. When the load current falls below this value, the regulator smoothly transitions to PFM operation.

PWM Mode Operation

In PWM mode, the ADP2119/ADP2120 operate at a fixed frequency. At the beginning of each oscillator cycle, the P-channel MOSFET switch turns on, applying a positive voltage across the inductor. The current in the inductor increases until the current sense signal crosses the inductor current peak level, turning off the P-channel MOSFET switch and turning on the N-channel MOSFET synchronous rectifier. This applies a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier turns off the N-channel MOSFET for the remainder of the cycle or until the inductor current reaches zero, which causes the zero-crossing comparator to also turn off the N-channel MOSFET.

The peak inductor current level is set by V. V is the output of a transconductance error amplifier that compares the feedback voltage to an internal 0.6 V reference.

PFM Mode Operation

When PFM mode is enabled, the regulator smoothly transitions to variable frequency PFM operation when the load current drops below the pulse skip threshold current. Switching continues only as necessary to keep the output voltage within regulation. When the output voltage drops below the specified value, the part goes into pulse width modulation mode for several oscillator cycles to increase the output voltage back to the specified value. During the waiting time between pulses, both power switches are turned off and the output capacitors supply the load current. The output voltage ripple in this mode is larger than that in PWM mode due to the occasional drop and recovery of the output voltage.

slope compensation

Slope compensation stabilizes the internal current control loop of the ADP2119/ADP2120 near or above 50% duty cycle to prevent subharmonic oscillations. Slope compensation is accomplished by adding an artificial voltage ramp to the current-sense signal during the on-time of the P-channel MOSFET switch. This voltage ramp depends on the output voltage. There is more slope compensation when operating at high output voltages. Slope Compensation The ramp value determines the minimum inductance that can be used to prevent subharmonic oscillations.

enable/disable

The exact analog threshold of the EN input pin is 1.2v (typ) with a hysteresis of 100mv. When the enable voltage exceeds 1.2 V, the regulator turns on, and when it falls below 1.1 V (typ), the regulator turns off. To force the part to start automatically when input power is applied, connect EN to VIN.

When the ADP2119/ADP2120 is turned off, the soft-start capacitor discharges. This will cause a new soft-start cycle to begin when the part is re-enabled.

An internal pull-down resistor (1 MΩ) prevents accidental enablement if EN is left floating.

Integrated soft start

The ADP2119/ADP2120 include integrated soft-start circuitry to limit the output voltage rise time and reduce inrush current at startup. The soft-start time is fixed at 1024 clock cycles.

If the output voltage is precharged before turning on, this part prevents reverse inductor current (which will discharge the output capacitor) by keeping both mosfets off until the soft-start voltage exceeds the voltage on the FB pin.

track

The ADP2119/ADP2120 have a tracking input, TRK, that allows the output voltage to track another voltage (the main voltage). Tracking inputs are especially useful in core and I/O voltage tracking in FPGAs, DSPs and ASICs.

The internal error amplifier includes three positive inputs: the internal reference voltage, the soft-start voltage, and the TRK voltage. The error amplifier regulates the FB voltage to the lowest of the three voltages. To track the mains voltage, connect the TRK pin to a resistive divider for the mains voltage. If not using the tracking function, connect the TRK pin to the VIN.

Oscillator and Sync

To synchronize the ADP2119/ADP2120, drive an external clock at the sync/mode pin. The frequency of the external clock can be in the range of 1 MHz to 2 MHz. During synchronization, the regulator operates only in CCM mode and the switching frequency is synchronized with the external clock.

Current limiting and short circuit protection

The ADP2119/ADP2120 have peak current limit protection circuitry to prevent current runaway. When the inductor peak current reaches the current limit, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle begins. The overcurrent counter is incremented during this period. If the overcurrent counter counts over 10, the part enters hiccup mode and both the high-side and low-side MOSFETs are turned off. The part remains in this mode for 4096 clock cycles and then attempts to restart from soft-start. If the current limit fault is cleared, the component resumes normal operation. Otherwise, after calculating 10 current limit violations, it will enter hiccup mode again.

Over Voltage Protection (OVP)

The output voltage is continuously monitored by a comparator through the FB pin, which is 0.6 V (typ) under normal operation. This comparator is set to activate when the FB voltage exceeds 0.66v (typ), indicating an output overvoltage condition. If the voltage remains above this threshold for 16 clock cycles, the high-side MOSFET turns off and the low-side MOSFET turns on until the current through the low-side MOSFET reaches the limit (-0.6 A for forced continuous conduction mode, 0 A for PFM mode) . After this, both mosfets remain off until FB falls below 0.54v (typ), at which point the part restarts. In this case, the behavior of PGOOD will be described in the Power Good section.

Under Voltage Lockout (UVLO)

The undervoltage lockout circuit is integrated in the ADP2119/ADP2120. If the input voltage drops below 2.1V, the part shuts down and both the power switch and the synchronous rectifier are turned off. When the voltage rises above 2.2V again, the soft-start cycle starts and the part starts up.

Thermal shutdown

A thermal shutdown circuit shuts down the regulator if the ADP2119/ADP2120 header temperature rises above 150°C. Extreme junction temperatures can be the result of high current operation, poor board design, and/or excessive ambient temperatures. A 25°C hysteresis is included, so if thermal shutdown occurs, the part will not resume operation until the die temperature drops below 125°C. When the thermal shutdown is over, the soft-start starts.

Good power (PGOOD)

PGOOD is an active high open drain output that requires a resistor to pull it up to a voltage. High means that the voltage on the FB pin (and therefore the output voltage) is within ±10% of the expected value. A low voltage on this pin means that the voltage on the FB pin is not within ±10% of the desired value. There is a waiting period of 16 cycles after FB is detected as out of bounds.

application information

ADIsimPower Design Tool

The ADP2119/ADP2120 are supported by the ADIsimPower design toolset. ADIsimPower is a set of tools for generating a complete power supply design optimized for specific design goals. These tools enable users to generate complete schematics, bills of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and part count, taking into account the operating conditions and constraints of the IC and all practical external components. For more information on the ADIsimPower design tool, see /ADIsimPower. The toolset is available from this website, and users can also request unpopular boards through the tool.

This section describes the selection of external parts for the ADP2119/ADP2120. A typical application circuit for the ADP2119 is shown in Figure 50.

Output voltage selection

The output voltage of the adjustable version can be set by an external resistor divider, the following formula calculates the output voltage.

To limit the output voltage accuracy degradation due to FB bias current (0.1 µA max) to less than 0.5% (max), ensure that R is less than 30 kΩ.

Sensor selection

The inductor value is determined by the operating frequency, input voltage, output voltage, and ripple current. The smaller the inductance value, the larger the inductor current ripple and the faster the transient response, but the efficiency will be reduced. The larger the inductance value, the smaller the current ripple and the higher the efficiency, but the slower the transient response. As a guideline, the inductor current ripple, ΔI, is typically set to 1/3 of the maximum load current trade-off between transient response and efficiency.

The inductance value can be calculated using the following formula:

Where: VIN is the input voltage. VOUT is the output voltage. ΔIL is the inductor current ripple. D is the duty cycle. D = Credential/Vehicle Identification Number.

When the duty cycle is greater than 50%, the regulator employs slope compensation in the current loop to prevent sub-harmonic oscillations. Internal slope compensation limits the minimum inductance value.

The negative current limit (-0.6 A) also limits the minimum inductance value. The inductor current ripple (ΔI) calculated from the selected inductor should not exceed 1.2 A. The peak inductor current should be kept below the peak current limit threshold and can be based on:

Make sure that the rms current of the selected inductor is greater than the maximum load current and that its saturation current is greater than the peak current limit of the regulator.

Output Capacitor Selection

Output voltage ripple, load step transients, and loop stability determine the choice of output capacitor.

ESR and capacitance determine the output ripple.

Load transient response depends on the inductance, output capacitance and control loop.

The ADP2119/ADP2120 integrate loop compensation to provide a simple power solution design. Table 5 and Table 6 show the typical recommended inductors and capacitors for the ADP2119/ADP2120. X5R or X7R ceramic capacitors are strongly recommended.

The regulator can use higher or lower inductor and output capacitor values, but needs to be checked for system stability and load transient performance. The ADP2119 has a minimum output capacitance of 22µF and the ADP2120 has a minimum output capacitance of 10µF with an inductance range of 1µH to 3.3µH.

Input Capacitor Selection

The input capacitor reduces input voltage ripple caused by switching currents on PVIN. Place the input capacitor as close as possible to the PVIN pin. A 10µF or 22µF ceramic capacitor is recommended. The rms current rating of the input capacitor should be greater than the value calculated by the following formula:

Voltage tracking

The ADP2119/ADP2120 include a tracking function that allows the output (slave voltage) to be configured to track an external voltage (master voltage), as shown in Figure 51.

A common application is coincidence tracking (see Figure 52). Coincidence tracking limits the slave output voltage to be the same as the master voltage until the specified value is reached. Connect the TRK pin to a resistive divider for the mains voltage. For coincidence tracking, set RTRKT = RTOP and RTRKB = RBOT.

The ratio tracking is shown in Figure 53. The slave output is limited to a fraction of the master voltage. In this application, both the slave voltage and the master voltage reach their final values at the same time. The ratio of the slave output voltage to the master voltage is a function of the two dividers (see equation below).

Typical Application Circuit

Dimensions