其中RSENSE是传感元件的电阻值（在TMOSu003d25oC时），B是可从中获得的常数图13，kT是传感元件和控制器之间的温度耦合系数（it结果KTu003d（ TJ-25)/(TMOS-25)), α is the temperature coefficient of sensitive components. Starting from RTC depends on constant B, in turn depends on RTC. It requires an iteration process to correctly design the RTC value. Due to the nature of the thermal sensor, negative offset needs to compensate the active offset introduced by the ITS at the reference temperature, and the resistance settings between the shift tube and the SGND can be set as follows:

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123]

Dynamic video conversion

This device can manage dynamic video code changes and allows running normally in the device. OVP and UVP signals are blocked during each VID conversion and re -activated after the conversion. When dynamically changing the regulatory voltage (D-VID), the system needs to output the capacitor accordingly. This means that additional ID-VID needs to be provided, especially when the output voltage is increased, the threshold must be considered when the current is set. Current result:

Among them, DVOUT is the selected DAC LSB (VRD10.X is 12.5MV, Hammer DAC is 25mV), TVID is between each LSB conversion conversion conversion time interval. OC threshold over overcoming dynamic video will cause the device to enter the constant current limit, thereby reducing the output voltage DV/DT, and it will also cause the D-VID test failure. The method of modifying the device depends on the status of the video selection, and then depends on the selected DAC.

VID_SEL u003d Open (see Figure 14).

Select VRD10.x DAC. The device will modify the VID code of the upper edge of the clock to modify the frequency of the switching of each phase, and wait for the following aspect to confirm the decline. Once the new code is stable, on the next rising edge, the quotation begins to rise or decreases with LSB increment (12.5mV) per clock cycle (still 3 · FSW) until the new VID code is reached. In conversion, VID code changes are ignored; after the conversion is completed, the device will restart the VID on the next available ascending along the upper along the upper along.

Warning:

If the new VID code is more than 1 LSB higher than the previous code, the device will be executed to the frequency of equal to 3 · FSW, until the new code arrives: Therefore, it is recommended Carefully control the VID change rate to carefully control the slope voltage change of the output.

vid_sel u003d ground (see Figure 15).

Select Hammer DAC, when the device is checkedThe VID code modification of the bell rising edge is the same frequency of each phase, waiting for the next confirmation of the next drop edge. A new code is stable. On the next rising edge, the quoting starts with LSB increment or decrease (25mv) per clock cycle until it reaches the new VID code. During the conversion period, the change of the VID code is ignored; the device restarts the surveillance VID after the next rising edge is completed. If the new VID code is more than one digit higher than the previous code, the device will execute the reference of each switching cycle of each switching period until the new code reaches

to enable and disable

This device There are three different power supplies: VCC pin provides internal control logic, VCCDRX power supply provides high -side drivers and drivers. If the voltage at the pin VCC and VCCDRX does not exceed the opening threshold specified in the electrical characteristics, the device is turned off: all the drives keep the MOSFET closed to display high impedance to the load. Once the device is powered correctly, it can ensure that the equipment runs normally, but it can be controlled in different ways:

Export

It can be used for power sorting control of complex systems. Set the freedom of the pin, and the device realizes a soft start -programming voltage. Put the short circuit to SGND and reset the device (in this case, the SS_ end is short -circuited to SGND and is protected from being disabled, unless pre -OVP) is from the lock status, and it is also prohibited to keep all MOSFET closed to display high impedance devices to display high impedance devices Go to load the goods. It can then recover from any lock state (such as OVP and UVP).

NOCPU (Vit [0; 5] u003d 1111 times)

In this case (VID5 status has nothing to do), the device is disabled and all MOSFETs are closed to display high impedance loads. However, it is waiting for any VID code conversion to start the soft start. In this case, the SS U -end pins are short -circuited for SGND

Soft start

During the soft startup process, a slope will be generated, which increases the reference voltage from 0V to the final value of programming. Through VID in the 2048 clock cycle, as shown in Figure 16. Once the soft start, the reference value increases: the upper and lower MOS start switching with closed -loop adjustment, the output voltage begins to increase. At the end of the digital soft start, the SS -end signal is driven by high level. When the reference voltage reaches 0.6V, the owed voltage comparator is enabled, and the overvoltage is always enabled during the soft startup period. The threshold is equal to 115%of the programming reference value or the threshold of ROVP programming (see the relevant chapters).

Output voltage monitor and protection

This device monitors the voltage through the pin vSEN to manage the OVP/UVP state.

UV protection

If the output voltage monitored by VSEN decreases to less than 60%of the benchmark voltage exceeding one clock cycle, the device shuts down all MOSFETs, OSC/fault -driven high level (5V). Conditions are locking; to recover, you need to circulate VCC or OUTEN pins.

Programmable OVP protection

Once the VCC exceeds the opening threshold and the device is enabled (OUTEN u003d 1), the device will provide a programmable overvoltage protection; when the induced voltage exceeds the threshold of the programming, the induced voltage exceeds the threshold of programming The controller permanently opens all low -side MOSFETs and close all high -sides MOSFET to protect the load. OSC/fault pins are driven by high levels (5V), and restart operation requires a power supply or external pin Cy Cling. The OVP threshold is programmed by OVP pin: keeps floating, and the threshold is set to 115%(typical values) of the programming output voltage in the interior. Connect the OVP pin to SGND through the resistor ROVP, and the OVP threshold is turned into a fixed voltage, as shown below: OVPTH u003d 1.455 · ROVP · 12.5μ

Pre -protection (123]

When VCC When the pins are lower than the informant threshold, a preliminary OVP protection opens the low -side MOSFET as long as the FBR pin voltage is greater than 1.8V. When the VCC keeps the threshold of the device and the pre-VP opening threshold, it depends on the status of the outen tube. When the device is closed (and then avoids protected red areas in Figure 17), the power supply is powered by the 5VSB bus as the controller as shown in Figure 17. Overvoltage and under voltage are also activated during soft start (see the relevant chapters).

Over -current protection

According to the selected current reading method, the peak or bottom current of the device limit the sensor enters the constant current Read. Through the design of the RG resistor, the over -current threshold is programmed to ensure that the device will not enter OCP during the normal operation of the device. This value must also be considered to consider the additional current device required during the dynamic VID conversion process. In addition, due to the expansion of the internal threshold, the RG design must consider its minimum IOCTH (minimum value) as follows:

Among them (Inductor sensor) When currently reads the current measured by the current, the IOCPX must be calculated from the corresponding output current value ouT (OCP) as follows (ID-vid must also consider implementing D-VID):

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The current value (iOUT) input (iOUT) is the constant value, where the output current is the constant valueMOSFET sensor) or constant current (inductors sensor), u0026#8710; IPP is an inductor current ripple of each phase, and ID-VID is the additional current (such as applicable) required by D-VID. In particular, due to the peak or valley value of the electrical sensor current (according to the state of CS_SEL), the ripple entity must be considered if it is not neglected, and the impact on the actual OC threshold must be considered.

LS MOSFET detection (CS_SEL u003d opening the road) over current

When the current information IInfox Over reaches a fixed threshold of IOCTH (typical value of 35 μA), the device detects the overcurrent of each phase of each phase. Happening. When this happens, the device will keep the relative LS-MOS FET open, and skip the clock cycle until the threshold crossing back and the IINFOX result is lower than the low threshold. This means that the device limits the bottom of the current ripple of each inductor. After exiting the OC conditions, the LS MOSFET is closed, and the HS is turned on through the PWM comparator under the duty -occupying ratio driver. Keep the LS opening and skip the clock cycle, which will increase the connection time after exiting the OC conditions. Considering the device with this current fluid measurement, it has the greatest connection time dependence with the conveying current given through the following relationship:

In the formula Output current (iOUT u003d ∑ · iPaseX), TSW is the switch cycle (TSW u003d 1/FSW). This linear relationship is 0.80 · TSW at zero -negative load, and at the maximum current of 0.40 · TSW, it is a typical value and causes two different current behaviors to cause the device:

The tons of limited output voltage.

When the current reaches the maximum connection time of IOCPX, this will occur (information u0026 lt; IOCTH). FIG. 18 shows that the maximum output voltage that the device can adjust can be adjusted considering the TON limit applied by the previous relationship. If the expected output characteristics pass through the maximum output voltage, the output voltage will begin to decline after crossing. In this case, the device does not perform constant current restrictions, and only limit the maximum connection time after the previous relationship. Before the UVP or IDROOP u003d 105μA is detected, the output voltage starts to decrease until the characteristics are generated (as shown in Figure 18).

Hengli operation

When the valley current of each phase reaches the IoCPX limit, this will occur (information u0026 gt ;Table of contents). The device enters the quasi -constant current operation: The low -side MOSFET is kept in the power -powered state and turned to the clock cycle below IOCPX (IInfox u0026 LT; IOCTH). High -sides MOSFET can control the power of one ton after the LS is closed.event. This means that when the quasi -constant stream runs, the average current transported can increase a slight increase due to the increase in current ripples. In fact, the increase in the connection time is that the increase in the closing time must reach the bottom of the IOCPX. The worst case is the values u200bu200bwhen the connection time reaches the maximum value. When this happens, the device works in a constant current, and the output voltage decreases with the load. More than the UVP threshold will cause the device to lock the driver of the OSC pin (Figure 19 shows this working status). You can observe the peak current (IPEAK) is greater than IOCPX, but it can be determined as follows:

The power connection correlation.

FIG. 24 shows the location of some small signal components.

The size of the grid and the phase traces must be determined by MOSFET based on the driver provided to the power supply. The robustness of the equipment allows the use of the controller without losing performance. In any case, if possible, it is recommended to shorten the distance between the distance controller and the power part. In addition, because the Phasex pin is the return path of the high -voltage side drive, it can be connected to the MOSFET of the MOSFET source directly to the MOSFET source directly to the high -voltage side. For LS MOSFETS, the return path is PGNDX pin: it can directly connect to the power ground layer.

The self -raising capacitor must be close to the Bootx and Phasex pins as much as possible to minimize the cycle of creation.

The decoupled power container of VCC and SGND should be as close to the related pins as possible.

Deserter containers of VCCDRX and PGNDX should be as close to these pins as possible. This capacitor maintains the peak current required by the low -side MOSFET drive.

Sensitive components must refer to SGND (if.): Set the resistor ROSC, offset resistor ROFFSET, TC resistor RTC and OVP resistor ROVP.

Star Ground: Connect SGND and PGND planes at a point to avoid equipment behavior errors caused by high current transmission.

It is recommended to place an additional ceramic capacitor near HS MOSFET. This helps to reduce heart failure.

VSEN helps reduce the noise of the injection foot.

OUTEN pin filtering vs.sgnd to help reduce the accidental jumping gates caused by coupling noise: Be careful to reduce the mesh needle to reduce the coupling noise when the wiring.

Phase pins peak. Because HS-MOSFET has almost no switch, it can be pins on Phasex. If these voltage peaks overcome the maximum breakdown voltage of the pin, the device can absorb energy and cause damage. The voltage peak must be restricted by appropriate layout; the use of a gate resistance and the Schottky diode are connected in parallelMOSFET and/or cushioning network low -edge MOSFET. When FSW u003d 600kHz, 20NSEC cannot overcome 26V.

Start the additional charging of the capacitor. A system that does not use the Sytky diode may have a large peak on the phase pins. This peak is also limited, but this peak is also a limited result: leading to a self -lifting capacitor overcharge. The additional cost will lead to the worst case of the maximum input voltage. During a specific transient period, the phase voltage is started to overcome the anti -dead braking system. The maximum rated value will also cause equipment failure. In this case, it is recommended to do a small resistance in series on the diode (one resistance can be used in the upstream of the diode anode, which is sufficient for three diode).

current influenza response connection.

Remote buffer: The input connection of this component must be used as a parallel network from the fiber grating routing/to compensate the loss along the output power trajectory, and at the same time, it also avoids picking up any co -model noise. Connecting these pins on a point that is away from the load will cause non -best load adjustment and increase the output tolerance.

current reading: The RG resistor must be injected as close to the noise in the restricted device as much as possible; this pair of RG (RC) -CG network is still effective in the sensor on the induction sensor. The PCB trace line that connects these resistors to the reading point must be used as a parallel record channel to avoid picking up any co -model noise.

The same important is to avoid any offset in measurement. In order to obtain better accuracy, the connection is as close to the sensor element as possible. Summary layout. A small filter capacitor may require a small filter capacitor between the VOUT and SGD on the CSX line, placed near the controller, and allows higher layout flexibility in the current influenza connection.

When embedding the L6711 -based VRD

embedding VRD into the application, you must be careful, because the entire VRD is the most common system that the entire VRD is the switch DC/DC regulator and its must work. Digital system MB or similar. In fact, the latest MB has become faster and stronger: high -speed data bus is more and more commonly generated by VRDs that do not follow the switching noise, which may affect other layout guidelines for data integrity. When wiring in the following circumstances, a few simple dot switching large currents must be considered (large switching large current will cause the trace line of the voltage spikes on the mixed inductor, which will affect the nearby trace lines): on the large current switch VRD trajectory and the trajectory and the trajectory of the large current switch and the trajectory and the trajectory of the large current switch and the trajectory and Maintain a safe protection distance between the data bus, especially at high -speed data bus to reduce noise coupling. When tracking the I/O subsystem routing deviation of the I/O subsystem, keep a safe protection distance or appropriately filter near VRD. The possible cause of noise may be phase connection, MOSFET gate driver and input voltage path (from input large -capacity capacitors andHS drain).If you don't persist, you must also consider the PGND connection on a power supply plane.These connections must be careful of the sensitive data of noise.Because the noise generated is mainly due to the VRM switching activity, noise emissions depends on how fast the current switch is.In order to reduce the level of noise emissions, in addition to the previous reduction of the current slope, and then increase the number of switching times: this will cause increased switching loss, which is a factor that must be considered in other designs of the system.