Features and Benefits

▪ 2-wire step and direction interface

▪ Double bridge full gate drive for N-channel mosfet

▪ Operating voltage exceeds 12 to 50 V

▪ Synchronous rectification

▪ Cross-conduction protection

▪ Tunable mixed decay

▪ Integrated sinusoidal DAC current reference

▪ PWM current control with fixed off-time

illustrate

The A3986 is a dual full bridge gate driver integrated suitable for driving a variety of high power industrial bipolar 2-phase stepper motors (typically 30 to 500 watts). Motor power is provided by an external N-channel power mosfet with supply voltage from 12V to 50V.

This device contains two sinusoidal digital-to-analog converters, reference voltage controllers that generate two independent fixed off-time pulse width modulated currents. They provide a current-regulating MOSFET full bridge for an external power supply.

The motor stepping is controlled by a two-wire step and direction interface, providing full microstep control with half-step, four-step and sixteen-step resolution. Capable of slow, mixed or fast decay modes, the fixed asset time conditioner reduces audible motor noise, improves step accuracy, and reduces power consumption.

Translation is the key integrated circuit that enables this. Just a single pulse at the step input drives the motor one step (full, half, quarter or sixteenth, depending on the microstep selection input). There are no phase sequence tables, high frequency control lines, or complex programming interfaces. This reduces the need for complex microcontrollers.

The above-mentioned supply voltage mosfet required for the high-side N-channel is provided by the bootstrap capacitor. Efficiency is the application of synchronous rectification and power FETs with integrated crossover control to prevent penetration as well as programmable dead time.

In addition to crossover current control, internal circuit protection provides thermal shutdown with hysteresis and undervoltage lockout. No special power-up sequence is required.

This part is available as a 38-pin TSSOP (Package LD). This package is lead free, 100 % matte tin leadframe.

Functional block diagram

Function description

Basic operation

The A3986 is a complete microstepping FET driver with built-in converter for simple operation and minimal control inputs. It is designed to operate two-phase bipolar stepper motors in full, half, quarter and sixteenth order modes. The current in each of the two external power full bridges (full N-channel mosfets) is independently regulated by a fixed off-time PWM control circuit. The full bridge current for each step is set by the external current sense resistor RSENSE in the ground connection of the bridge, the reference voltage VREF, and the value of the DAC output controlled by the converter.

PWM using N-channel MOSFETs provides the most cost-effective solution for high-efficiency motor drives. The A3986 provides all the necessary circuitry to ensure that the gate-source voltage of both the high-side and low-side external mosfets is above 10v and that there is no cross conduction (pass-through) in the external bridge.

Specific functions are described in detail in the following sections.

power supply

Two power connections are required. The motor power supply should be connected to VBB to provide the gate drive level. Internal logic power is provided by the VDD input. The internal logic is designed to operate between 3 and 5.5 volts, allowing the use of 3.3 or 5 volts external logic interface circuits.

Ground The ground pin is the reference voltage for internal logic and analog circuits. No large current flows through this pin. To avoid any noise from the switching circuit, the power ground neutral point should be traced independently.

VREG The voltage at this pin is generated by a low-dropout linear regulator from the VBB supply. It is used to operate the low-side gate drive outputs GLxx and provide charging current for the bootstrap capacitor CBOOTx. To limit the voltage drop when supplying charge current, this pin should be disconnected from the ceramic capacitor CREG to ground. The CREG value should normally be

For PWM frequencies up to 14 kHz, 40 times the value of the bootstrap capacitor. Above 14 kHz, the minimum recommended value can be determined by the following formula:

where CREG and CBOOT are in nF and fPWM is the maximum PWM frequency in kilohertz. VREG is monitored and if the voltage is too low, the output will be disabled.

Refer to the reference voltage VREF at this pin for the maximum (100%) peak current. The REF input is internally limited to 2 V between VREF and VDD when a 20 kΩ pull-up resistor is connected. This allows the maximum reference voltage to be set without the need for an externally generated voltage. An external reference voltage lower than the maximum value can also be input to this pin. The voltage VREF divided by 8 produces the DAC reference voltage level.

OSC internal FET timing is controlled by the master clock typically running at 4 MHz. A resistor, ROSC, connected from the OSC pin to GND sets the frequency (in MHz) to approximately:

where ROSC (unit: kΩ) is usually between 50 kΩ and 10 kΩ. The primary oscillator period is used to derive the PWM off time, dead time and blanking time.

gate drive

The A3986 is designed to drive an externally powered N-channel mosfet. It provides the transient current required for fast charging and discharging to reduce losses in external FETs during switching. The charge and discharge rates can be controlled by an external resistor RGx in series with the gate of the FET. The gate drive circuit introduces a dead time tDEAD between turning off one FET and turning on the complementary FET, thus preventing cross conduction. tDEAD is at least 3 cycles of the main oscillator, but can be extended by 1 cycle to allow oscillator synchronization.

C1A, C1B, C2A, and C2B are used for the high-side connections for the boot capacitor, CBOOTx, and the positive supply of the high-voltage gate driver. When the associated output Sxx terminal is low, the bootstrap capacitor is charged to approximately VREG. When the output voltage rises, this terminal voltage rises with the output voltage to provide the boosted gate voltage required by the high voltage N-channel power mosfet. The bootstrap capacitor should be ceramic with a value of 10 to 20 times the total MOSFET gate capacitance.

GH1A, GH1B, GH2A, and GH2B are high-side gate drive outputs for external N-channel MOSFETs. An external series gate resistor can be used to control the slew rate seen at the gate and thus the di/dt and dv/dt at the motor terminals. GHxx=1 (high) indicates that the top half of the driver is turned on and will supply current to the gate of the high-side MOSFET in the external motor driver bridge. GHxx=0 (low) means that the lower half of the driver is turned on and sinks current from the gate circuit of the external MOSFET to the corresponding Sxx pin.

S1A, S1B, S2A and S2B are connected directly to the motor, these terminals sense the voltage on the load and define the negative supply for the floating high side driver. The discharge current from the high-side MOSFET gate capacitance flows through these connections, which should have low impedance traces to the MOSFET bridge.

GL1A, GL1B, GL2A, and GL2B are low-side gate drive outputs for external N-channel MOSFETs. An external series gate resistor (as close to the MOSFET gate as possible) can be used to reduce the slew rate at the gate, thereby controlling the di/dt and dv/dt at the motor terminals. GLxx=1 (high) indicates that the top half of the driver is turned on and will supply current to the gate of the low-side MOSFET in the external motor driver bridge. GLxx=0 (low) means the lower half of the driver is on and sinks current from the gate of the external MOSFET to the LSSx pin.

The low-side return path for the discharge of the LSS1 and LSS2 gate capacitors is connected through a low-impedance path to the common source of the low-side external FET.

motor control

The speed and direction of the motor are simply controlled by two logic inputs, while the microstepping stage is controlled by another two logic inputs. At power-up or reset, the converter sets the DAC and phase current polarity to the initial initial state (see Figures 2 to 5 for initial state conditions) and sets the two-phase current regulator to mixed decay mode. When a step command signal appears on the step input, the converter automatically sequences the DACs to the next stage (see Table 3 for current stage sequence and current polarity).

The microstep resolution is set by the inputs MS1 and MS2, as shown in Table 1. If the new DAC level is higher than or equal to the previous level, the decay mode of the full bridge will be slow decay. If the new DAC output level is lower than the previous level, the attenuation mode of this full bridge will be set by the PFD1 and PFD2 inputs. This automatic current decay selection improves microstepping performance by reducing current waveform distortion caused by motor BEMF.

A low-to-high transition on the step ms1 and ms2 step inputs puts the translator in sequence and advances the motor one increment. The converter controls the input to the DAC and the current flow in each winding. The size of the increment is determined by the state of the MSx input. According to Table 1, these microstep selection inputs are used to select the microstep format. Changes to these inputs will not take effect until the next rising edge of the input.

Director This direction input determines the direction of rotation of the motor. Clockwise when low, counterclockwise when high. Changes to this input will not take effect until the next rising edge.

Internal PWM current control

Each full bridge is independently controlled by a fixed off-time PWM current control circuit that limits the load current in the phase to the desired value ITRIP. Initially, a pair of diagonal source and sink mosfets are enabled and current flows through the motor windings and current sense resistor RSENSEx. When the voltage across RSENSEx equals the DAC output voltage, the current sense comparator resets the PWM latch, turning off the source MOSFET (slow decay mode) or source MOSFET (fast decay mode). The maximum value of the current limit is set by selecting the voltage at the RSENSE and REF inputs, and the transconductance function is approximated as:

The DAC controlled by the converter steps down the reference voltage VREF in precise steps to produce the sinusoidal reference level required by the current sensing comparator. This limits the phase current trip level ITRIP to a fraction of the maximum current level ITRIP(max), defined as:

The percentages for each step are shown in Table 3.

An internal PWM current control circuit uses the main oscillator to control how long the power mosfet remains off. The off time tOFF is nominally 87 cycles of the main oscillator (21.75µs at 4MHz), but synchronizing with the main oscillator may extend by 1 cycle.

Blanking: This function blanks the output of the current sense comparator when the internal current control switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and switching transients associated with load capacitance. Blank time t is 6 cycles of the main oscillator (1.5µs at 4MHz). Because t follows after the end of tOFF, no synchronization error occurs.

Dead Time To prevent cross-conduction (shoot-through) in the power full bridge, dead time is introduced between turning off one MOSFET and turning on the complementary MOSFET. Dead time t is 3 cycles of the main oscillator (750 ns at 4MHz), but synchronizing to the main oscillator may extend by 1 cycle.

Enabling reset this input just turns off all power mosfets. When set to logic high, the output is disabled. When set to logic low, internal control enables the output as needed. Both the converter's inputs (STEP, DIR, MS1 and MS2) and the internal sequencing logic are active regardless of the enable input state. An effective low control input to minimize power consumption when not in use. This disables most of the internal circuitry, including the output mosfet and the internal regulator. When set to logic high, allows the device to function and start normally in its initial position. When coming out of sleep mode, wait 1 ms for the internal regulator to stabilize before issuing a STEP command. The output can also be reset to its home position without going into sleep mode. To do this, the pulse reset input is low and the pulse width is between twR (min) and twR (max).

Mixed Decay Operation

Hybrid decay is a technique that provides greater control over phase current as the current decreases. When the stepper motor is driven at high speed, the back EMF of the motor will lag the drive current. If a passive current decay mode (such as slow decay) is used in a current control scheme, the motor back EMF can cause the phase current to rise out of control. Mixed decay removes this effect by placing the full bridge initially in fast decay and then switching to slow decay after a period of time. Because fast decay is an active (driven) decay mode, this part of the current decay cycle will ensure that the current remains in control. Using fast decay for the full current decay time (off time) will result in a larger ripple current, but once the current is in control, switching to a slow decay will reduce the ripple current value. The off time the full bridge must maintain fast decay will depend on the characteristics and speed of the motor.

When the phase current rises, the back EMF of the motor will not affect the current control, and the slow decay method can be used to reduce the pulsation of the phase current. When the current rises, the A3986 automatically switches between slow decay and mixed decay when the current drops. The part of the off-time during which the full bridge remains fast decay is defined by the PFD1 and PFD2 inputs.

PFD1 and PFD2 use the percentage fast decay pins to select the fast decay section used when mixed decay is enabled according to Table 2. Mixed decay is enabled when the output current commanded by the step input signal is lower than the previous step. In mixed decay mode, when the trigger point is reached, the A3986 enters fast decay mode until the specified number of main oscillator cycles are completed. After this fast decay section, the A3986 switches to slow decay mode for the remainder of the fixed off time tOFF.

Choosing a fast decay of 0% with PFD1 and PFD2 will effectively keep the slow decay of the full bridge. This option can be used to keep the phase current ripple to a minimum when the motor is stationary or stepping at a very low rate.

Selecting 100% fast decay will provide the fastest current control when the current drops and help when the motor is being driven at very high step rates.

SR is used to set the input for synchronous rectification mode. When a PWM off cycle is triggered, the load current cycles according to the decay mode selected by the control logic. The synchronous rectification feature turns on the appropriate MOSFET during current decay and effectively shorts the body diode at the low RDS(on) of the MOSFET. This greatly reduces power dissipation and eliminates the need for additional Schottky diodes. Synchronous rectification can be set to active mode or disabled mode.

• Active mode: When the SR pin input is logic low, active mode is enabled and synchronous rectification will occur. This mode prevents load current reversal by turning off synchronous rectification when a zero current level is detected. This prevents reverse conduction of the motor windings.

• Disable mode: When the SR pin input is logic high, synchronous rectification is disabled. This mode is typically used when an external diode is required to transfer the power losses from the power mosfet to an external diode (usually a Schottky diode).

Shutdown Operation If VREG experiences an overtemperature fault or an undervoltage fault, the mosfet will be disabled until the fault condition is cleared. At power-up, if the VDD voltage is low, an under-voltage lockout (UVLO) circuit will disable the mosfet until the VDD voltage reaches a minimum level. Once VDD is above the minimum level, the converter will reset to the master state and the mosfet will be re-enabled.

application information

Current sensing

To minimize IPEAK current level sensing inaccuracy due to ground tracking IR drop, sense resistor RSENEX should be independently returned to the power ground star point. For low value sense resistors, the IR drop in the sense resistor PCB traces can be significant and should be considered. Sockets should be avoided because the contact resistance of sockets can cause variations in the sensor.

Thermal Protection

All drives will shut down when the joint temperature reaches a typical 165°C. This is just to prevent the A3986 from malfunctioning due to overtemperature connections. Thermal protection does not protect the A3986 from persistent short circuits. Thermal shutdown has a hysteresis of about 15°C.

circuit layout

Because this is a switch-mode application, care must be taken during the layout of the application PCB where there are rapid current changes. The following points are guidelines for the layout. Following all guidelines is not always possible. However, each point should be carefully considered as part of any layout process.

Ground connection layout recommendations:

1. Decoupling capacitors for power pins VBB, VREG, and VDD should be independently connected near the ground pins, not on any ground plane. Decoupling capacitors should also be placed as close as possible to the corresponding power supply pins.

2. The oscillator timing resistor ROSC should be connected to the GND pin. It should not be connected to any ground plane, common power, or power ground.

3. The ground pin should be connected to a single-point common power supply through a separate low-impedance trace.

4. Using a tightly grounded (tip and barrel) probe, reference the ground pin to check for transient peak voltage excursions on the LSS pin. If the voltage at LSS exceeds the absolute maximum specified in this datasheet, add additional clamps, capacitors, or both between the LSS pin and the AGND pin.

Other layout suggestions:

1. The gate charge drive path and gate discharge return path may carry transient current pulses. Therefore, traces from GHxx, GLxx, Sxx, and LSSx should be kept as short as possible to reduce the inductance of circuit traces.

2. Provide independent connections from each LSS pin to the common point of each power bridge. It is not recommended to connect LSS directly to the GND pin. LSS connections should not be used to detect connections.

3. Reduce stray inductance by using short, wide copper wires on the drain and source terminals of all power FETs. This includes the motor lead connections, the input power bus, and the common power supply for the low-side power FET. This will minimize the voltage generated by rapidly switching large load currents.

4. Consider using a small (100nF) ceramic decoupling capacitor between the source and drain of the power FET to limit fast transient voltage spikes caused by trace inductance.

The above are just suggestions. Every application is different and may experience different sensitivities. Each design should be tested at maximum current to ensure any parasitic effects are eliminated.

LD package, 38-pin TSSOP