The HA5024 is four versions of the popular Intersil HA5020 . It has a wide frequency band and high slew rate, and is optimized for video applications with gains between 1 and 10. It is a current feedback amplifier and therefore produces less bandwidth degradation at high closed loop gain voltage feedback amplifiers. Low differential gain and phase, 0.1dB gain flatness, and the ability to drive two 75 cables are ideal for demanding video applications. The HA5024 also features a disable function that significantly reduces supply current while forcing the output to a true high impedance state. This feature allows 2:1 as well as 4:1 video multiplexers to be implemented with a single integrated circuit. Current feedback designs allow the bandwidth of the user amplifier to depend on the feedback resistor. By lowering the RF, the bandwidth can be increased to compensate for reduced loop gain or heavy output loading at higher off positions.

feature

The four versions of the HA-5020 individually output enable/disable input offset voltage. 800 volts wide unity gain bandwidth. 125 MHz slew rate. 475 V/sec differential gain. 0.03% difference. 0.03 degree supply current (per amplifier). 7.5mA ESD protection. Guaranteed specification of 4000 volts at ±5V supplies lead-free plus annealed (RoHS compliant)

application

Video Multiplexers; Video Switching and Routing Video Gain Blocks Video Distribution Amplifiers/RGB Amplifiers Flash A/D Drivers Current-to-Voltage Converters Medical Imaging Radar and Imaging Systems

Absolute Maximum Ratings Thermal Information

Voltage between the V+ and V- terminals. 36 volts

DC input voltage (Note 3). ±V power supply

Differential input voltage. 10 volts

output current (Note 4). Short circuit protection

ESD rating (Note 3)

Human body model (per MIL-STD-883 method 3015.7). 2000 volts

operating conditions

temperature range. -40°C to 85°C

Supply voltage range (typical). ±4.5V to ±15V

Thermal Resistance (Typical, Note 2) θJA (°C/Watt) PDIP Package. 75 SOIC packs. 90

Maximum Junction Temperature (Note 1). 175 degrees Celsius

Maximum connection temperature (plastic packaging, Note 1). 150 degrees Celsius

Maximum storage temperature range. -65°C to 150°C

Maximum lead temperature (10s for soldering). 300 degrees Celsius (SOIC - lead only)

Lead-free PDIPs are available for through-hole wave solder processing only. They are not used in the reflow process

application.

CAUTION: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a pressure rating and operation

Installation under the above or any other conditions stated in the operating section of this specification is not implied.

notes:

1. The design of the maximum power dissipation (including the output load) must ensure that the connection temperature of the die is below 175°C and below 150°C

For plastic packaging. See the Application Information section for information on safe operating areas.

2. θJA is measured in free air with components mounted on the evaluation PC board.

3. The non-inverting input of an unused amplifier must be connected to GND.

4. The output protection is shorted to ground. However, shorting to ground will not degrade reliability and continuous (100% duty cycle) output current should not exceed 15mA for maximum reliability.

Electrical Specifications V Power=±5V, RF=1kAV=+1, RL=400CL10pF, unless otherwise specified

Electrical Specifications V Power=±5V, RF=1kAV=+1, RL=400CL10pF, unless otherwise specified (continued)

notes:

5. VCM=±2.5V. At -40°C, the product is tested at VCM=±2.25V, because self-heating is not allowed for short-time testing.

6. RL=100, VIN=2.5V. This is the minimum current that must be drawn from the disable pin in order to disable the output. The output is regarded as disabled when -10mVVOUT+10mV.

7. VIN=0V. This is the maximum current that can be drawn from the disable pin while the HA5024 remains enabled. The HA5024 is considered disabled when the supply current is reduced by at least 0.5mA.

8. VOUT switches from -2V to +2V, or from +2V to -2V. Specifications are 25% to 75%.

9.

10. RL=100, VOUT=1V. Rise/fall times are measured from the 10% to 90% point; propagation delay is measured from the 50% point in and out.

11. A. Production testing; B. Typical or guaranteed limits based on characteristics; C. Typical design for reference only.

12. VIN = +2V, Disabled = +5V to 0V. Measured from disabled to 50% point of output=0V.

13. VIN = +2V, Disabled = 0V to +5V. Measured from disabled to 50% point of output=2V.

14. VIN=0V, force output from 0V to ±2.5V, tR=tF=50ns, disabled=0V.

15. Measured with VM700A video tester of NTC-7 composite VITS.

16. VOUT=±2.5V. At -40°C, the product is tested at VOUT=±2.25V, since self-heating is not allowed for short test time.

Note:

17. A series input resistor of ≥100 is recommended to limit the input current in case the input signal appears before the HA5024 is powered up.

application information

For optimal feedback resistor inversion and non-inversion frequency response plots, see Figure 11 and Figure 12 in the Curves section of Typical Performance, illustrating the performance of the HA5024 for various closed-loop gain configurations. Although the bandwidth dependence on closed-loop gain is not as severe as for voltage feedback amplifiers, there can be a significant reduction in bandwidth at higher gains. This works by exploiting the unique relationship of the current feedback amplifier

bandwidth and radio frequency. Feedback resistors are required for all current feedback amplifiers, even for unity gain applications, and for RF, along with internal compensation capacitors, to set the dominant pole of the frequency response. So the bandwidth of the amplifier is inversely proportional to the radio frequency. This HA5024 design is optimized for a 1000 RF with a gain of +1. Reducing RF in unity gain applications reduces stability, resulting in excessive peaking and overshoot. At higher positions the gain amplifier is more stable, so the RF can be reduced in a bandwidth stability trade-off. The following table lists the various gains and expected bandwidths.

PC board layout

The frequency response of this amplifier depends to a large extent on the degree of care required in designing the PC board. Use low inductance components such as chip resistors and chip capacitors are strongly recommended. If there are lead components used, the wires must be kept short especially for power decoupling components and those components connected to the inverting input. Care must be taken to disconnect the power supply. A large value tantalum or electrolytic capacitor in parallel with a small value (0.1µF) chip capacitor works well in most cases. It is strongly recommended to use a ground plane to control noise. Care must also be taken to reduce the capacitance to ground (-IN) as seen by the amplifier's inverting input. The larger this capacitor is, the worse the gain peaking is at pulse overshoot and possible instability. It is recommended to connect the trace to -IN and keep the connection to -IN as short as possible to minimize the capacitance of the node to ground. Driving Capacitive Loads Capacitive loads reduce the phase margin of the amplifier resulting in frequency response peaking and possible oscillation. In most cases, oscillation can be achieved by placing an isolation resistor (R) in series with the output as shown in Figure 6.

The choice of isolation resistor is highly load dependent, but 27 has been determined to be a good starting value. Power consumption considerations Due to the inherently high supply current of the quad amplifier, care must be taken to ensure that the maximum junction temperature (TJ, see Absolute Maximum Ratings) is not exceeded. Figure 7 shows the maximum ambient temperature versus voltage for the package type available for the power supply (plastic dipping, SOIC). Static operation at ±5V DC Both package types can operate over the full industrial range from -40°C to 85°C. Recommended thermal calculations, which account for output power, are performed by the designer.

enable/disable function

When enabled, the amplifier operates as a normal current feedback amplifier with all data in the electrical specification sheet valid and applicable. when? Disabling the amplifier output assumes a true high impedance state and the supply current decreases significantly. The circuit shown in Figure 8 is the enable/disable function. A large value resistor in series to disable the pin makes it appear as a driver. When the driver pulls this pin, low current is pinned from the driver. This current, possibly and when the external circuit and process variable is at the appropriate potential to ensure that point "A" reaches the shutdown output. The driver must be compliant and capable of sinking all current. A dedicated TTL gate can be used when VCC is +5V. The maximum low level output voltage is 0.4V of the TTL gate, with enough compliance to ensure that the amplifier will always be disabled, even if D1 won't turn on, the TTL gate will draw enough current to keep point "A" at the proper voltage. Disable pins when VCC is greater than +5V should use an open collector to drive devices with a fault class greater than VCC. Referring to Figure 8, it can be seen that R6 will act as a pull-up resistor to +VCC if the disable pin is left open. In those cases all circuits do not need the enable/disable function. Some circuits can be disabled by leaving the disable pin floating. If using the driver to set the enable/disable level, ensure that the driver does not sink more than 20µA when the disable pin is high.

typical application

Four-Channel Video Multiplexer Referring to amplifier U1A in Figure 9, R1 terminates the cable with a characteristic impedance of 75 and the back of R4 terminates the cable in its characteristic impedance. This amplifier is set in a gain configuration of +2 to produce a total network gain of +1 when driving the double-terminated cable. If different networks, the value of R3 can be changed in hopes of gaining gains. R5 holds the disable pin to ground, thus inhibiting the amplifier until switch S1 is thrown to position 1. In position 1, the switch will pull the disable pin up to enable the amplifier to operate. Since the actual signal conversion takes place within the amplifier, its differential gain and phase parameters are 0.03% and 0.03 degrees respectively, determining the operation of the circuit. The other three circuits, U1B to U1D, operate in a similar fashion. When the positive supply rail is 5V, the disable pin can be controlled by a dedicated TTL gate as previously described. If a multiplexer IC or its equivalent is used to select a channel its logic must be interrupted prior to fabrication. The HA5024IP is typically used as a remote video multiplexer when these conditions are met, and the multiplexer can be expanded by adding more amplifier ICs. Low-Impedance Multiplexers Two common problems arise when you try to multiplex multiple high-speed signals into a low-impedance source as an A/D converter. The first problem is that the impedance of the amplifier oscillating with a low radiation source causes gain errors. The second problem is that the multiplexer provides no gain, introduces various distortions and limits the frequency response. Using an op amp enable/disable function, like the HA5024, eliminates the multiplexer problem, as an external mux chip is not needed, and the HA5024 can drive a low impedance (large capacitance) load if a series isolation resistor is used.

notes:

18.U1 is HA5024IP.

19. All resistors are 

20. S1 turns off before turning on.

21. Use a ground plane.

Referring to Figure 10, both inputs are at characteristic impedance; 75 is typical for video applications. Because the driver typically has a gain of 0.5 at the characteristic impedance input, amplifier U2 is configured with a gain of +2 to set the circuit equal to one. Resistors R2 and R3 determine the amplifier gain, if a different gain is required, R2 should be changed according to the equation G=(1+R3/R2). R3 sets the frequency response of the amplifier, so you should refer to the manufacturer's datasheet before changing its value. R5, C1D1 is an asymmetric charge-discharge time circuit which configures U1 to open before switching on to prevent both amplifiers from being activated simultaneously. If the design is scaled to more channels, the drive logic must be designed to be built first. R4 is included in the feedback so that the gain of the large open loop amplifier U2 will represent the load output impedance in a small closed loop while keeping the amplifier stable at the load capacitance value. The circuit shown in Figure 10 does not observe oscillating capacitance values; therefore, problem one has been solved. Frequency and Gain The characteristic of the circuit is now that the amplifier behaves independently of any multiplexing operation; thus, problem 2 has been solved. The multiplexer conversion time is about 15µs, and the component values are displayed.

Typical performance curve VSUPPLY=±5V, AV=+1, RF=1k; RL=400TA=25°C, unless otherwise specified