Features and Benefits

▪ Low RDS (on) output

▪ Automatic current decay mode detection/selection

▪ Mixed and slow current decay modes

▪ Low power synchronous rectification

▪ Internal UVLO and thermal shutdown circuitry

▪ Cross current protection

illustrate

The A3984 is a complete microstepping motor driver with built-in translation for easy operation. It is designed to operate bipolar stepper motors in full-, half-, fourth-, and sixteen-order modes with output drive capacities up to 35 V and ±2 A. The A3984 includes a fixed off-time current regulator capable of operating in slow decay mode or mixed decay mode.

Translation is the key to the ease of implementation of A3984. Just a single pulse at the step input can drive the motor one microstep. There are no phase sequence tables, high frequency control lines or complex programming interfaces. The A3984 interface is ideal for applications where complex microprocessors are unavailable or overburdened.

The chopper control in the A3984 automatically selects the current decay mode (slow or mixed). When a signal is present at the step input pin, the A3984 determines whether the step is producing higher or lower current in each motor phase. If you change to a higher current, the decay mode is set to slow decay. If you change to a lower current, the current decay is set to mixed (the setting is initially a fast decay of 31.25% of the fixed off time, then a slow decay for the remainder of the off time). This current decay control scheme can reduce the audible noise of the motor, improve step accuracy, and reduce power consumption.

Internal synchronous rectification control circuitry is provided to improve power consumption during PWM operation.

Absolute Maximum Ratings

Internal circuit protections include: hysteretic thermal shutdown, undervoltage lockout (UVLO), and cross-current protection. No special power-up sequence is required.

The A3984 is available in a low profile (1.2 mm max), 24-pin TSSOP and exposed thermal pad (LP package). Lead free, 100 % matte tin leadframe.

Functional block diagram

Function description

device operation. The A3984 is a complete microstepping motor driver with a built-in converter for simple operation and minimal control lines. It is designed to operate bipolar stepper motors in full-step, half-step, fourth-step and sixteen-step modes. The currents in the two output full bridges and all N-channel DMOS field effect transistors are regulated by a fixed off-time PMW (pulse width modulated) control circuit. In each step, the current of each full bridge is set by the values of its external current sense resistor (RS1 or RS2), the reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the converter).

At power-up or reset, the converter sets the DAC and phase current polarities to their initial initial state (as shown in Figures 2 to 5), and sets the current regulator to a mixed decay mode for both phases. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage and current polarity. (See Table 2 for the current level sequence.) The microstep resolution is set by the combined effect of the inputs MS1 and MS2, as shown in Table 1.

When stepping, if the new output level of the DAC is lower than its previous output level, the attenuation mode of the active full bridge is set to mixed. If the new output level of the DAC is higher or equal to its previous level, the decay mode of the active full bridge is set to slow. This automatic current decay selection improves microstepping performance by reducing current waveform distortion caused by motor back EMF.

Reset input (reset). The reset input sets the converter to a predefined initial state (shown in Figure 2 to Figure 5) and turns off all DMOS outputs. All step inputs will be ignored until the reset input is set high.

Step input (step). A low-to-high transition on the step input puts the translator in sequence and advances the motor one increment. The converter controls the input of the DAC and the current flow in each winding. The size of the increment is determined by the combined state of the inputs MS1 and MS2.

Microstep selection (MS1 and MS2). Select the microstep format as shown in Table 1. MS2 has a 50 kΩ pull-down resistor. Any changes made to these inputs will not take effect until the next rising edge.

Direction Input (DIR). This determines the direction of rotation of the motor. When low, the direction is clockwise, when high, the direction is counterclockwise. Changes to this input will not take effect until the next rising edge.

Internal PWM current control. Each full bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to the desired value ITRIP. Initially, a pair of diagonal source and sink DMO outputs are enabled and current flows through the motor windings and current sense resistor RS. When the voltage across R equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the source DMOS fet (in slow decay mode) or the sink and source DMOS fet (in mixed decay mode).

The maximum value of the current limit is set by selecting the voltage on the RS and VREF pins. The transconductance function is approximated by the current-limited maximum value itrimax(A), which is given by:

where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V).

The DAC output reduces the VREF output to the current sense comparator in precise steps such that:

(See Table 2 for %itrimpax for each step.)

It is critical that the maximum rating (0.5 V) of the SENSE1 and SENSE2 pins is not exceeded.

fixed rest periods. The internal PWM current control circuit uses a one-shot circuit to control the duration that the DMOS FET remains off. The one-shot off time tOFF is determined by the choice of an external resistor connected from the ROSC timing pin to ground. If ROSCpin is tied to an external voltage >3v, tOFF defaults to 30µs.

For this purpose, the ROSC pin can be safely connected to the VDD pin purpose. The value of tOFF (μs) is approximately:

blank. This function is used to clear the output of the current sense comparator control circuit when the internal current switches the output. The comparator output is hidden to prevent false overcurrent detection due to reverse recovery current, clamp diodes and capacitance-related switching transients. The blank time tBLANK (μs) is approximately:

Charge Pumps (CP1 and CP2). A charge pump is used to generate a gate supply greater than VBB to drive the source DMOS gate. A 0.1µF ceramic capacitor should be connected between CP1 and CP2. In addition, a 0.1µF ceramic capacitor is required to store energy between VCP and VBB for operating the high-side DMOS gate.

VREG (VREG). The internally generated voltage is used to operate the sink side DMOS output. The VREG pin must be grounded separately from the 0.22µF capacitor. VREG is monitored internally. In fault conditions, the DMOS output A3984 is disabled.

Enable input (enable). This input turns all DMOS outputs on or off. When set to logic high, the output is disabled. When set to logic low, internal control makes the output mandatory. The converter also inputs STEP, DIR, MS1 and MS2 as internal sequencing logic, all of which remain active independently of the enable input state.

closure. In the event of a fault, over temperature (too high TJ) or under voltage (on VCP), the DMOS output of the A3984 is disabled until the fault condition is cleared. A UVLO (under-voltage lockout) circuit disables the DMOS output and resets the translator to its original state at power-up.

Sleep mode (sleep). When the motor is not in use, this input disables most of the internal circuitry including the output DMOS FET, current regulator, and charge pump. The sleep pin is logic low, causing the A3984 to enter sleep mode. A logic high allows normal operation, as well as startup (at which point the A3984 drives the motor home to the microstep position). When emerging from sleep mode, in order to stabilize the charge pump, a Step command is issued.

Mixed decay operations. The bridge can have a mix of decay modes, depending on the sequence of steps, as shown in Figures 3 to 5. When the trigger point is reached, the A3984 initially enters a fast decay mode with 31.25% off time. tove. After that switch to slow decay mode for the remaining flight time.

Synchronous rectification. When a PWM off period is triggered by the internal fixed-off time period, the load current receiver calculates according to the decay mode selected by the control logic. This synchronous rectification function turns on the FET during current decay, effectively shorting the body of the diode with low DMOS RDSON. This significantly reduces power differentials and can eliminate the need for external Schottky diodes in many applications. Turn off synchronous rectification when zero current level is detected.

Low Voltage Package, 24-Pin TSSOP with Exposed Thermal Pad

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