Features

• High resolution: –130dB SNR (250SPS, high resolution mode); –127dB SNR (250SPS, low power mode)

• High Accuracy: THD: –120dB; Inlet: 0.8ppm

• Low noise PGA

• Dual channel input multiplexer

• Inherently stable modulator with fast response over travel detection

• Flexible digital filters: Sinc+FIR+IIR (optional); linear or minimum phase response; programmable high-pass filter; selectable FIR data rates: 250SPS to 4kSPS

• Filter bypass option

• Low power consumption: high resolution mode: 27mW; low power mode: 16mW; shutdown: 10 microwatts

• Offset and gain calibration engine

• Sync input

• Analog Power Supply: Unipolar (+5V) or Bipolar (±2.5V)

• Digital Power: 1.8V to 3.3V

application

Energy exploration; seismic monitoring; high-precision instruments.

illustrate

The ADS1282 is a high performance monolithic analog-to-digital converter (ADC) with an integrated low noise programmable gain amplifier (PGA) and a dual input multiplexer (MUX). The ADS1282 is suitable for the requirements of energy exploration and seismic monitoring environments.

The converter uses a fourth-order inherently stable delta-sigma (ΔΣ) modulator with excellent noise and linearity performance. The modulator can be used with on-chip digital filters or with post-processing filters.

A flexible input multiplexer provides additional external measurement inputs, as well as internal self-test connections. The PGA has very low noise (4nV/)√Hz and high input impedance, allowing easy connection to geophones and hydrophones.

Digital filters provide selectable data rates from 250 to 4000 samples per second (SPS). A high-pass filter (HPF) has an adjustable corner frequency. On-chip gain and offset scaling registers support system calibration.

A synchronization input (SYNC) can be used to synchronize the conversions of multiple ADS1282s. The SYNC input also accepts a clock input for sequential alignment of conversions from external sources.

Two operating modes optimize noise and power. Meanwhile, the amplifier, modulator and filter lose 27mW in low power mode and only 16mW. Housed in a compact TSSOP-28 package, the ADS1282 is fully specified over the -40°C to +85°C temperature range with a maximum operating temperature range of +125°C.

Overview

The ADS1282 is a high-performance analog-to-digital converter (ADC) used in energy exploration, seismic monitoring, geological imaging, and other precision applications. The converters provide 24-bit or 32-bit output data at data rates from 4000SPS to 250SPS.

Figure 1 shows the block diagram of the ADS1282. The device features unipolar and bipolar analog power supplies for input range flexibility (AVDD and AVSS, respectively) and accepts digital supplies from 1.8V to 3.3V. The analog supply can be set to +5V to accept unipolar signals (with input offset), or below ±2.5V to accept true bipolar input signals (ground referenced).

An internal low dropout (LDO) regulator is used to provide the digital core from the DVDD. The BYPAS pin is the LDO output and requires a 0.1µF capacitor to reduce noise (BYPAS should not be used to drive external circuits).

The two-channel input MUX allows five configurations: Input 1; Input 2; Input 1 and Input 2 shorted together; shorted with 400Ω test; and common mode test. The input MUX is followed by a continuous time PGA with very low 4nV/noise. The √Hz PGA is controlled by register settings, allowing gains of 1 to 64.

The gain and offset registers scale the digital filter output to produce the final code value. The zoom function can be used for calibration and sensor gain matching. Output data words are provided as 24-bit words or full 32-bit words, allowing full utilization of the inherent high resolution.

The sync input resets the operation of the digital filters and modulators, allowing simultaneous conversion of multiple ADS1282 devices to external events. The sync input supports a continuously toggled input mode that accepts an external data frame clock locked to the slew rate.

The reset input resets the register settings and restarts the conversion process. The PWDN input sets the device to a micropower state. Note that register settings are not preserved in PWDN mode. If you need to preserve register settings (slightly higher quiescent current in standby mode), use the STANDBY command.

Noise-immune Schmitt triggers and clock-qualified inputs (reset and sync) provide increased reliability in high-noise environments. In addition to reading and writing configuration registers, the serial interface is also used to read conversion data.

Noise performance

The ADS1282 has excellent noise performance (SNR). The signal-to-noise ratio depends on the data rate and PGA settings. As the data rate decreases, the bandwidth decreases and the signal-to-noise ratio increases accordingly. Table 1 summarizes the typical noise performance with the input shorted.

idle tone

The ADS1281 modulator contains an internal dither signal that randomizes idle tone energy. Low level idle tones may still be present, typically 137dB below full scale. Low-level idle tones can be shifted out of the passband by applying an external 20mV offset.

Operating mode

For applications where minimum power consumption is important, a low power mode can be selected (register bit mode = 0). In low power mode, the power is reduced from 27mW to 17mW, and the signal-to-noise ratio is reduced by 3dB.

Analog Inputs and Multiplexers

A schematic diagram of the input multiplexer is shown in Figure 2. The specified input operating range of the input is shown in Equation 1:

ESD diodes protect the multiplexer inputs. If the input voltage is below AVSS–0.3V or above AVSS+0.3V, the ESD protection diode may turn on. If these conditions are possible, external Schottky clamp diodes and/or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table).

Additionally, overdriving either multiplexer input may affect the transition of the other channel. If overdriven output is possible, it is recommended to clamp the signal with an external Schottky diode.

The multiplexer connects the two external differential inputs to the preamp inputs. This multiplexer has various self-test modes. Table 3 summarizes the configuration of the multiplexer Figure 2.

A typical on-resistance switch for a multiplexer is 30Ω. When using a multiplexer with two inputs shorted, the on-resistance and the variation of resistance with input level can cause measurement errors and additional nonlinearity, as shown in Figure 3.

Programmable Gain Amplifier

The PGA is a low noise, continuous time differential input/differential output CMOS amplifier. The gain is programmable from 1 to 64 by register bits, PGA[2:0]. The PGA differentially drives the modulator through a 300Ω isolation resistor. 10nF gear capacitors must be connected to CAPP and CAPN to filter out high frequency noise from aliasing.

Referring to Figure 4, amplifiers A1 and A2 are chopped to remove 1/f input noise. The cut frequency is fCLK/512 (nominal 8kHz). As shown in Figure 5, the chopping is in the passband. However, chopping reduces the impedance of the input PGA (see Characteristics). Chop the register bits to '0' by setting. Table 2 shows the register bit settings that control the gain and corresponding input range.

analog to digital converter

The ADC module of the ADS1282 consists of two modules: a high-precision modulator and a programmable digital filter.

Modulator

As shown in Figure 6, the high-performance modulator is an inherently stable fourth-order Σ2+2 pipeline structure. It moves the quantization noise to a higher frequency (beyond the passband), which can be easily removed by digital filtering, and the modulator can be filtered by an on-chip digital filter or a post-processing filter.

The first stage of the modulator converts the analog input voltage into a pulse code modulation (PCM) stream. The “1” density of the PCM data stream is highest when the level of the differential analog input (AINP–AINN) is close to half the reference voltage 1/2 × (VREFP–VREFN). As the differential analog input level approaches zero, the PCM has nearly equal densities of '0's and '1's. At the two extremes of analog input levels (+FS and –FS), the "1" density of the PCM stream is approximately +90% and +10%, respectively.

The second stage of the modulator produces a "1" density data stream designed to cancel the quantization noise of the first stage. The data streams of the two stages are then combined before being input to the digital filter stage, as shown in Equation 2.

M0[n] represents the latest first stage output, and M0[n–1] represents the previous stage output. When the modulator output is enabled, the digital filter is turned off to save power.

The modulator is optimized for input signals within the 4kHz passband. As shown in Figure 7, the noise shaping of the modulator results in a sharp increase in noise above 6kHz. The modulator has a chopped input structure to further reduce noise in the passband. Noise is shifted out of the passband and appears at the chopping frequency (fCLK/512=8kHz). The component at 6.5kHz is the tone frequency, shifted out of band by the 20mV external input. The frequency of the tone is about VIN/3 (in kHz).

Modulator overtravel

The ADS1282 modulator is inherently stable and therefore has predictable recovery behavior caused by input overdrive conditions. Modulators do not exhibit self-resetting behavior, which often results in erratic output data flow.

The ADS1282 modulator outputs a 1s density data stream with a 90% duty cycle when a positive full-scale input signal is applied (a negative full-scale signal is 10% duty cycle). If the input is over 90% modulated, but less than 100% modulated (10% and 0% for negative overdrive), the modulator remains stable and continues to output a 1s density data stream. The digital filter can clip the output code to +FS or –FS, or not, depending on the duration of the overdrive. When the input overspeeds (worst case) from returning to the normal range for a long time, the modulator returns to the normal range immediately, but the delayed transition of the group delay digital filter returns the result within the linear range (31 linear readings phase FIR). 31 additional readings (62 total) are required for fully settled data.

If the input sufficiently overdrives the modulator to full duty cycle (that is, all 1s, all 0s, or ±110% FSR), the modulator goes into stable saturation. Digital output codes may clip to +FS or –FS, again depending on duration. Overdrives of small duration may not always clip output codes. When the input returns to the normal range, the modulator takes up to 12 modulator clock cycles (fMOD) to come out of saturation and return to the linear region. The digital filter requires an additional 62 transformations of the fully fixed data (linear phase fir).

In the extreme case of overrange, either input will exceed the analog supply voltage plus the internal ESD diode drop. The internal ESD diode starts to conduct and the signal at the input is cut off. The modulator will maintain linear operation if the differential input signal range is not exceeded. If the differential input signal range is exceeded, the modulator is saturated but stable, outputting all 1s or 0s. When the input overdrive is removed, the diode recovers quickly and the ADS1282 returns to normal. Note that the linear input range is ±100mV beyond the analog supply voltage; at input levels above this, be careful to limit the input current to 100mA peak transient and 10mA continuous.

Modulator Input Impedance

The modulator uses an internal capacitor to sample the buffered input voltage to perform the conversion. The charging of the input sampling capacitor draws the transient current from the PGA output. The average value of the current can be used to calculate the effective input impedance REFF=1/(fMOD×CS).

in:

The resulting modulator input impedance is 55kΩ when CLK=4.096MHz. Note that the modulator input impedance and the PGA output antialiasing resistance result in a system gain error of -1%. CS can vary by ±20% or more across production batches, affecting gain error.

Modulator overtravel detection (magnetic flux leakage)

The ADS1282 has a fast response overrange detection that indicates when the differential input exceeds approximately 100% overrange. Threshold tolerance is ±2.5%. When in an overrange condition, the MFLAG output is asserted high. As shown in Figures 8 and 9, the absolute value of the input is compared to 100% of the range. The output of the comparator is sampled at a rate of fMOD/2, producing the MFLAG output. The minimum MFLAG pulse width is fMOD/2.

Modulator output mode

The modulator digital stream output is directly available, bypassing and disabling the internal digital filter. The modulator output mode is activated in Pin mode by setting MOD/DIN=1, and activated in register mode by setting CONFIG0 register bits filter[1:0]=00. Then, pins DR0/M0 and DR1/M1 become the modulator data outputs, and PHS/MCLK become the modulator clock outputs. When not in modulator mode, these pins are inputs and must not float.

The modulator output consists of three signals: one output for the modulator clock (PHS/MCLK) and two outputs for the modulator data (DR0/M0 and DR1/M1). The modulator clock output rate is fMOD (fCLK/4). The sync input resets the MODCLK stage, as shown in Figure 10. The sync input is latched on the rising edge of CLK. MODCLK resets and the next rising edge of MODCLK occurs after five CLK periods.

The modulator output data is two bits wide and must be merged together before being filtered. Combine the data outputs using the time domain equation of Equation 2.

digital filter

A digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, a trade-off can be made between resolution and data rate: for higher resolutions, filter more; for higher data rates, filter less.

The digital filter consists of three cascaded filter stages: variable decimation, fifth-order sinc filter; fixed decimation FIR, low-pass filter (LPF) with selectable phase; and programmable, first-order, high-pass filter (HPF), as shown in Figure 11.

The output can be obtained from one of the three filter blocks, as shown in Figure 11. To achieve a completely off-chip digital filter, select the filter bypass setting (modulator output). For partial filtering of the ADS1282, select the sinc filter output. For full on-chip filtering, activate the sinc and FIR stages. Then, HPF can be included to remove DC and low frequencies from the data. Table 4 shows the filter options in register mode. Table 5 shows the filter options in Pin mode.

Sinc filter stage (sinx/x)

The sinc filter is a fifth-order low-pass filter with variable decimation rate. Data is provided from the modulator to this part of the filter at a rate of fMOD (fCLK/4). The sinc filter attenuates the high frequency noise of the modulator and then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter; it is set by DR[1:0] and the mode selection, as shown in Table 6.

Equation 3 shows the scaled Z-domain transfer function of the sinc filter.

Equation 4 shows the function of the frequency domain transmission sinc filter.

where: N = decimation rate (see Table 6)

A sinc filter has notches (or zeros) and their multiples that appear at the output data rate. At these frequencies, the gain of the filter is zero. Figure 12 shows the sinc filter and Figure 13 shows the roll of the sinc filter.

fir period

The second stage of the ADS1282 digital filter is an FIR low-pass filter. Data is fed to this stage from the sinc filter. The FIR stage is divided into four sub-stages, as shown in Figure 14. The first two sub-stages are half-band filters with a decimation ratio of 2. The third sub-phase is decided by 4, and the fourth sub-phase is decided by 2. The overall decimation of the FIR stage is 32. Note that the third and fourth parts use two sets of coefficients depending on the phase selection. Table 23 (in the appendix section at the end of this document) lists the FIR level coefficients. Table 7 lists the data rate and overall decimation rate of the FIR stage.

As shown in Figure 15, the FIR frequency response provides a flat passband (±0.003dB passband ripple) for a data rate of 0.375. Figure 16 shows the transition from pass to stop.

Although not shown in Figure 16, the passband response is repeated at multiples of the modulator frequency (NfMOD-f0 and NfMOD+f0, where N=1, 2, etc., f0=passband). These image frequencies, if present in the signal without external filtering, fold back (or alias) into the passband and cause errors. It is recommended to use the ADS1282 input to limit possible out-of-band input signals. Usually, a single RC filter is sufficient.

Group Delay and Step Response

The FIR block is implemented as a multi-level FIR structure with optional linear or minimum phase response. The passband, transition, and stopband responses of the filters are nearly identical, but differ in their respective phase responses.

Linear phase response

Linear phase filters have constant delay time and input frequency (i.e. constant group delay). The linear phase filter has a characteristic that the time delay from an arbitrary time of the input signal to the same time of the output data is constant regardless of the signal properties. This filtering behavior results in essentially zero phase error when analyzing multi-tone signals. However, the group delay and settling time of the linear phase filter are slightly larger than the minimum phase filter, as shown in Figure 17.

Minimum phase response

The minimum phase filter provides the input signal to the output, but the relationship (phase) is not constant with frequency, as shown in Figure 18. The filter phase is selected by the PHS bit (register mode) or the PHS/MCLK pin (pin mode); Table 8 shows additional information.

HPF grade

The last stage of the ADS1282 filter block is a first-order HPF implemented as an IIR structure. This filter stage blocks the DC signal and rolls out low frequency components below the cutoff frequency. The transfer function of the filter is shown in Equation 5:

In the formula, b is calculated according to formula 6:

The high pass corner frequency is programmed by the hexadecimal registers HPF[1:0]. Equation 7 is used to set the high pass corner frequency. Table 9 lists example values for high-pass filters.

Where: HPF = high pass filter register value (converted to hexadecimal); ωN = 2πfHP/fDATA (normalized frequency, radians); fHP = high pass corner frequency (Hz); fDATA = data rate (Hz).

HPF introduces a small gain error, in this case the magnitude depends on the ratio fHP/fDATA. For many common values (fHP/fDATA), the gain error is negligible. Figure 19 shows the gain error of the HPF. The gain error factor is shown in Equation 13 (see appendix at the end of this document).

Figure 20 shows the first-order amplitude and phase responses of the HPF. Note that the settling time of the filter should be considered in the case of applying a step input or synchronization.

Voltage Reference Inputs (VREFP, VREFN)

The reference voltage for the ADS1282 ADC is the differential voltage between VREFP and VREFN: VREF=VREFP–VREFN. The reference input has a structure similar to that of the analog input, and the circuit on the reference input is shown in Figure 21. The average load on the switched capacitor reference input can be modeled by the effective differential impedance REFF=tSAMPLE/CIN (sample=1/fMOD). Note that the effective impedance of the reference input loads an external reference with a non-zero source impedance.

The ADS1282 reference input is protected by an ESD diode. To prevent these diodes from energizing, the voltage at either input must remain within the range shown in Equation 8:

A high-quality voltage reference is necessary to obtain the best performance from the ADS1282. Noise and drift on the reference voltage can degrade the overall performance of the system, so special attention must be paid to the circuits that generate the reference voltage to obtain full performance. For most applications, a 1µF ceramic capacitor applied directly to the reference input pin is recommended.

Main clock input (CLK)

The ADS1282 requires a clock input to operate. The clock is applied to the CLK pin. The data conversion rate is proportional to the CLK frequency. Power consumption is relatively constant with CLK frequency (see Typical Characteristics).

As with any high-speed data converter, a high-quality, low-jitter clock is critical for optimal performance. A crystal clock oscillator is the recommended clock source. Make sure to avoid excessive ringing on the clock input; keep the clock trace as short as possible and use a 50 ohm series resistor close to the power supply.

Synchronization (SYNC PIN and SYNC Command)

The ADS1282 can be synchronized with external events or with other ADS1282 devices (if the synchronization event applies to all devices at the same time).

The ADS1282 has two synchronization sources: the sync input pin and the sync command. The ADS1282 also has two synchronization modes: pulse synchronization and continuous synchronization. In pulse synchronization mode, the ADS1282 synchronizes to a single synchronization event. In continuous sync mode, either the device synchronizes to a single sync event, or a continuous clock is applied to pins with a period equal to an integer multiple of the data rate. When the periods of the sync input and DRDY output do not match, the ADS1282 resyncs and restarts the conversion. Note that in Pin control mode, the reset input is used as synchronous control.

Pulse sync mode

In pulse sync mode, when a sync event occurs (either by pin or command), the ADS1282 stops and restarts the conversion process. When a sync event occurs, the device resets the internal memory; DRDY goes high and new conversion data is available after the digital filter is set, as shown in Figure 22 and Table 10.

Continuous sync mode

In continuous sync mode, a single sync pulse or a continuous clock can be applied. When a single sync pulse (rising edge) is applied, the device behaves similarly to pulse sync mode. In this mode, however, DRDY continues to toggle unaffected, but the DOUT output remains low until data is ready. When the conversion data is non-zero, the new conversion data is ready (as shown in Figure 22).

When a continuous clock is applied to a sync pin, the period must be an integer multiple of the output data rate, otherwise the device will resynchronize. When the sync input is first applied to the first rising edge of CLK, the device will resync (sync under the following conditions ≠ N/fDATA). DRDY continues to output, but DOUT remains low until new data is ready. Then, if the period of the applied sync clock matches an integer multiple of the output data rate, the device is free to run without resynchronizing. The phase of the application clock and the output data rate (DRDY) do not have to match. Figure 23 shows the continuous sync mode.

Reset (reset pin and reset command)

The AD S1282 can be reset in two ways: by turning the reset pin low or by sending a reset command. When using the reset pin, pull it low for at least 2/fCLK to force a reset. The ADS1282 remains in reset until the pins are released. By command, the reset takes effect on the next rising edge of fCLK after the eighth rising edge of SCLK of the command. Note: The SPI interface may require a reset for the reset command to work properly; see section.

In reset, the registers are set to their default values and the conversion is synchronized on the next rising edge of CLK. New conversion data is available, as shown in Figure 24 and Table 11.

Power down (PWDN pin and alternate command)

There are two ways to shut down the ADS1282: set the PWDN pin low or send an alternate command. When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the register settings are reset.

When powered down, note that device outputs remain active and device inputs cannot float. The SPI port and configuration registers remain active when the standby command is sent. Figure 25 and Table 12 show the times.

power-on sequence

The ADS1282 has three power supplies: AVDD, AVSS, and DVD. Figure 26 shows the power-up sequence for the ADS1282. The power supplies can be arranged in any order. The power supply [the difference between AVDD – AVSS and DVDD] generates an internal reset, and the sum of its outputs generates a global internal reset. After the supply exceeds the minimum threshold, 216 fCLK cycles are counted before the internal reset is released. After the internal reset is released, new conversion data is available, as shown in Figure 26 and Table 12.

DVD Power

DVD disc power supplies operate in the range of +1.65V to +3.6V. If the operating voltage of the DVD disc is lower than 2.25V, please connect the DVD disc pin to the BYPAS pin. If DVD is greater than or equal to 2.25V, do not connect DVD to BYPAS pin (open circuit). Figure 27 shows this connection.

serial interface

The serial interface is used to read conversion data and access configuration registers. The interface consists of three basic signals: SCLK, DIN, and DOUT. The additional output DRDY is converted to low in Read Data Continuous mode when the data is ready to be retrieved. Figure 28 shows the connections when using multiple converters.

Serial Clock (SCLK)

The serial clock (SCLK) is used to clock the data input (DIN) and output (DOUT) of the ADS1282. This input is a Schmitt trigger input with high noise immunity. However, it is recommended to keep the SCLK as clean as possible to prevent possible glitches from unintentionally shifting data.

Data is shifted to DIN on the rising edge of SCLK and to DOUT on the falling edge of SCLK. If SCLK remains low for 64 DRDY cycles, the data transfer or command in progress is terminated and the SPI interface is reset. The next SCLK pulse starts a new communication cycle. This timeout feature can be used to recover the interface in the event of a transmission interruption or unexpected failure of SCLK. SCLK should be held low when not active.

Data Input (DIN)

The data input pin (DIN) is used to input register data and commands to the ADS1282. Hold data low when reading conversion data in continuous read data mode (except when a stop read data continuous command is issued). Data is transferred into the converter on the rising edge of SCLK. In Pin mode, DIN is not used.

Data output (DOUT)

The data output pin (DOUT) is used to output data from the ADS1282. Data is shifted on DOUT on the falling edge of SCLK. In pin mode, only conversion data is read from this pin.

Data Ready (DRDY)

DRDY is an output; when it transitions low, this transition indicates that new transition data is ready, as shown in Figure 29. When reading data in continuous mode, the data must be read within four CLK cycles before DRDY goes low again or the data is overwritten with new conversion data. When reading data via command mode, the read operation can overlap the occurrence of the next DRDY without corrupting the data.

DRDY is reset high on the first falling edge of SCLK. Figure 29 and Figure 30 show the functionality of DRDY with and without data readback, respectively.

If no data is retrieved (SCLK is not provided), the DRDY pulses up to four fCLK cycles during the 8000001h update, as shown in Figure 30.

Data Format

The ADS1282 provides conversion data in 32-bit binary two's complement format, as shown in Table 13. The LSB of the data is a redundant sign bit: "0" for positive numbers and "1" for negative numbers. However, when the output is clipped to +FS, LSB=1; when the output is clipped to -FS, LSB=0. Data readback can be stopped at 24 bits if desired.

read data

The ADS1282 has two methods for reading converted data: continuous read data and command read data.

Read data continuously

In read data continuous mode, conversion data is shifted directly from the device without sending a read command. This mode is the default mode at startup. This mode is also enabled by the RDATAC command. When DRDY goes low, indicating that new data is available, the MSB of the data appears on DOUT, as shown in Figure 31. Data is usually read on the rising edge of SCLK, and DRDY returns high on the first falling edge of SCLK. After the 32-bit data is shifted out, further SCLK transitions cause DOUT to go low. Read operations can be stopped at 24 bits if desired. The data shift operation must be completed within four CLK cycles before DRDY falls again, otherwise the data may be corrupted.

Read data continuous mode is the default data mode of Pin mode. When the Stop Read Data Continuous command is issued, the DRDY output is blocked, but the ADS1282 continues to convert. In stop continuous mode, data can only be read by command.

read data by command

Read data continuous mode is commanded by SDATAC. In this mode, conversion data is read by command. In read data command mode, a read data command must be sent to the device for each data conversion (see Figure 32). When a read data command is received (on the eighth SCLK rising edge), the data is available for read only when DRDY goes low (tDR). When DRDY goes low, conversion data appears on DOUT. Data can be read on the rising edge of SCLK.

one-time operation

The performance of the ADS1282 is very energy efficient, with one-time conversions using alternate commands under software control. Figure 33 shows this sequence. First, issue the standby command to set the standby mode.

When ready to take a measurement, issue a wake-up command. Monitor DRDY; when it goes low, the fully set conversion data is ready to be read directly in read data continuous mode. Then, issue another alternate command. When ready for the next measurement, repeat the cycle from another wake-up command.

Offset and Full-Scale Calibration Registers

The transformed data can be scaled by offset and gain before producing the final output code. As shown in Figure 34, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the full scale register (FSC). Equation 9 shows the scale:

The offset and full-scale register values are set by direct writes, or automatically by a calibration command.

OFC[2:0] register

The offset calibration is a 24-bit word consisting of three 8-bit registers, as shown in Table 18. Offset registers are left-justified to align with 32 bits of conversion data. The offset is in two's complement format, with a maximum positive value of 7FFFFFh and a maximum negative value of 800000 hours. This value is subtracted from the converted data. A register value of 00000h has no offset correction (default). Note that while the offset calibration register value can correct the offset from –FS to +FS (as shown in Table 16), to avoid overloading the input, the analog input cannot exceed the full-scale range.

FSC[2:0] register

Full-scale calibration is a 24-bit word consisting of three 8-bit registers, as shown in Table 19. The full-scale calibration value is 24-bit, straight-offset binary, normalized to 1.0 at code 400000h. Table 17 summarizes the scaling of the full-scale registers. The register value of 400000h (default) has no gain correction (gain=1). Note that while the gain calibration register value corrects for gain errors greater than 1 (gain correction < 1), it cannot exceed the full-scale range of the analog input to avoid overloading the input.

Calibration command

A calibration command can be sent to the ADS1282 to calibrate the conversion data. The offset and gain calibration register values are written internally to perform calibration. Appropriate input signals must be applied to the ADS1282 inputs before sending a command. Use slower data rates for more consistent calibration results; this effect is a by-product of the lower noise provided by these data rates. Also, if calibrating at power-up, make sure the reference voltage is fully stable.

Figure 35 shows the calibration command sequence. After the analog input voltage (and reference voltage) has stabilized, send a stop data continuous command followed by a sync and read data continuous command. After 64 data cycles, DRDY goes low. When DRDY goes low, send a stop data continuation, followed by a calibration command, followed by a read data continuation command. After 16 data cycles, calibration complete and conversion data may be read at this time. The sync input must be held high during calibration.

OFSCAL command

The OFSCAL command performs offset calibration. Before sending the offset calibration command, a zero input signal must be applied to the ADS1282 and the input allowed to settle. When sending the command, the ADS1282 takes an average of 16 readings and then writes this value to the OFC register. The contents of the OFC register can then be read or written. During offset calibration, full-scale correction is bypassed.

Gankar order

The GANCAL command performs gain calibration. Before sending the GANCAL command, a dc input signal within positive or negative full scale, but not exceeding positive or negative full scale, must be applied. Once the signal is stable, commands can be sent. The ADS1282 averages 16 readings and then calculates a value to compensate for gain error. Gain then writes the correction value to the FSC register. The contents of the GANCAL register can then be read or written. Note that when the gain calibration command corrects a gain error greater than 1 (gain correction < 1), the analog input cannot exceed the full scale range to avoid input overload. This should be calibrated for gain calibration after offset.

User calibration

System calibration of the ADS1282 can be performed without using the calibration command. This procedure requires that the calibration value be calculated externally and then written to the calibration register. The steps of this process are:

1. Set OFSCAL[2:0] register=0hGANCAL[2:0]=400000h. These values set the offset and gain registers to 0 and 1, respectively.

2. Apply zero-difference input to the input of the system. Wait for the system to stabilize, then average n output readings. More average readings result in more consistent calibration. Write the average value to the OFC register.

3. Apply differential positive or negative DC signal, or AC signal, smaller than the system. Wait for the system to stabilize, then average n output readings.

The value written to the FSC register is calculated by Equation 10 and Equation 11.

The DC signal calibration is as shown in Equation 10 and Equation 11. Expected output codes are based on 31-bit output data.

For AC signal calibration, use the rms value of the collected data (as shown in Equation 12).

Order

The commands listed in Table 20 control the operation of the ADS1282. Command operations can only be performed in register mode. Most commands are self-contained (i.e. 1 byte long); register reads and writes require a second command byte in addition to the actual data byte.

A delay of 24 fCLK cycles is required between commands and between bytes within a command, from the last SCLK rising edge of one command to the first SCLK rising edge of the next command. This delay is shown in Figure 36.

In read data continuous mode, the ADS1282 places conversion data on the output pins when SCLK is applied. Since potential conflicts between converted data on DOUT and data on DOUT are caused by registers or reading data through command operations, it is necessary to send consecutive instructions or data read by an instruction before stopping reading the data register. The STOP Read Data Continuous command disables the direct output of converted data on the DOUT pin.

Wake up: wake up from standby mode

Description: This command is used to exit standby mode. After the command is sent, the time when the first data is ready is shown in Figure 25 and Table 13. Sending this command during normal operation has no effect; for example, reading data via the read data continuation method while holding data low.

Standby: Standby mode

Description: This command puts the ADS1282 into standby mode. During standby, the device enters a low-power state where low quiescent current keeps register settings and the SPI interface active. To shut down the device completely, set the PWDN pin low (register settings are not saved). To exit standby mode, issue a wake-up command. Operation in standby mode is shown in Figure 37.

Synchronization: Synchronized A/D conversion

Description: This command is used to synchronize A/D conversion. After the command is received, the read in progress is canceled and the conversion process starts over. To synchronize multiple ADS1282s, this command must be sent to all devices simultaneously. Note that the sync pin for this command must be high.

reset: reset the device

Description: The reset command resets the registers to their default values, enables read data continuous mode, and restarts the conversion process; the reset command functions the same as the reset pin. The reset command timing is shown in Figure 24.

RDATAC: Read data continuously

Description: This command enables read data continuous mode (default mode). In this mode, conversion data can be read directly from the device without providing a data read command. Whenever DRDY falls, new data is available for reading. For more details.

SDATAC: Stop reading data continuously

Description: This command stops reading data in continuous mode. The read data continuous mode needs to be exited before sending register and data read commands. This command disables the DRDY output, but the ADS1282 continues to convert.

RDATA: read data by command

Description: This command reads conversion data. See the Read Data by Command section for details.

RREG: read register data

Description: This command is used to read single or multiple register data. The command consists of a two-byte opcode parameter and the output of the register data. The first byte of the opcode includes the starting address, and the second byte specifies the number of registers to read – 1.

The first command byte: 001r rrr, where rrrrr is the starting address of the first register.

Second command byte: 000n nnnn, where nnnnn is the number of registers to read – 1.

From the 16th falling edge of SCLK, register data appears on DOUT.

The RREG command is shown in Figure 38. Note that a delay of 24 fCLK cycles is required between each byte transaction.

WREG: write register

Description: This command writes single or multiple register data. The command consists of a two-byte opcode parameter and an input of register data. The first byte of the opcode contains the starting address and the second byte specifies the number of registers to write – 1.

The first command byte: 001r rrr, where rrrrr is the starting address of the first register.

Second command byte: 000n nnnn, where nnnnn is the number of registers to write – 1.

Data Bytes: One or more register data bytes, depending on the number of registers specified.

Figure 39 shows the WREG command.

Note that a delay of 24 fCLK cycles is required between each byte transaction.

OFSCAL: offset calibration

Description: This command performs offset calibration. The input of the converter (or input of an external preamplifier) should be zeroed and stabilized before sending this command. After this operation, the offset calibration registers will be updated. See the Calibration Commands section for details.

GANCAL: Gain calibration

Description: This command performs gain calibration. The input to the converter should have a regulated DC input, preferably close to (but not exceeding) positive full scale. The gain calibration register is updated after this operation. See the Calibration Commands section for details.

register map

Register mode (PIN=0) allows read and write access to device registers. In general, the registers contain all the information needed to configure the part, such as data rate, filter selection, calibration, etc. The registers are accessed by the RREG and WREG commands. Registers can be accessed individually or as a block of registers by sending or receiving consecutive bytes.

Configuration Guide

After reset or power-up, the registers can be configured using the following steps:

1. Reset the serial interface. It may be necessary to restore the serial interface before using it (undefined I/O power-up sequence may result in incorrect SCLK detection). To reset the SPI interface, toggle the reset pin, or in read data continuous mode, hold SCLK low for 64 DRDY cycles.

2. Configuration register. Registers are configured by writing to them individually or as a group. Software can be configured in either mode. The STOPC command must be sent before register read/write operations to cancel read data continuous mode.

3. Verify the register data. The registers can be read back to verify device communication.

4. Set the data mode. After register configuration, the device can be configured in Read Data by register mode via the Read Data Continuous command or using the STOPC command to place it in read data continuous mode.

5. Synchronized reading. When synchronization is high, the ADS1282 is free to run data conversion. To stop and restart the conversion, first select Low Sync, then High Sync.

6. Read data. If Read Data Continuous mode is active, data is read directly after DRDY falls by applying SCLK pulses. If read data continuous mode is not active, data can only be read by command. A Read Data command must be sent in this mode to read each conversion result (note that DRDY is only asserted after each Read Data command is sent).

application information

The ADS1282 is a very high resolution ADC. Optimum device performance requires special attention to the design of supporting circuits and printed circuit boards (PCBs). Locate noisy digital components, such as microcontrollers, oscillators, etc., in PCB areas away from converters or front-end components. Placing digital components close to the power entry point keeps digital current paths short and separated from sensitive analog components.

To maintain good total harmonic distortion (THD) and achieve maximum signal-to-noise ratio (SNR), the analog inputs of the ADS1282 must be driven differentially. Also, the capacitors located in the signal path should be low distortion (ceramic gear or equivalent). A typical detector application is shown in Figure 40. The ADS1282 inputs are protected from transient voltages by diode clips or gas discharge tubes. For self-test, low distortion sources are connected to Input 2 (AINP2 and AINN2).

If using a switching dc/dc power supply, check the ADS1282 passband for the power frequency component. Voltage ripple should be kept as low as possible.

Figure 41 shows the digital connections to an FPGA (Field Programmable Gate Array) device. In this example, two ADS1282s are shown connected. The DRDY output of each ADS1282 can be used; however, when the devices are synchronized, the DRDY output of only one device is sufficient. Shared SCLK lines between devices are optional.

from each device connected to the FPGA. For synchronization, the synchronization control line connects all ADS1282 devices. The reset line is also connected to all ADS1282 devices.

For best performance, the FPGA and ads282 should work on the same clock. Avoid ringing on the digital inputs. A 47Ω resistor in series with the digital trace helps reduce ringing by controlling the impedance. Place the resistor on the source (driver) end of the trace. Unused digital inputs should not be floating; tie them directly to DVD or GND.

PW (R-PDSO-G**) Plastic Small Outline Packaging

14 pins shown