feature

Low power, single nanometer digital-to-analog converter; AD5660 : 16-bit; AD5640: 14-bit; AD5620: 12-bit; Guaranteed 12-bit accuracy; On-chip, 1.25 V/2.5 V, 5 ppm/°C reference; tiny 8-lead SOT- 23 , MSOP and LFCSP packages; at 5V, the power supply drops to 480mA , at 3V, the power supply drops to 200mA ; 3V/5V single supply; 16-bit monotonicity guaranteed by design; power-on reset to zero /midscale; 3 power-down functions; serial interface with Schmitt trigger input; rail-to-rail operation; synchronous interrupt facility.

application

Process Control; Data Acquisition Systems; Portable Battery-Powered Instruments; Digital Gain and Offset Adjustment; Programmable Voltage and Current Sources; Programmable Attenuators.

General Instructions

AD5620/AD5640/AD5660, member of the Nano DAC 8482 ; family of devices, low power, single, 12-/14-/16-bit, buffered voltage output DACs guaranteed monotonicity by design.

The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference voltage that provides a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference voltage that provides a full-scale output voltage range of 5V. The reference voltage associated with each part is available from the VREFOUT pin.

These parts include a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or mid-scale (AD5620-3 and AD5660-3) until a valid write occurs . Part power down reduces the device's current consumption to 480NA at 5V and provides software selectable output loads in power down mode. Power consumption is 2.5 mW at 5 V, dropping to 1 microW in power-down mode.

The AD5620/AD5640/AD5660 on-chip precision output amplifiers allow rail-to-rail output swing. User can input for inversion of output amplifier in remote sensing applications. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface, operate at clock frequencies up to 30 MHz, and are compatible with standard SPI 174 ; and QSPI™, Microwire™ and digital signal processor interface standards.

Product Highlights

1. Guaranteed 12-/14-/16-bit nanoDAC-12-bit precision.

2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference.

3. Provide 8-lead SOT-23, MSOP and LFCSP packages.

4. Power-on reset to 0 V or midscale.

5. Precipitation time of 10 microseconds.

Timing Characteristics

All input signals are specified with tr=tf=1 ns/V (10% to 90% V) and timed from a voltage level of (V+V)/2. See Figure 2. V=2.7 V to 5.5 V; all specifications T to T unless otherwise noted.

Absolute Maximum Ratings

TA = 25°C unless otherwise noted.

Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; equipment at these or any other conditions beyond the operating conditions is not implied by this section of this specification. Exposure to absolute long-term maximum rated conditions may affect device reliability.

Typical performance characteristics

the term

Relative accuracy

For DACs, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation (lsb) of a straight line passing through the endpoints of the DAC transfer function. Figures 6 to 8 show typical INLs and codes.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. Monotonicity is assured by differential nonlinearity specified to a maximum of ±1 LSB. The monotonicity of the DAC is guaranteed by design. Figures 9 to 11 show typical DNLs and codes.

Zero code error

A zero code error is a measure of the output error when a zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. Since the output of the DAC cannot go below 0 V, the zero code error is always positive in the AD5620/AD5640/AD5660. This is due to a combination of offset errors in the DAC and output amplifier. Zero-code errors are expressed in millivolts. Figure 20 shows a plot of zero code error versus temperature.

full scale error

Full-scale error is a measure of the output error when the full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V-1 LSB. Full-scale error is expressed as a percentage of full-scale range. Figure 19 shows a plot of full-scale error versus temperature.

gain error

This is a measure of the span error of the DAC. It is the slope deviation of the DAC transfer characteristic from ideal, expressed as a percentage of the full-scale range.

Zero code error drift

This is a way to measure the zero code error as a function of temperature. Expressed in microvolts/degree Celsius.

Gain temperature coefficient

This is a measure of gain error as a function of temperature. Expressed in (ppm of full scale)/°C.

offset error

Offset error is the difference between V (actual value) and VOUT (ideal value) measured in the linear region of the transfer function, expressed in mV. The offset error is measured on the AD5660 and the code 512 is loaded into the DAC register. It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR)

This shows how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. The unit is decibel. VREF remains at 2.5v and VDD varies by ±10%.

Output voltage settling time

This represents the amount of time that the output of the DAC settles to a specified level on a 1/4 to 3/4 full-scale input change. Measured from the 24 falling edges of SCLK.

Digital-to-analog fault pulse

A digital-to-analog fault pulse is a pulse injected into the analog output when the input code in the DAC register changes state. It is usually designated as a fault region in nV-s and is measured when the digital input code is changed by 1lsb at the major carry transition (0x7FFF to 0x8000). See Figures 32 and 33.

digital feedthrough

Digital feedthrough is a measurement of pulses injected from the DAC's digital input into the DAC's analog output, but when the DAC output is not being updated. It is specified in nV-s and is measured by a full-scale code change on the data bus, i.e. from all 0s to all 1s, or vice versa.

noise spectral density

This is a measure of internally generated random noise. Random noise is characterized by spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and measuring the noise at the output. The unit of measurement is nV/√Hz. Figure 38 shows the noise spectral density plot.

theory of operation

Section D/A

The AD5620/AD5640/AD5660 digital-to-analog converters are fabricated using a CMOS process. The structure consists of a string DAC and an output buffer amplifier. These parts include an internal 1.25 V/2.5 V, 5 ppm/°C reference, which is internally increased by 2. Figure 39 shows a block diagram of the DAC architecture.

Because the input encoding of the DAC is straight binary, the ideal output voltage is given by:

where: D is loaded into the DAC register. 0 to 4095 (12 bits) for AD5620; 0 to 16383 (14 bits) for AD5640; 0 to 65535 (16 bits) for AD5660; N is the DAC resolution.

resistor string

The resistor string section is shown in Figure 40. It's just a string of resistors, each with a value of R. The code loaded into the DAC register determines at which node on the string the voltage is tapped into the output amplifier. The voltage is cut off by closing a switch to connect the string to the amplifier. Because it is a string of resistors, monotonicity is guaranteed.

internal reference

The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference voltage giving a full-scale output voltage of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage of 5 V. The reference voltage associated with each part is available from the VREFOUT pin. A buffer is required if the reference output is used to drive an external load. A 100 nF capacitor is recommended between the reference output and GND to ensure reference stability.

output amplifier

The output buffer amplifier can generate rail-to-rail voltages at its output, allowing the output to range from 0v to VDD. The output buffer amplifier has a gain of 2 from a 50 kΩ resistor divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing remote sensing. This VFB pin must be connected to VOUT for proper operation. It can drive a 2 kΩ load in parallel with 1000 pF to GND. Figure 22 shows the source and sink capabilities of the output amplifier. The slew rate is 1.5 V/µsec, and the settling time is 10 µsec from 1/4 to 3/4 full scale.

serial interface

The AD5620/AD5640/AD5660 have a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and MICROWIRE interface standards and most DSPs. A timing diagram of a typical write sequence is shown in Figure 2. Pull the sync line low at the beginning of the write sequence. Data from the data line is recorded to a 16-bit shift register (AD5620/AD5640) or a 24-bit shift register (AD5660) on the falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the AD5620/AD5640/AD5660 compatible with high-speed DSPs. On the 16th falling clock edge (AD5620/AD5640) or the 24th falling clock edge (AD5660), the last data bit is clocked and the programming function is performed, i.e., a change of DAC register contents and/or a change of operating mode is performed . During this phase, the sync line can be held low or high. In both cases, it must be brought up at least 33 ns before the next write sequence so that the falling edge of synchronization can initiate the next write sequence.

Because the sync buffer draws more current when VIN=2v compared to when VIN=0.8v, between two write sequences, SYNC should be idle low for lower power operation of the part. However, as mentioned earlier, synchronization must be improved again before the next write sequence.

input shift register

AD5620/AD5640 type

The input shift registers of the AD5620/AD5640 are 16 bits wide (see Figure 41 and Figure 42). The first two bits are the control bits that control which mode of operation the part is in (normal mode or any of the three power down modes). The next 14/12 bits are the data bits respectively. They are transferred to the DAC register on the falling edge of SCLK 16.

AD5660

The input shift register of the AD5660 is 24 bits wide (see Figure 43). The first six don't care. The next two are control bits that control which mode of operation the part is in (normal mode or any of the three power down modes). See the "Shutdown Modes" section for a more complete description of the various modes. The next 16 bits are the data bits. They are transferred to the DAC register on the falling edge of SCLK 24.

Sync outage

In a normal write sequence to the AD5660, the sync line is held low for at least 24 falling edges of SCLK, and the DAC is updated on 24 falling edges. However, if sync is brought high before the falling edge of 24, this will act as an interruption to the write sequence. The shift register is reset and the write sequence is considered invalid. Neither an update of the DAC register contents nor a change in operating mode occurs (see Figure 44). Similarly, in a normal write sequence for the AD5620/AD5640, the sync line is held low on at least 16 falling edges of SCLK and the DAC is updated on 16 falling edges. However, if sync is brought high before the falling edge of 16 hours, this will act as an interruption to the write sequence.

power-on reset

The AD5620/AD5640/AD5660 family includes a power-on reset circuit that controls the output voltage during power-up. The AD5620/AD5640/AD5660-1-2 DAC output power can reach 0 V, and the AD5620/AD5660-3 DAC output power can reach midscale. The output will remain at this level until a valid write sequence is issued to the DAC, which is useful in applications where it is important to know the state of its output during power-up of the DAC.

Power down mode

The AD5620/AD5640/AD5660 have four independent modes of operation. These modes are software programmable by setting two bits in the control register. Table 7 and Table 8 show how the state of the bits corresponds to the operating mode of the device.

When both bits are set to 0, the part operates normally at 5V and its normal power consumption is 550µA. However, for the three power down modes, the supply current drops to 480NA at 5V (200NA at 3V). Not only does the supply current drop, but the output stage switches from inside the amplifier's output to a resistor network of known value. The advantage is that the output impedance of the component is known when the component is in power down mode. There are three options: the output is internally connected to GND via a 1 kΩ or 100 kΩ resistor, or left open (three states). The output stage is shown in Figure 45.

When the power-down mode is activated, the bias generator, output amplifier, reference, resistor string, and other associated linear circuits are all turned off. However, when powered down, the contents of the DAC registers are not affected. For VDD=5 V and VDD=3 V, the time to exit power down is typically 5 microseconds (see Figure 31).

Microprocessor interface

AD5660 to Blackfin® ADSP-BF53x Interface

Figure 46 shows the serial interface between the AD5660 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family includes two dual-channel synchronous serial ports SPORT1 and SPORT0 for serial and multiprocessor communications. Using SPORT0 to connect to the AD5660, the interface setup is as follows: DT0PRI drives the DIN pins of the AD5660, while TSCLK0 drives the part's SCLK, synchronously driven by TFS0.

AD5660-to-68HC11/68L11 interface

Figure 47 shows the serial interface between the AD5660 and the 68HC11/68L11 microcontroller. The SCK of the 68HC11/68L11 drives the SCLK of the AD5660, and the MOSI output drives the serial data line of the DAC. The sync signal comes from the port line (PC7). The setup conditions for proper operation of this interface are as follows: The 68HC11/68L11 is configured with its CPOL bit set to 0 and the CPHA bit set to 1. When data is transferred to the DAC, the sync line is taken low (PC7). When the 68HC11/68L11 is configured in this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data for the 68HC11/68L11 is transferred in 8-bit bytes with only 8 falling clock edges during the transfer cycle. The data MSB is transferred first. To load data into the AD5660, after the first 8 bits have been transferred, PC7 is held low, a second serial write is performed to the DAC, and at the end of the process, PC7 is taken high.

AD5660-to-80C51/80L51 interface

Figure 48 shows the serial interface between the AD5660 and the 80C51/80L51 microcontroller. The interface settings are as follows: the TxD of the 80C51/80L51 drives the SCLK of the AD5660, and the RxD drives the serial data line of the component. The sync signal again comes from the bit programmable pins on the port. In this case, use port line P3.3. When data is to be transferred to AD5660, P3.3 is taken low. The 80C51/80L51 only transmits data in 8-bit bytes; therefore, only 8 falling clock edges occur during the transmit cycle. To load data into the DAC, P3.3 is held low after the first 8 bits have been sent and a second write cycle is initiated to send the second byte of data. P3.3 rises after this cycle is completed. The 80C51/80L51 outputs the serial data LSB first; however, the AD5660 requires its data to be received with the MSB as the first bit. The 80C51/80L51 transfer routines should take this into account.

AD5660 to Microwire Interface

Figure 49 shows the interface between the AD5660 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5660 on the rising edge of SK.

application information

Use REF19x as

AD5620/AD5640/AD5660

Since the supply current required by the AD5620/AD5640/AD5660 is extremely low, another option is to use a REF19x voltage reference (5V for REF195 or 3V for REF193) to supply the required voltage to the part (see Figure 50). This is especially useful if the power supply is noisy, or if the system supply voltage is not 5 V or 3 V, such as 15 V. REF19x is the regulated supply voltage for the AD5620/AD5640/AD5660 output. If the low dropout REF195 is used, 500 µA of current needs to be supplied to the AD5660. This has no load on the output of the DAC. When the DAC output is loaded, the REF195 must also supply current to the load. The total current required (with a 5 kΩ load on the DAC output) is:

The load regulation of the REF195 is typically 2ppm/mA, which results in an error of 3ppm (15µV) for the 1.5ma current drawn from it. This corresponds to the AD5660's 0.197 LSB error.

Bipolar Operation Using the AD5660

The AD5660 is designed for single-supply operation, but a bipolar output range can also be achieved using the circuit in Figure 51. Figure 51 shows the ±5 V output voltage range. Rail-to-rail operation at the amplifier output can be achieved using the AD820 or OP295 as the output amplifier. The output voltage for any input code can be calculated as:

where D represents the input code in decimal (0 to 65535). When V=5 V, R1=R2=10 kΩ,

This results in an output voltage range of ±5 V, where 0x0000 corresponds to the -5 V output and 0xFFFF corresponds to the +5 V output.

Using the AD5660 as an Isolated, Programmable, 4mA to 20mA Process Controller

In many process control system applications, two-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA to power the transmitter's signal conditioning circuitry. The full-scale output signal of these transmitters is 20 mA. A reverse approach to process control can also be used, where a low-power, programmable current source is used to control remotely located sensors or devices in a loop.

A circuit that performs this function is shown in Figure 52. Using the AD5660 as the controller, the circuit provides a programmable output current of 4 to 20 mA, proportional to the DAC's digital code. The bias voltage for the controller is provided by the ADR02 and requires no external trimming for two reasons: first, the ADR02 has a small initial output voltage tolerance; second, the supply current consumption of both the AD8627 and AD5660 is low. The entire circuit, including the optocoupler, consumes less than 3mA from a total budget of 4mA. The AD8627 regulates the output current to meet the sum of the currents at the non-spinning nodes of the AD8627.

For the values shown in Figure 52,

Where D=0≤D≤65535, when the digital code of AD5660 is equal to 0xFFFF, it provides a full-scale output current of 20 mA. Offset trimming at 4 mA is provided by P2, while P1 provides circuit gain trimming at 20 mA. Because the non-vertical input of the AD8627 is on the virtual ground, the two trims do not interact. Schottky diode D1 is required in this circuit to prevent loop supply transients from pulling the non-inverting input of the AD8627 below 300mV above its inverting input.

Without this diode, this transient could cause phase reversal of the AD8627 and latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum input voltage of the ADR02, which ranges from 12 V to 40 V.

Using the AD5620/AD5640/AD5660 and Galvanically Isolated Interface

For process control applications in industrial environments, a galvanically isolated interface is often required to protect and isolate the control circuit from dangerous common-mode voltages that can occur in the area where the DAC operates. iCoupler® provides isolation in excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire serial logic interface; therefore, the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 53). The power supply to the components must also be isolated, which is done through the use of transformers. On the DAC side of the transformer, a 5 V regulator provides the 5 V required by the AD5620/AD5640/AD5660.

Power Bypass and Ground

When accuracy is important in a circuit, it is helpful to carefully consider the power and ground return layout on the board. A printed circuit board containing the AD5620/AD5640/AD5660 should have separate analog and digital sections, each with its own board area. If the AD5620/AD5640/AD5660 are in a system where other devices require an AGND to DGND connection, the connection should only be made at one point. This ground point should be as close as possible to the AD5620/AD5640/AD5660.

The power supplies to the AD5620/AD5640/AD5660 should be bypassed with 10µF and 0.1µF capacitors. The capacitor should be physically located as close to the device as possible, ideally, the 0.1µF capacitor should be right across from the device. The 10µF capacitors are of the tantalum bead type. Importantly, 0.1µF capacitors have low efficiency series resistance (ESR) and low efficiency series inductance (ESI), which are typical characteristics of common ceramic types of capacitors. This 0.1µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents generated by internal logic switches.

The power cord itself should have as large a trace as possible to provide a low impedance path and reduce the impact of faults on the power cord. Clocks and other components with fast switching digital signals should be isolated from the rest of the board by digital ground. Avoid crossover of digital and analog signals as much as possible. When traces cross on opposite sides of the board, make sure they are at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is microstrip, where the component side of the board is used only for the ground plane, and the signal traces are placed on the solder side. However, this is not always possible with 2-layer boards.

Dimensions