HCPL-540X* 5962...

  • 2022-09-23 10:13:53

HCPL-540X* 5962-89570 HCPL-543X Hermetically sealed, very high speed, logic gate optocoupler

feature

Double Mark Equipment Part Number and Instruction Drawing Number Manufactured and Tested MIL-PRF-38534 Certified Production Line QML-38534, Class H and K Three Sealed Package Configurations Performance Guaranteed Over -55°C to + 125 °C High Speed: 40 M bit /s High Common Mode Rejection 500V /µs Reliable 1500 V DC Withstand Test Voltage Active (Totem Pole) Output Tertiary Output Available High Radiated Immunity HCPL-2400 /30 Functional Compatibility Reliability Data Compatible with TTL, STTL , LSTTL and HCMOS logic families

application

military and space

High reliability system

Transportation, Medical and Life-Critical Systems

High-speed isolated logic system

computer peripheral interface

switching power supply

Isolated Bus Driver (Network Application) - (5400/1 only)

Pulse Transformer Replacement

Ground loop elimination

harsh industrial environment

High-speed disk drive I/O

A/D digital isolation, D/A conversion

illustrate

These units are single and double sealed channel optocouplers. Products are capable of operation and storage over the full military temperature range and are purchased as standard products or with full MIL-PRF-38534 ratings

H or K test or appropriate descriptive diagram. All equipment manufactured and tested on MIL-PRF-38534 certified lines are included in the DESC Compliant Hybrid Manufacturers List QML-38534 Microcircuit. Each channel has an algal light-emitting diode optically coupled to an integrated circuit high-gain photon detector. This combination results in very high

data rate capability. The detector has a hysteretic threshold, typically providing 0.25mA differential mode noise immunity and minimizing output signal potential chatter. The single inter-detector channel unit has a three-state output stage that eliminates the need for a pull-up resistor and allows direct driving of the data bus. All units are compatible with TTL, STTL, LSTTL and HCMOS logic families. 35ns pulse width distortion specification guaranteed at +125°C with 35% pulse width distortion. Figures 13 to 16 show proposed circuits to reduce pulse width distortion and optimize signal rate products. Package Style These parts are 8-pin immersion holes (case profile P), and lead-free ceramic chip carrier (case profile 2). Equipment may be purchased with various lead bending and plating options. See the selection guide table for details. Standard Military Drawings (SMD) each part has packaging and leadership styles. Because the same electronic mold is used (emitter and detector) for each channel of each device listed in this data sheet, the absolute maximum ratings, recommended operating conditions, electrical specifications and performance numbers shown on all parts are similar . There are occasional exceptions to packaging changes and limitations, as described. Add the same packaging components using processes and materials in all equipment. These similarities provide a rationale for the use of data obtained from one part to represent the performance of other parts against mold-related reliability of certain limited radiation test results.

Absolute Maximum Ratings

(No derating required up to +125°C)

Storage temperature range, TS-65°C to +150°C

Operating temperature TA-55°C to +125°C

Case temperature, TC+170°C junction temperature TJ

Lead solder temperature 260°C for 10 seconds

Average forward current if average (per channel) 10mA

Peak input current if PK (per channel) 20mA[1]

Reverse input voltage, VR (each channel) 3 volts

Supply voltage, VCC min 0.0 V, max 7.0 V.

Average output current, IO-min 25mA, max 25mA. (per channel)

Output voltage, VO (per channel)………..- 0.5 V min, 10 V max.

Output power consumption, PO (per channel) 130 mW

Package power consumption, PD (per channel) 200 mW for single channel product only

Tri-state startup voltage, VE-0.5 V min, 10 V max.

Note enable pin 7. An external 0.01µF to 0.1µF bypass capacitor must be connected between VCC and ground for each package type.

Electrical Characteristics

TA = -55°C to +125°C, 4.5 V ≤ VCC ≤ 5.25 V, 6 mA ≤ IF (on) ≤ 10 mA, 0 V ≤ VF (off) ≤ 0.7 V, unless otherwise specified.

All typical values are VCC = 5 V, TA = 25°C, IF = 8 mA unless otherwise noted.

Typical Characteristics Unless otherwise specified, all typical values are TA = 25°C, VCC = 5 V, IF = 8 mA.

parameter restrictions.

1. No more than 5% duty cycle, no more than 50 microsecond pulse width.

2. All devices are considered two terminal devices: measured between all input leads or terminals shorted together and all output leads

3. This is a transient withstand test, not a working condition. Or the terminals are shorted together.

4. The propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5v point on the falling PHL 4.

5. The 1.5 volt point on the rising edge of the output pulse. Pulse width distortion, PWD=|t The propagation delay is measured from the 50% point on the falling edge of the input current pulse to the PLH edge of the output pulse.

6. The output short-circuit duration does not exceed 10 ms. >2.0 volts). O(min) logic high state (V is the maximum slew rate of common-mode voltage that can be maintained at an output voltage of H(VO(MAX) < 0.8v). cm is the maximum slew rate of common-mode voltage that can be maintained at logic low State L5 is maintained at the output voltage.

7. For the desired logic high state, the V device will withstand the line and CC 7. Power supply noise immunity is the peak-to-peak amplitude of the AC ripple voltage on V

8. Measured between adjacent shorted input pairs of each multi-channel device. <0.8v.OL(MAX)>2.0v, VOH(MIN) remains at the desired logic state for the desired logic low state.

9. Every channel.

10. Standard parts are 100% tested at 25°C (groups 1 and 9). SMD and hi rel parts are 100% tested at 25, 125 and -55°C

11. Parameters are tested after design and process changes as part of initial device characterization. Parameters guaranteed (subgroups 1 and 9, 2 and 10, 3 and 11).

12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group

13. The HCPL-6430 and HCPL-6431 dual channel parts work as two independent single channel units. Use single-channel optocouplers with the same part number that switch simultaneously under the same operating conditions.

MIL-PRF-38534 Class H, Class K and DESC SMD Test Procedures HP's Hi Rel Opto; coupler meets MIL-PRF-38534 Class H and K. Therefore, Class H equipment complies with DESC drawings 5962-89570 and 5962-89571. Testing including 100% on-screen display and quality conformance inspection is MIL-PRF-38534. Data Rate and Pulse Definition Propagation delay is the time required to describe the limited advantage of information translation systems changing logic levels from input to output. The Propagation Low-to-High Delay (tPLH) specifies the amount of time the system output changes from a logic 0 to a logic 1, when at the input. The propagation delay from high to low (tPHL) specifies the time required for the system output to go from logic 1 to logic 0, given a stimulus at the input (see Figure 5). When tPLH and tPHL are in value, the pulse width distorts the result. Pulse width distortion is defined as "124tPHL-tPLH" 124 and determines the maximum data volume distortion rate The maximum pulse width distortion 25-35% is typically used to specify the maximum data rate capability or system. The exact exact number depends on the application (RS-232, Powertrain Control Module, T-1, etc.). These high performance optocouplers have specified propagation delay (tPLH, tPHL) and pulse width distortion (124tPLH-tPHL-124;) over temperature as well as supply voltage range.