illustrate

The HCPL-3140 /HCPL-0314 series of devices include circuits of GaAsP light emitting diodes with power output stages optically coupled to integrated circuits. These optocouplers are ideal for driving power igbt mosfet applications for motor control inverters. The high operating voltage range output stage provides gate control. Voltage and current are provided by this optocoupler, which is very suitable for directly driving small and medium power igbt. For higher rated IGBTs, HCPL-3150 (0.5 A) or HCPL-3120 (2.0A) optocouplers can be used.

feature

0.4 A minimum peak output current High-speed response: 0.7µs maximum propagation delay over temperature Ultra-high CMR: 25KV/µs minimum at VCM=1KV Bootstrap Supply current: 3 mA maximum Wide operating temperature range: –40° C to 100 °C wide VCC operating range: 10 V to 30 V over temperature. The range offers DIP8 and SO8 packaging safety approvals: UL Listed, 3750 Vrms for 1 minute. CSA approved. IEC/EN/DIN EN 60747-5-2 certified VIORM=630 V peak (HCPL-3140)

application

Isolated IGBT/Power MOSFET gate drive

AC and Brushless DC Motor Drivers

Inverters for Home Appliances

Industrial inverter

Switching Power Supplies (SMPS)

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3140 Option 060)

Refer to the optocoupler section in the Design Catalogue of Isolation and Control Components, in the Product Safety Regulations section, IEC/EN/ for a detailed description of the partial discharge test profiles for method a and method b, see DIN EN 60747-5-2. Refer to the graph below to understand the relationship between PS and ambient temperature.

Switching Specifications (AC) exceed recommended operating conditions unless otherwise specified.

notes:

1. Linearly reduce the free air temperature above 70°C at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10 microseconds, maximum duty cycle = 0.2%. This value is intended to take into account IO peak design component tolerance min = 0.4 A. See the application section for more details on limiting IOL peaks.

3. Linear derating above 85°C, free air temperature is 4.0 mW/°C.

4. Input power consumption does not require derating.

5. Maximum pulse width = 50 microseconds, maximum duty cycle = 0.5%.

6. In this test, VOH is measured with DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps.

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.

8. According to UL 1577, each optocoupler is verified by applying insulation test voltage ≥ 4500 Vrms for 1 second (leak test current limit II-O ≤ 5μA). This test is performed prior to the partial discharge 100% production test (Method B) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).

9. The device is considered a two-terminal device: the pins on the inputs are shorted together and the pins on the output are shorted together.

10. PDD refers to the difference between tPHL and tPLH between any two components or channels under the same experimental conditions.

11. Common mode transient immunity is the maximum allowable value of common mode pulse VCM to ensure that the output will remain high (ie Vo>6.0V).

12. Common Mode Transient Immunity in Low State is the maximum allowable dVCM/dt of the common mode pulsed VCM to ensure that the output will remain in the low state (ie Vo<1.0V).

13. This load condition approximates the gate load of a 1200 V/25 a IGBT.

14. When the operating frequency and Qg of the driving IGBT increase, the power supply current increases.

Application Information Elimination of Negative IGBT Gate Drive For firm IGBT turn-off, HCPL-3140/HCPL-0314 have very low maximum volume 1.0v. Minimum specification Rg and lead inductance HCPL-3140/HCPL-0314 to IGBT gate and emitter A negative IGBT gate drive application can be eliminated by mounting a small PC board IGBT directly above the HCPL-3140/HCPL-0314, possibly by mounting a, as shown in Figure 19. Care should be taken with such a PC board design to avoid routing of the IGBT collector or emitter traces close to the HCPL-3140/HCPL-0314 input components which can cause unwanted transient signal coupling to the input of the HCPL-3140/HCPL-0314 and degradation. (If the IGBT drain must be routed at the HCPL-3140/HCPL-0314 input, then the LED should be reversed in the off state with a bias to prevent transient signals from coupling from the IGBT drain from the HCPL-3140/HCPL-0314 on.)

Select Gate Resistor (Rg) Step 1: Calculate the Rg minimum value based on the IOL peak specification. The Rg of the IGBT in Figure 19 can be analyzed as the voltage supplied by a simple RC circuit HCPL-3140/HCPL-0314.

The volume value of 5 V in the above formula is the volume current at the peak of 0.6A (see Figure 6). Step 2: Check HCPL-3140/HCPL-0314 power consumption and increase Rg if necessary. HCPL-3140/HCPL-0314 Total Power Dissipation (PT) is equal to Emitter Power (PE) and Output Power (PO).

where KICC•Qg•f is the ICC increase due to switching, and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case) = 10 mA, Rg = 32Ω, max duty cycle = 80%, Qg = 100 nC, f = 20 kHz, TAMAX = 85°C:

In the previous formula, the 3ma value of ICC is the entire operating temperature range. Since PO in this case is less than PO(MAX), Rg=32Ω for power dissipation.

LED Driver Circuit Considerations Ultra High CMR Performance Without Detector Shielded Optocoupler The main cause of CMR failure is capacitive coupling of the optocoupler from the input side, through the package, to the detector IC as shown in Figure 21. The HCPL-3140/HCPL-0314 improvements divert capacitively coupled current away from sensitive ICs by using a transparent Faraday shield for the detector IC. However, this shield does not eliminate the capacitance of the LED with optocoupler pins 5-8 as shown in Figure 22. This capacitive coupling causes LED current mode transients when disturbing the common shield optocoupler and becomes a major source of CMR failure. The main design goal of high CMR is that the LED driver circuit changes to maintain the state (on or off) of the LED during normal common mode transients. For example, the proposed application circuit (Figure 19) can achieve 10 kV/µs CMR while minimizing component complexity. Keeping the LEDs in the proper state of technology is in the next two sections.

CMR with LED (CMRH) A high CMR LED driver circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED beyond the input current so that it does not pull the threshold below a critical value briefly. A minimum LED current of 8 mA provides sufficient margin to a maximum of 5 mA to achieve a CMR of 10 kV/µs. CMR (CMRL) high when LED is off The CMR LED driver circuit must maintain mode transients during LED off (VF ≤ VF(off)). For example, in the -dVCM/dt transient in Figure 23, water flows through the RSAT and VSAT logic gates that pass through CLEDP. As long as the low resulting state voltage of the logic gate is less than VF(off) the LED will remain off and no common mode fault will occur. The open collector driver circuit, shown in Figure 24, cannot save a+dVCM/dt during which the LED goes off temporarily, because all current flowing through the Clayton must be supplied by the LED. Not recommended for applications requiring extremely high CMR1 performance . This alternative drive circuit is like the recommended application circuit (Figure 19), and is turned off to achieve ultra-high CMR shunting performance. IPM Dead Time and Propagation Delay Specifications The HCPL-3140/HCPL-0314 includes a Propagation Delay Difference (PDD) specification designed to help designers minimize their "dead time" power inverter designs. Dead time is the time the high and low side power transistors turn off.

Any overlapping conduction in Q1 and Q2 will result in power device rails flowing through the motor from high voltage to low voltage. To minimize dead time for a given design, turning on LED2 should be delayed (relative to turning off LED1) so that in the worst case, transistor Q1 just turns off when transistor Q2 is on, as shown in Figure 26. The amount of delay condition necessary to achieve this is equal to the maximum propagation delay difference specification, PDD max, which is specified for a 500 ns operating temperature range of -40° to 100°C. Delaying the LED signal maximum propagation delay variance ensures that the minimum dead time is zero, but does not tell the designer that the maximum dead time is . This maximum dead time is equal to the difference between the maximum and minimum propagation delay specifications as shown in Figure 27. The maximum fatality time for HCPL-3140/HCPL -0314 is 1 microsecond (= 0.5 microseconds - (-0.5 microseconds) over the operating temperature range of -40°C to 100°C. Note that propagation delay is used to calculate PDD and dead time are equal to temperature and test conditions because the optocouplers considered below are usually mounted close to each other and swap the same IGBTs.