feature

Correlated Double Sampler (CDS); 0dB to 18dB Pixel Gain Amplifier (PxGA); 6dB to 42dB 10-bit Variable Gain Amplifier (VGA); 10-bit 25 MSPS A/D Converter; with Variable Level Controlled black level clamp; complete on-chip timing driver; 800 ps resolution precision timing core; on-chip 3V level and RG drivers; 40-lead LFCSP package.

application

Digital cameras; high-speed digital imaging applications.

General Instructions

The AD9948 is a highly integrated CCD signal processor for digital camera applications. Specified at pixel rates up to 25 MHz, the AD9948 consists of a complete analog front end with A/D conversion, combined with programmable timing drivers. Precision timing cores allow high 800 ps resolution speed clocks.

The analog front end includes black level clamp, CDS, PxGA, VGA and 25 MHz 10-bit A/D converter. Timing drivers provide high-speed CCD clock drivers for RG and H1-H4. Operation is programmed using a 3-wire serial interface.

Packaged in a space-saving 40-lead LFCSP package, the AD9948 operates over the –20°C to +85°C temperature range.

the term

Differential Nonlinearity (DNL)

An ideal ADC shows code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, each code must have a limited width. Guaranteed no missing codes at 10-bit resolution means that all 1024 codes must be present separately under all operating conditions.

peak nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the AD9948's output from a true straight line. The point used as the zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as 1 LSB and 0.5 LSB beyond the last code transition. Measure the deviation from the middle of each specific output code to a true straight line. The error is then expressed as a percentage of the full-scale signal of the 2v ADC. The input signal is always appropriately amplified to meet the full-scale range of the ADC.

total output noise

The rms output noise is measured using the histogram technique.

The standard deviation of the ADC output code is calculated in LSB and represents the rms noise level of the entire signal chain at a specified gain setting. Using this relationship, the output noise can be converted into an equivalent voltage:

where n is the bit resolution of the ADC. For the AD9948, 1 LSB is approximately 1.95 mV.

Power Supply Rejection (PSR)

PSR is measured by a step change applied to the power supply pin. The PSR specification is calculated from the change in the data output for a given supply voltage step change.

Typical Performance Characteristics - AD9948

System Overview

Figure 1 shows the year 9948 AD. The CCD output is processed by the AD9948's AFE circuit, which consists of a CD, a PxGA, a VGA, a black level clamp, and an a/D converter. The digitized pixel information is sent to the digital image processor chip, where all post-processing and compression takes place. To operate the CCD, the CCD timing parameters are programmed into the AD9948 from the image processor through a 3-wire serial interface. The system master clock CLI provided by the image processor, AD9948 generates the high speed CCD clock and all internal AFE clocks. All AD9948 clocks are synchronized to VD and HD. All AD9948 horizontal pulses (CLPOB, PBLK, and HBLK) are programmed and generated internally.

H drivers for H1-H4 and RG are included in the AD9948, allowing these clocks to be connected directly to the CCD. The AD9948 supports an H drive voltage of 3 V.

Figure 2a shows the horizontal and vertical counter dimensions of the AD9948. All internal horizontal clocks are programmed with these dimensions to specify line and pixel positions.

Serial interface timing

All internal registers of the AD9948 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data word. Both 8-bit addresses and 24-bit data words are written from the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 3a. Although many registers are less than 24 bits wide, all 24 bits must be written for each register. If the register is only 16 bits wide, then the upper 8 bits are irrelevant and can be filled with zeros during the serial write operation. If less than 24 bits of data are written, the registers will not be updated with the new data.

Figure 3b shows a more efficient method of writing data to a register using the AD9948's address auto-increment feature. Using this method, the lowest address required is written first, followed by multiple 24-bit data words. Each new 24-bit data word will be automatically written to the next highest register address. Faster register loads can be achieved by eliminating the need to write to each 8-bit address. Address auto-increment can be used from any register location, and can be used to write to two or the entire register space.

complete register list

All addresses and default values are in hexadecimal. All registers are VD/HD updated as shown in Figure 3a, except for the registers shown in Table I, which are SL updated.

Precise timing high-speed timing generation

The AD9948 uses a precision timing core to generate flexible high-speed timing signals. This core is the basis for generating timing for the CCD and AFE; reset gate RG, horizontal drivers H1-H4 and SHP/SHD sampling clock. The unique architecture allows system designers to optimize image quality with precise control of horizontal CCD readout and AFE-correlated double sampling.

Timing resolution

The precision timing core uses the 1× master clock input (CLI) as a reference. This clock should be the same frequency as the CCD pixel clock. Figure 4 illustrates how the internal timing core divides the master clock cycle into 48 steps or edge locations. Therefore, the edge resolution of the precision timing kernel is (tCLI/48). See the Application Information section for more information on using the CLI input.

High-speed clock programmability

Figure 5 shows how the high-speed clocks RG, H1-H4, SHP and SHD are generated. The RG pulse has programmable rising and falling edges and can be inverted using polarity control. Horizontal clocks H1 and H3 have programmable rising and falling edges, and polarity control. H2 and H4 are always clocked opposite to H1 and H3, respectively. Table X summarizes the high-speed timing registers and their parameters.

The width of each edge position setting is 6 bits, but only 48 valid edge positions are available. Therefore, the register values are mapped into four quadrants, each containing 12 edge locations. Table XI shows the correct register values for the corresponding edge locations.

H driver and RG output

In addition to programmable timing positions, the AD9948 has on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD input. Adjustable H driver and RG driver current

by using

DRV Control Register (Address x062). The DRV control register is divided into five different 3-bit values, each adjustable in 4.1 mA increments. The minimum setting of 0 is equal to off or three states, and the maximum setting of 7 is equal to 30.1 mA.

As shown in Figure 6, H2/H4 outputs are opposite to H1/H3. The internal propagation delay caused by signal inversion is less than 1 ns, which is significantly less than the typical rise time of driving a CCD load. This results in an H1/H2 crossover voltage at about 50% of the output swing. Crossover voltage is not programmable.

digital data output

A dual-phase register (address x064) is available for the AD9948 data output stage. Any edge between 0 and 47 is programmable, as shown in Figure 7a. The pipeline delay digital data output is shown in Figure 7b.

The AD9948 data output phase is programmable using the dual phase register (address x064). Any edge from 0 to 47 can be programmed as shown in Figure 7a. The pipeline delay for digital data output is shown in Figure 7b.

Horizontal clamping and blanking

The AD9948's horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Define separate sequences for each signal, which are then organized into regions during image readout. This allows changing dark pixel clamping and blanking patterns at each stage of readout to accommodate different image transfer timings and high-speed line movements.

A single CLPOB and PBLK sequence AFE level timing consists of CLPOB and PBLK as shown in Figure 8. These two signals are independently programmed using the parameters shown in Table XII. Start polarity, first toggle position and second toggle position are fully programmable for each signal. The CLPOB and PBLK signals are active low and should be programmed accordingly. Up to four separate sequences can be created per signal.

A single HBLK sequence

The programmable timing of HBLK shown in Figure 9 is similar to CLPOB and PBLK. However, no polarity control is activated. Only the toggle positions are used to specify the start and stop positions of the blanking period. In addition, there is a polarity control, the HLBK mask, which specifies the polarity of the horizontal clock signals H1-H4 during the blanking period. As shown in Figure 10, setting HBLKEMAX high will set H1=H3=low and H2=H4=high during blanking. HBLK can use up to four separate sequences.

Generate special HBLK patterns

Six toggle positions are available for HBLK. Typically, only two toggle positions are used to generate standard HBLK intervals. However, additional toggle positions can be used to generate special HBLK patterns, as shown in Figure 11. The pattern in this example uses all six switching positions to generate two additional sets of pulses during the HBLK interval. By changing the toggle position, different modes can be created.

Horizontal sequence control

The AD9948 uses sequence change positions (SCPs) and sequence pointers (SPTRs) to organize individual horizontal sequences. Up to four scps can be used to divide the readout into four separate regions, as shown in Figure 12. SCP 0 is always hardcoded to line 0, SCP1–SCP3 are register programmable. Within each region defined by the SCP, the SPTR register specifies the sequence used by each signal. CLPOB, PBLK, and HBLK each have a separate set of SCPs. For example, CLPOBSCP1 will define region 0 for CLPOB, and in this region any of four separate CLPOB sequences can be selected using the CLPOBSPTR register. The next SCP defines a new area and in this area each signal can be assigned to a different individual sequence. The sequence control registers are summarized in Table XIV.

External HBLK signal

The AD9948 can also be used with an external HBLK signal. Setting the HBLKDIR register (address x040) high will disable the internal HBLK signal generation. Use the HBLKPOL register to specify the polarity of the external signal and the HBLKMASK register to specify the mask polarity of H1. Table XV summarizes the register values when using the external HBLK signal.

H counter synchronization

The H counter reset occurs seven CLI cycles after the falling edge of HD. The PxGA steering is synchronized with the internal H counter reset (see Figure 13).

Recommended Power-Up Sequence

When the AD9948 is powered up, the following sequence is recommended (see Figure 14 for each step):

1. Turn on the power of the AD9948.

2. Apply master clock input, CLI, VD and HD.

3. Although the AD9948 includes an on-chip power-on reset, a software reset of the internal registers is recommended. Write 1 to the SW_RST register (address x010), which resets all internal registers to their default values. This bit is self-clearing and will automatically reset back to 0.

4. The precision timing core must be reset by writing a 0 to the TGCORE_RSTB register (address x012) followed by a l to the TGCORE_RSTB register. This will start the internal timing core operation.

5. Write 1 to the update prevention register (address x014). This will prevent the serial register data from being updated.

6. Write the required registers to configure high-speed timing and horizontal timing.

7. Write 1 to the output control register (address x011). This will allow the output to become active after the next rising edge of VD/HD.

8. Write 0 to the update prevention register (address x014). This will allow serial information to be updated on the next VD/HD falling edge.

The next falling edge of VD/HD allows register updates to occur, including OUT U controls that make all clock outputs available.

Mock front end description and operation

The AD9948 signal processing chain is shown in Figure 15. Each processing step is critical to obtain high-quality images from raw CCD pixel data.

DC reduction

In order to reduce the large DC offset of the CCD output signal, a DC recovery circuit with an external 0.1μF series coupling capacitor is used. This will restore the DC level of the CCD signal to about 1.5v for compatibility with the AD9948's 3v supply voltage.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract video information and suppress low-frequency noise. The timing shown in Figure 5 illustrates how the reference level and the CCD signal level are sampled using two internally generated CDS clocks, SHP and SHD, respectively. The location of the SHP and SHD sample edges is determined by the setting of the SAMPCONTROL register at Address 0x63. The placement of these two clock signals is critical to get the best performance from the CCD.

By default, the gain of CDS is fixed at 0db. Using bits D10 and D11 in the AFE operation register, the gain can be reduced to -2db or -4db. This will allow the AD9948 to accept input signals greater than 1V pp. See Table VIII for register details.

PxGA

PxGA provides individual gain adjustments for each color pixel. PxGA is a programmable gain amplifier with four independent values that can multiplex its gain values on a pixel-to-pixel basis (see Figure 16). This allows lower output color pixels to be obtained to match higher output color pixels. Additionally, PxGA can be used to adjust the white balance of colors, reducing the amount of digital processing required. Four different gain values are switched according to the color control circuit. In the AFE CTLMODE register at address 0x03, different color control modes for three different types of CCD color filter arrays can be programmed (see Figures 18a to 18c for timing examples). For example, the progressive steering mode accommodates the popular Bayer red, green and blue filters (see Figure 17a).

The same Bayer pattern can also be interlaced, which should be used with this type of CCD (see Figure 17b). The color control performs proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user using vertical (VD) and horizontal (HD) sync pulses. See Figure 18b for timing information.

The third type of readout is divided into three distinct readout areas using the Bayer pattern. This type of CCD should use the three-field mode (see Figure 17c). The color control performs proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the user using vertical (VD) and horizontal (HD) sync pulses. See Figure 18c for timing information.

The PxGA gain for each of the four channels changes from 0db to 18db in 512 steps, specified using the PxGA GAIN01 and PxGA GAIN23 registers. The PxGA gain curve is shown in Figure 19. The PxGA GAIN01 register contains 9 bits for PxGA Gain0 and Gain1, and the PxGA GAIN23 register contains 9 bits for PxGA Gain2 and Gain3.

Variable Gain Amplifier

The VGA stage offers a gain range of 6dB to 42dB and is programmable with 10-bit resolution via the serial digital interface. A minimum gain of 6db is required to match the 1v input signal to the ADC full scale range of 2v. Compared to a 1v full-scale system, the equivalent gain range is 0db to 36db.

The VGA gain curve follows a linear in-dB characteristic. The exact VGA gain for any gain register value can be calculated using the formula:

where the code range is 0 to 1023.

There is a limit to the maximum amount of gain that can be applied to the signal. PxGA can add up to 18dB, while VGA can provide up to 42dB. However, the maximum total gain from PxGA and VGA is limited to 42db. If the register is programmed to specify an overall gain greater than 42dB, the overall gain will be clipped to 42dB.

A/D converter

The AD9948 utilizes a high performance ADC architecture optimized for high speed and low power consumption. Differential nonlinearity (DNL) performance is typically better than 0.5lsb. The ADC uses a 2 V input range. Typical linearity and noise performance curves for the AD9948 are shown in TPC 1 and TPC 2.

Optical black clip

An optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency changes in the CCD black level. During optical black (masked) pixel intervals on each line, the ADC output is compared to a fixed black level reference selected by the user in the clamp register.

This value is programmable between 0 LSB and 63.75 LSB in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input via a D/A converter. Typically, the optical black clip loop is opened once per horizontal line, but this loop can be updated more slowly to suit specific applications. If an external digital clamp is used during postprocessing, the AD9948 optical black clamp can be disabled using Bit D2 in the OPRMODE register. When the loop is disabled, the clamp register can still be used to provide programmable offset adjustment.

The CLPOB pulse should be placed during the optical black pixel of the CCD. It is recommended that the CLPOB pulse duration be at least 20 pixels wide to minimize clamping noise. Shorter pulse widths can be used, but clamping noise may increase and the ability to track low frequency changes in black level will be reduced. See the Horizontal Clamping and Blanking and Application Information sections for timing examples.

digital data output

The AD9948 digital output data is latched using a bi-phase register value, as shown in Figure 15. The output data timing is shown in Figure 7. The output latch can also be made transparent so that the data output is immediately available from the A/D converter. Programming AFE Control Register Bit D4 to 1 will set the output latch transparent. Data output (three states) can also be disabled by setting AFE Control Register Bit D3 to 1.

The data output encoding is usually straight binary, but by setting bit D5 of the AFE control register to 1, the encoding will be grayed out.

Application Information Circuit Configuration

The recommended circuit configuration for the AD9948 is shown in Figure 21. Getting good image quality from the AD9948 requires careful attention to the PCB layout. All signals should be routed to maintain low noise performance. The CCD output signal should be routed directly to Pin 27 through a 0.1µF capacitor. The master clock, CLI, should be carefully routed to pin 25 to minimize interference with the CCDIN, REFT, and REFB signals.

The digital outputs and clock inputs are on pins 2 to 13 and pins 31 to 39 and should be connected to the digital ASIC away from the analog and CCD clock signals. Placing series resistors near the digital output pins may help reduce digital transcoding noise. If the digital outputs must drive loads greater than 20pf, buffering is recommended to minimize additive noise. If the digital ASIC can accept gray code, the output of the AD9948 can be selected to output the data in gray code format using control register bit D5. Compared to binary encoding, grayscale encoding helps reduce potential digitization noise.

The H1-H4 and RG traces should have low inductance to avoid excessive signal distortion. Due to the large transient current requirements of H1-H4 due to the CCD capacitive load, it is recommended to use heavier traces. If possible, physically positioning the AD9948 closer to the CCD will reduce the inductance on these lines. As always, the routing path from the AD9948 to the CCD should be as direct as possible.

Grounding and Decoupling Recommendations

As shown in Figure 21, the AD9948 recommends a single ground plane. The ground plane should be as continuous as possible, especially around pins 23 to 30. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All high frequency decoupling capacitors should be placed as close as possible to the package pins. It is recommended to solder the exposed baffle on the bottom of the package to a large pad with multiple vias between the pad and the ground plane.

All power pins must be grounded with high quality high frequency chip capacitors. There should also be bypass capacitors of 4.7µF or larger for each main supply AVDD, RGVDD, HVDD, and DRVDD, although this is not necessary for each individual pin. In most applications, it is easier to share the power supply for RGVDD and HVDD, which can be done by bypassing the individual power supply pins individually. A separate 3V supply can be used for DRVDD, but this supply pin should still be disconnected to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended.

The reference bypass pins (REFT, REFB) should be separated from ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be close to the pin.

Drive CLI input

The master clock input (CLI) of the AD9948 can be used in two different configurations, depending on the application. Figure 23a shows a typical dc-coupled input from a master clock source. The master clock signal should be at standard 3v CMOS logic levels when using DC coupled techniques. As shown in Figure 23b, a 1000 pF ac coupling capacitor can be used between the clock source and the CLI input. In this configuration, the CLI input will be self-biased to an appropriate DC voltage level of about 1.4v. When using AC coupling technology, the amplitude of the master clock signal can be as low as ±500mv.

Horizontal Timing Example

Figure 24 shows an example of a CCD layout. The horizontal register contains 28 dummy pixels that will appear on each line clocked from the CCD. In the vertical direction, there are 10 black (OB) lines at the front end of the readout and 2 black (OB) lines at the back end of the readout. The horizontal direction has four OB pixels in the front and 48 in the back.

To configure the AD9948 horizontal signal for this CCD, three sequences can be used. Figure 25 shows the first sequence used during vertical blanking. During this time, the sensor has no valid OB pixels, so the CLPOB signal is not used. During this time, PBLK may be enabled because no valid data is available.

Figure 26 shows the recommended order of vertical OB intervals. To stabilize the clamp loop of the AD9948, the clamp signal is applied to the entire line.

Figure 27 shows the recommended order for valid pixel readout. The 48 OB pixels at the end of each row are used for CLPOB signals.

Dimensions

40 lead frame chip scale package; 6mm 6mm body (CP-40); dimensions are in millimeters